commit 637b373acd121592fa4c8deb5b15703771ac2e97
author Tor Jeremiassen <torerik@google.com> Tue Jan 28 16:41:08 2025 -0800
committer Tor Jeremiassen <torerik@google.com> Tue Jan 28 17:13:19 2025 -0800
tree a24bea0dd58774cdc031a256d92d4e6be766026d
parent ee332aa13b60b044cd3d278745867c32e4e2a6f4

Fixed bug in previous commit when adding unimp and c.unimp instructions

PiperOrigin-RevId: 720750716
Change-Id: I3dc630b166cfd6d0c1a95d4bd3d4a12fe5f4a48a

cheriot/riscv_cheriot.bin_fmt

diff --git a/cheriot/riscv_cheriot.bin_fmt b/cheriot/riscv_cheriot.bin_fmt
index 249f80c..3859033 100644
--- a/cheriot/riscv_cheriot.bin_fmt
+++ b/cheriot/riscv_cheriot.bin_fmt
@@ -281,12 +281,12 @@
   amominuw : AType  : func5 == 0b1'1000, func3 == 0b010, opcode == 0b010'1111;
   amomaxuw : AType  : func5 == 0b1'1100, func3 == 0b010, opcode == 0b010'1111;
   // RiscV32 CSR manipulation instructions.
-  csrrw    : IType  : func3 == 0b001, rd != 0,  opcode == 0b111'0011;
+  csrrw    : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd != 0,  opcode == 0b111'0011;
   csrrs    : IType  : func3 == 0b010, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrc    : IType  : func3 == 0b011, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrs_nr : IType  : func3 == 0b010, rs1 != 0, rd == 0, opcode == 0b111'0011;
   csrrc_nr : IType  : func3 == 0b011, rs1 != 0, rd == 0, opcode == 0b111'0011;
-  csrrw_nr : IType  : func3 == 0b001, rd == 0,  opcode == 0b111'0011;
+  csrrw_nr : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd == 0, opcode == 0b111'0011;
   csrrs_nw : IType  : func3 == 0b010, rs1 == 0, opcode == 0b111'0011;
   csrrc_nw : IType  : func3 == 0b011, rs1 == 0, opcode == 0b111'0011;
   csrrwi   : I2Type : func3 == 0b101, rd != 0,  opcode == 0b111'0011;
@@ -297,7 +297,7 @@
   csrrwi_nr: I2Type : func3 == 0b101, rd == 0,  opcode == 0b111'0011;
   csrrsi_nw: I2Type : func3 == 0b110, i_uimm5 == 0, opcode == 0b111'0011;
   csrrci_nw: I2Type : func3 == 0b111, i_uimm5 == 0, opcode == 0b111'0011;
-  unimp    : IType  : func3 == 0b001, rs1 == 0, rd == 0, opcode == 0b111'0011;
+  unimp    : IType  : func3 == 0b001, u_imm12 == 0b1100'0000'0000, rs1 == 0, rd == 0, opcode == 0b111'0011;
   // RiscV32 Privileged instructions.
   mret    : Inst32Format  : bits == 0b001'1000'00010'00000'000'00000, opcode == 0b111'0011;
   wfi     : Inst32Format  : bits == 0b000'1000'00101'00000'000'00000, opcode == 0b111'0011;

cheriot/test/riscv_cheriot_encoding_test.cc

diff --git a/cheriot/test/riscv_cheriot_encoding_test.cc b/cheriot/test/riscv_cheriot_encoding_test.cc
index 8b58730..33616e7 100644
--- a/cheriot/test/riscv_cheriot_encoding_test.cc
+++ b/cheriot/test/riscv_cheriot_encoding_test.cc
@@ -370,6 +370,8 @@
   enc_->ParseInstruction(kCsrci);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32Cheriot, 0),
             OpcodeEnum::kCsrrciNw);
+  enc_->ParseInstruction(kCsrw | 0xc00'00000);
+  EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32Cheriot, 0), OpcodeEnum::kUnimp);
 }
 
 TEST_F(RiscVCheriotEncodingTest, RV32MOpcodes) {
@@ -499,6 +501,8 @@
   enc_->ParseInstruction(kCebreak);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32Cheriot, 0),
             OpcodeEnum::kCebreak);
+  enc_->ParseInstruction(0x0000);
+  EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32Cheriot, 0), OpcodeEnum::kCunimp);
 }
 
 TEST_F(RiscVCheriotEncodingTest, RiscVCheriotOpcodes) {