diff --git a/cheriot/cheriot_top.cc b/cheriot/cheriot_top.cc
index 2a5edae..3557f96 100644
--- a/cheriot/cheriot_top.cc
+++ b/cheriot/cheriot_top.cc
@@ -193,7 +193,7 @@
   rv_bp_manager_ = new riscv::RiscVBreakpointManager(
       rv_action_point_manager_,
       [this](HaltReason halt_reason) { RequestHalt(halt_reason, nullptr); });
-  // Set the software breakpoint callback.
+  // Set the software action callback.
   state_->AddEbreakHandler([this](const Instruction *inst) {
     if (rv_action_point_manager_->IsActionPointActive(inst->address())) {
       // Need to request a halt so that the action point can be stepped past
@@ -275,7 +275,6 @@
 
 absl::Status CheriotTop::StepPastBreakpoint() {
   uint64_t pc = state_->pc_operand()->AsUint64(0);
-  uint64_t bpt_pc = pc;
   // Disable the breakpoint.
   rv_action_point_manager_->WriteOriginalInstruction(pc);
   // Execute the real instruction.
@@ -294,11 +293,11 @@
   real_inst->DecRef();
   // Re-enable the breakpoint.
   // Re-enable the breakpoint.
-  rv_action_point_manager_->WriteBreakpointInstruction(bpt_pc);
+  rv_action_point_manager_->WriteBreakpointInstruction(pc);
   // Get the next pc value.
-  uint64_t pcc_val = pcc_->data_buffer()->Get<uint32_t>(0);
   if (state_->branch()) {
     state_->set_branch(false);
+    uint64_t pcc_val = pcc_->data_buffer()->Get<uint32_t>(0);
     AddToBranchTrace(pc, pcc_val);
     next_pc = pcc_val;
     if (break_on_control_flow_change_) {
@@ -350,7 +349,7 @@
     SetPc(pc);
     auto *inst = cheriot_decode_cache_->GetDecodedInstruction(pc);
     // Set the next_pc to the next sequential instruction.
-    next_pc += inst->size();
+    next_pc = pc + inst->size();
     bool executed = false;
     do {
       executed = ExecuteInstruction(inst);
@@ -452,7 +451,7 @@
       SetPc(pc);
       // Set the PC destination operand to next_seq_pc. Any branch that is
       // executed will overwrite this.
-      next_pc += inst->size();
+      next_pc = pc + inst->size();
       bool executed = false;
       do {
         // Try executing the instruction. If it fails, advance a cycle
diff --git a/cheriot/riscv_cheriot_i_instructions.cc b/cheriot/riscv_cheriot_i_instructions.cc
index 16bf8cc..062879d 100644
--- a/cheriot/riscv_cheriot_i_instructions.cc
+++ b/cheriot/riscv_cheriot_i_instructions.cc
@@ -42,7 +42,8 @@
   db->DecRef();
   // See if the instruction is interpreted as 32 or 16 bit instruction.
   if ((inst_word & 0b11) != 0b11) inst_word &= 0xffff;
-  LOG(INFO) << "RiscVIllegalInstruction: " << std::hex << inst_word;
+  LOG(INFO) << "RiscVIllegalInstruction at: [" << std::hex << inst->address()
+            << "] " << inst_word;
   state->Trap(/*is_interrupt=*/false, /*trap_value=*/inst_word,
               *EC::kIllegalInstruction,
               /*epc=*/inst->address(), inst);