No public description PiperOrigin-RevId: 795167890 Change-Id: I19589d6175869aed33bbf954d745e55a49192c59

diff --git a/cheriot/cheriot_cli_forwarder.cc b/cheriot/cheriot_cli_forwarder.cc
index 7f94943..e91b7a6 100644
--- a/cheriot/cheriot_cli_forwarder.cc
+++ b/cheriot/cheriot_cli_forwarder.cc

@@ -35,13 +35,13 @@
 using HaltReasonValueType =
     ::mpact::sim::generic::CoreDebugInterface::HaltReasonValueType;
 
-CheriotCLIForwarder::CheriotCLIForwarder(CheriotRenodeCLITop *cheriot_cli_top)
+CheriotCLIForwarder::CheriotCLIForwarder(CheriotRenodeCLITop* cheriot_cli_top)
     : cheriot_cli_top_(cheriot_cli_top) {}
 
 // Forward the calls to the CheriotRenodeCLITop class - CLI methods.
 
 absl::StatusOr<size_t> CheriotCLIForwarder::ReadTagMemory(uint64_t address,
-                                                          void *buf,
+                                                          void* buf,
                                                           size_t length) {
   return cheriot_cli_top_->CLIReadTagMemory(address, buf, length);
 }
@@ -113,29 +113,29 @@
 
 // Read/write the named registers.
 absl::StatusOr<uint64_t> CheriotCLIForwarder::ReadRegister(
-    const std::string &name) {
+    const std::string& name) {
   return cheriot_cli_top_->CLIReadRegister(name);
 }
 
-absl::Status CheriotCLIForwarder::WriteRegister(const std::string &name,
+absl::Status CheriotCLIForwarder::WriteRegister(const std::string& name,
                                                 uint64_t value) {
   return cheriot_cli_top_->CLIWriteRegister(name, value);
 }
 
-absl::StatusOr<DataBuffer *> CheriotCLIForwarder::GetRegisterDataBuffer(
-    const std::string &name) {
+absl::StatusOr<DataBuffer*> CheriotCLIForwarder::GetRegisterDataBuffer(
+    const std::string& name) {
   return cheriot_cli_top_->CLIGetRegisterDataBuffer(name);
 }
 
 // Read/write the buffers to memory.
 absl::StatusOr<size_t> CheriotCLIForwarder::ReadMemory(uint64_t address,
-                                                       void *buf,
+                                                       void* buf,
                                                        size_t length) {
   return cheriot_cli_top_->CLIReadMemory(address, buf, length);
 }
 
 absl::StatusOr<size_t> CheriotCLIForwarder::WriteMemory(uint64_t address,
-                                                        const void *buf,
+                                                        const void* buf,
                                                         size_t length) {
   return cheriot_cli_top_->CLIWriteMemory(address, buf, length);
 }
@@ -156,7 +156,7 @@
   return cheriot_cli_top_->CLIClearAllSwBreakpoints();
 }
 
-absl::StatusOr<Instruction *> CheriotCLIForwarder::GetInstruction(
+absl::StatusOr<Instruction*> CheriotCLIForwarder::GetInstruction(
     uint64_t address) {
   return cheriot_cli_top_->CLIGetInstruction(address);
 }

diff --git a/cheriot/cheriot_cli_forwarder.h b/cheriot/cheriot_cli_forwarder.h
index c7b700b..1291f3a 100644
--- a/cheriot/cheriot_cli_forwarder.h
+++ b/cheriot/cheriot_cli_forwarder.h

@@ -42,12 +42,12 @@
 
 class CheriotCLIForwarder : public CheriotDebugInterface {
  public:
-  explicit CheriotCLIForwarder(CheriotRenodeCLITop *top);
+  explicit CheriotCLIForwarder(CheriotRenodeCLITop* top);
   CheriotCLIForwarder() = delete;
-  CheriotCLIForwarder(const CLIForwarder &) = delete;
-  CheriotCLIForwarder &operator=(const CLIForwarder &) = delete;
+  CheriotCLIForwarder(const CLIForwarder&) = delete;
+  CheriotCLIForwarder& operator=(const CLIForwarder&) = delete;
 
-  absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void* buf,
                                        size_t length) override;
   // Set a data watchpoint for the given memory range. Any access matching the
   // given access type (load/store) will halt execution following the completion
@@ -89,8 +89,8 @@
   // Returns the reason for the most recent halt.
   absl::StatusOr<HaltReasonValueType> GetLastHaltReason() override;
 
-  absl::StatusOr<uint64_t> ReadRegister(const std::string &name) override;
-  absl::Status WriteRegister(const std::string &name, uint64_t value) override;
+  absl::StatusOr<uint64_t> ReadRegister(const std::string& name) override;
+  absl::Status WriteRegister(const std::string& name, uint64_t value) override;
 
   // Some registers, including vector registers, have values that exceed the
   // 64 bits supported in the Read/Write register API calls. This function
@@ -102,13 +102,13 @@
   // Note (2): In some cases, a register write may replace the DataBuffer
   // instance within a register so that any stored references to it become
   // stale.
-  absl::StatusOr<DataBuffer *> GetRegisterDataBuffer(
-      const std::string &name) override;
+  absl::StatusOr<DataBuffer*> GetRegisterDataBuffer(
+      const std::string& name) override;
 
   // Read/write the buffers to memory.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
 
   // Test to see if there's a breakpoint at the given address.
@@ -120,12 +120,12 @@
   absl::Status ClearAllSwBreakpoints() override;
 
   // Return the instruction object for the instruction at the given address.
-  absl::StatusOr<Instruction *> GetInstruction(uint64_t address) override;
+  absl::StatusOr<Instruction*> GetInstruction(uint64_t address) override;
   // Return the string representation for the instruction at the given address.
   absl::StatusOr<std::string> GetDisassembly(uint64_t address) override;
 
  private:
-  CheriotRenodeCLITop *cheriot_cli_top_;
+  CheriotRenodeCLITop* cheriot_cli_top_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_debug_info.cc b/cheriot/cheriot_debug_info.cc
index b6e6c40..2c06813 100644
--- a/cheriot/cheriot_debug_info.cc
+++ b/cheriot/cheriot_debug_info.cc

@@ -157,8 +157,8 @@
                            {*DebugRegisterEnum::kF30, kF30Name},
                            {*DebugRegisterEnum::kF31, kF31Name}}) {}
 
-CheriotDebugInfo *CheriotDebugInfo::Instance() {
-  static CheriotDebugInfo *instance_ = nullptr;
+CheriotDebugInfo* CheriotDebugInfo::Instance() {
+  static CheriotDebugInfo* instance_ = nullptr;
   if (instance_ == nullptr) {
     instance_ = new CheriotDebugInfo();
   }

diff --git a/cheriot/cheriot_debug_interface.h b/cheriot/cheriot_debug_interface.h
index 0be9869..ebf4274 100644
--- a/cheriot/cheriot_debug_interface.h
+++ b/cheriot/cheriot_debug_interface.h

@@ -36,7 +36,7 @@
   // Read tags from memory from the byte address (not tag address) given. The
   // tag address is computed by shifting the byte address right by three. The
   // length specifies the number of bytes (tags) to read.
-  virtual absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void *buf,
+  virtual absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void* buf,
                                                size_t length) = 0;
   // Set a data watchpoint for the given memory range. Any access matching the
   // given access type (load/store) will halt execution following the completion

diff --git a/cheriot/cheriot_decoder.cc b/cheriot/cheriot_decoder.cc
index 805d5fd..0c0b994 100644
--- a/cheriot/cheriot_decoder.cc
+++ b/cheriot/cheriot_decoder.cc

@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-CheriotDecoder::CheriotDecoder(CheriotState *state,
-                               util::MemoryInterface *memory)
+CheriotDecoder::CheriotDecoder(CheriotState* state,
+                               util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Need a data buffer to load instructions from memory. Allocate a single
   // buffer that can be reused for each instruction word.
@@ -55,16 +55,16 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *CheriotDecoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* CheriotDecoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAddressMisaligned, inst->address() ^ 0x1,
                    inst);
@@ -75,12 +75,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAccessFault, inst->address(), nullptr);
     });
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = cheriot_isa_->Decode(address, cheriot_encoding_);
+  auto* instruction = cheriot_isa_->Decode(address, cheriot_encoding_);
   return instruction;
 }
 

diff --git a/cheriot/cheriot_decoder.h b/cheriot/cheriot_decoder.h
index f219457..0645717 100644
--- a/cheriot/cheriot_decoder.h
+++ b/cheriot/cheriot_decoder.h

@@ -42,7 +42,7 @@
 class CheriotIsaFactory : public isa32::RiscVCheriotInstructionSetFactory {
  public:
   std::unique_ptr<isa32::Riscv32CheriotSlot> CreateRiscv32CheriotSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32::Riscv32CheriotSlot>(state);
   }
 };
@@ -54,37 +54,37 @@
   using SlotEnum = isa32::SlotEnum;
   using OpcodeEnum = isa32::OpcodeEnum;
 
-  CheriotDecoder(CheriotState *state, util::MemoryInterface *memory);
+  CheriotDecoder(CheriotState* state, util::MemoryInterface* memory);
   CheriotDecoder() = delete;
   ~CheriotDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
 
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override {
     return static_cast<int>(OpcodeEnum::kPastMaxValue);
   }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32::RiscVCheriotEncoding *cheriot_encoding() const {
+  isa32::RiscVCheriotEncoding* cheriot_encoding() const {
     return cheriot_encoding_;
   }
 
  private:
-  CheriotState *state_;
-  util::MemoryInterface *memory_;
+  CheriotState* state_;
+  util::MemoryInterface* memory_;
   generic::DataBufferFactory db_factory_;
-  generic::DataBuffer *inst_db_;
-  isa32::RiscVCheriotEncoding *cheriot_encoding_;
-  isa32::RiscVCheriotInstructionSetFactory *cheriot_isa_factory_;
-  isa32::RiscVCheriotInstructionSet *cheriot_isa_;
+  generic::DataBuffer* inst_db_;
+  isa32::RiscVCheriotEncoding* cheriot_encoding_;
+  isa32::RiscVCheriotInstructionSetFactory* cheriot_isa_factory_;
+  isa32::RiscVCheriotInstructionSet* cheriot_isa_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_f_getters.h b/cheriot/cheriot_f_getters.h
index c4565ba..82638ae 100644
--- a/cheriot/cheriot_f_getters.h
+++ b/cheriot/cheriot_f_getters.h

@@ -42,14 +42,14 @@
 using ::mpact::sim::riscv::RVFpRegister;
 
 using SourceOpGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
 using DestOpGetterMap =
     absl::flat_hash_map<int,
-                        absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+                        absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
 template <typename Enum, typename Extractors>
-void AddCheriotFSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVCheriotEncodingCommon *common) {
+void AddCheriotFSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVCheriotEncodingCommon* common) {
   Insert(getter_map, *Enum::kFrs1, [common]() {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<RVFpRegister>(
@@ -70,7 +70,7 @@
     return GetRegisterSourceOp<RVFpRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num));
   });
-  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface* {
     uint32_t rm = (common->inst_word() >> 12) & 0x7;
     switch (rm) {
       case 0:
@@ -96,8 +96,8 @@
 }
 
 template <typename Enum, typename Extractors>
-void AddCheriotFDestGetters(DestOpGetterMap &getter_map,
-                            RiscVCheriotEncodingCommon *common) {
+void AddCheriotFDestGetters(DestOpGetterMap& getter_map,
+                            RiscVCheriotEncodingCommon* common) {
   Insert(getter_map, *Enum::kFrd, [common](int latency) {
     int num = Extractors::RType::ExtractRd(common->inst_word());
     return GetRegisterDestinationOp<RVFpRegister>(

diff --git a/cheriot/cheriot_getter_helpers.h b/cheriot/cheriot_getter_helpers.h
index a71ac74..b97fc07 100644
--- a/cheriot/cheriot_getter_helpers.h
+++ b/cheriot/cheriot_getter_helpers.h

@@ -39,7 +39,7 @@
 constexpr int kNumRegTable[8] = {8, 1, 2, 1, 4, 1, 2, 1};
 
 template <typename M, typename E, typename G>
-inline void Insert(M &map, E entry, G getter) {
+inline void Insert(M& map, E entry, G getter) {
   if (!map.contains(static_cast<int>(entry))) {
     map.insert(std::make_pair(static_cast<int>(entry), getter));
   } else {
@@ -49,52 +49,52 @@
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    CheriotState *state, std::string name, int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    CheriotState* state, std::string name, int latency) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    CheriotState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    CheriotState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    CheriotState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    CheriotState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(CheriotState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(CheriotState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(CheriotState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(CheriotState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
 template <typename RegType>
-inline void GetVRegGroup(CheriotState *state, int reg_num,
-                         std::vector<generic::RegisterBase *> *vreg_group) {
+inline void GetVRegGroup(CheriotState* state, int reg_num,
+                         std::vector<generic::RegisterBase*>* vreg_group) {
   // The number of registers in a vector register group depends on the register
   // index: 0, 8, 16, 24 each have 8 registers, 4, 12, 20, 28 each have 4,
   // 2, 6, 10, 14, 18, 22, 26, 30 each have two, and all odd numbered register
@@ -106,53 +106,53 @@
   }
 }
 template <typename RegType>
-inline SourceOperandInterface *GetVectorRegisterSourceOp(CheriotState *state,
+inline SourceOperandInterface* GetVectorRegisterSourceOp(CheriotState* state,
                                                          int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(CheriotState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorRegisterDestinationOp(
-    CheriotState *state, int latency, int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+inline DestinationOperandInterface* GetVectorRegisterDestinationOp(
+    CheriotState* state, int latency, int reg_num) {
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(CheriotState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetVectorMaskRegisterSourceOp(
-    CheriotState *state, int reg_num) {
+inline SourceOperandInterface* GetVectorMaskRegisterSourceOp(
+    CheriotState* state, int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(state
                            ->GetRegister<RegType>(
                                absl::StrCat(CheriotState::kVregPrefix, reg_num))
                            .first);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(CheriotState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorMaskRegisterDestinationOp(
-    CheriotState *state, int latency, int reg_num) {
+inline DestinationOperandInterface* GetVectorMaskRegisterDestinationOp(
+    CheriotState* state, int latency, int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(state
                            ->GetRegister<RegType>(
                                absl::StrCat(CheriotState::kVregPrefix, reg_num))
                            .first);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(CheriotState::kVregPrefix, reg_num));
   return v_dst_op;
 }

diff --git a/cheriot/cheriot_getters.h b/cheriot/cheriot_getters.h
index efc2af2..3a0804a 100644
--- a/cheriot/cheriot_getters.h
+++ b/cheriot/cheriot_getters.h

@@ -41,22 +41,22 @@
 using ::mpact::sim::generic::SourceOperandInterface;
 
 using SourceOpGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
 using DestOpGetterMap =
     absl::flat_hash_map<int,
-                        absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+                        absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
 template <typename Enum, typename Extractors>
-void AddCheriotSourceGetters(SourceOpGetterMap &getter_map,
-                             RiscVCheriotEncodingCommon *common) {
+void AddCheriotSourceGetters(SourceOpGetterMap& getter_map,
+                             RiscVCheriotEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kAAq, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kAAq, [common]() -> SourceOperandInterface* {
     if (Extractors::Inst32Format::ExtractAq(common->inst_word())) {
       return new IntLiteralOperand<1>();
     }
     return new IntLiteralOperand<0>();
   });
-  Insert(getter_map, *Enum::kARl, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kARl, [common]() -> SourceOperandInterface* {
     if (Extractors::Inst32Format::ExtractRl(common->inst_word())) {
       return new generic::IntLiteralOperand<1>();
     }
@@ -136,7 +136,7 @@
     if (!res.ok()) {
       return new ImmediateOperand<uint32_t>(csr_indx);
     }
-    auto *csr = res.value();
+    auto* csr = res.value();
     return new ImmediateOperand<uint32_t>(csr_indx, csr->name());
   });
   Insert(getter_map, *Enum::kICbImm8, [common]() {
@@ -222,21 +222,21 @@
   Insert(getter_map, *Enum::kPcc, [common]() {
     return GetRegisterSourceOp<CheriotRegister>(common->state(), "pcc", "pcc");
   });
-  Insert(getter_map, *Enum::kRd, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRd, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRd(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<CheriotRegister>(
         common->state(), absl::StrCat(CheriotState::kXregPrefix, num),
         kXRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<CheriotRegister>(
         common->state(), absl::StrCat(CheriotState::kXregPrefix, num),
         kXRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kRs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs2, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<CheriotRegister>(
@@ -247,7 +247,7 @@
     return new ImmediateOperand<int32_t>(
         Extractors::SType::ExtractSImm(common->inst_word()));
   });
-  Insert(getter_map, *Enum::kScr, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kScr, [common]() -> SourceOperandInterface* {
     int csr_indx = Extractors::RType::ExtractRs2(common->inst_word());
     std::string csr_name;
     switch (csr_indx) {
@@ -271,8 +271,8 @@
       return GetRegisterSourceOp<CheriotRegister>(common->state(), csr_name,
                                                   csr_name);
     }
-    auto *csr = res.value();
-    auto *op = csr->CreateSourceOperand();
+    auto* csr = res.value();
+    auto* op = csr->CreateSourceOperand();
     return op;
   });
   Insert(getter_map, *Enum::kSImm20, [common]() {
@@ -293,8 +293,8 @@
 }
 
 template <typename Enum, typename Extractors>
-void AddCheriotDestGetters(DestOpGetterMap &getter_map,
-                           RiscVCheriotEncodingCommon *common) {
+void AddCheriotDestGetters(DestOpGetterMap& getter_map,
+                           RiscVCheriotEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kC2, [common](int latency) {
     return GetRegisterDestinationOp<CheriotRegister>(common->state(), "c2",
@@ -337,7 +337,7 @@
         common->state(), CheriotState::kCsrName, latency);
   });
   Insert(getter_map, *Enum::kScr,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            int csr_indx = Extractors::RType::ExtractRs2(common->inst_word());
            std::string csr_name;
            switch (csr_indx) {
@@ -361,12 +361,12 @@
              return GetRegisterDestinationOp<CheriotRegister>(
                  common->state(), csr_name, latency);
            }
-           auto *csr = res.value();
-           auto *op = csr->CreateWriteDestinationOperand(latency, csr_name);
+           auto* csr = res.value();
+           auto* op = csr->CreateWriteDestinationOperand(latency, csr_name);
            return op;
          });
   Insert(getter_map, *Enum::kRd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            int num = Extractors::RType::ExtractRd(common->inst_word());
            if (num == 0) {
              return GetRegisterDestinationOp<CheriotRegister>(common->state(),

diff --git a/cheriot/cheriot_ibex_hw_revoker.cc b/cheriot/cheriot_ibex_hw_revoker.cc
index 46b4b2a..ef62ab8 100644
--- a/cheriot/cheriot_ibex_hw_revoker.cc
+++ b/cheriot/cheriot_ibex_hw_revoker.cc

@@ -37,12 +37,12 @@
 using ::mpact::sim::util::MemoryInterface;
 using ::mpact::sim::util::TaggedMemoryInterface;
 
-CheriotIbexHWRevoker::CheriotIbexHWRevoker(RiscVPlicIrqInterface *plic_irq,
+CheriotIbexHWRevoker::CheriotIbexHWRevoker(RiscVPlicIrqInterface* plic_irq,
                                            uint64_t heap_base,
                                            uint64_t heap_size,
-                                           TaggedMemoryInterface *heap_memory,
+                                           TaggedMemoryInterface* heap_memory,
                                            uint64_t revocation_bits_base,
-                                           MemoryInterface *revocation_memory)
+                                           MemoryInterface* revocation_memory)
     : plic_irq_(plic_irq),
       heap_base_(heap_base),
       heap_max_(heap_base + heap_size),
@@ -66,9 +66,9 @@
 
 CheriotIbexHWRevoker::CheriotIbexHWRevoker(uint64_t heap_base,
                                            uint64_t heap_size,
-                                           TaggedMemoryInterface *heap_memory,
+                                           TaggedMemoryInterface* heap_memory,
                                            uint64_t revocation_bits_base,
-                                           MemoryInterface *revocation_memory)
+                                           MemoryInterface* revocation_memory)
     : CheriotIbexHWRevoker(nullptr, heap_base, heap_size, heap_memory,
                            revocation_bits_base, revocation_memory) {}
 
@@ -90,7 +90,7 @@
 }
 
 // This is called by the counter using the CounterValueSetInterface interface.
-void CheriotIbexHWRevoker::SetValue(const uint64_t &val) {
+void CheriotIbexHWRevoker::SetValue(const uint64_t& val) {
   if (interrupt_status_) SetInterrupt(false);
   if (!sweep_in_progress_) return;
   num_calls_++;
@@ -101,16 +101,16 @@
 }
 
 // Reads from the MMRs.
-void CheriotIbexHWRevoker::Load(uint64_t address, DataBuffer *db,
-                                DataBuffer *tags, Instruction *inst,
-                                ReferenceCount *context) {
+void CheriotIbexHWRevoker::Load(uint64_t address, DataBuffer* db,
+                                DataBuffer* tags, Instruction* inst,
+                                ReferenceCount* context) {
   if (tags != nullptr) std::memset(tags->raw_ptr(), 0, tags->size<uint8_t>());
   Load(address, db, inst, context);
 }
 
 // Reads from the MMRs.
-void CheriotIbexHWRevoker::Load(uint64_t address, DataBuffer *db,
-                                Instruction *inst, ReferenceCount *context) {
+void CheriotIbexHWRevoker::Load(uint64_t address, DataBuffer* db,
+                                Instruction* inst, ReferenceCount* context) {
   uint32_t offset = address & 0xffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -148,21 +148,21 @@
 }
 
 // Vector load is not supported.
-void CheriotIbexHWRevoker::Load(DataBuffer *address_db, DataBuffer *mask_db,
-                                int el_size, DataBuffer *db, Instruction *inst,
-                                ReferenceCount *context) {
+void CheriotIbexHWRevoker::Load(DataBuffer* address_db, DataBuffer* mask_db,
+                                int el_size, DataBuffer* db, Instruction* inst,
+                                ReferenceCount* context) {
   // This is left unimplemented. Vector load is not supported.
   LOG(FATAL) << "Vector load not supported";  // Crash OK
 }
 
 // Writes to the MMRs.
-void CheriotIbexHWRevoker::Store(uint64_t address, DataBuffer *db,
-                                 DataBuffer *tags) {
+void CheriotIbexHWRevoker::Store(uint64_t address, DataBuffer* db,
+                                 DataBuffer* tags) {
   Store(address, db);
 }
 
 // Writes to the MMRs.
-void CheriotIbexHWRevoker::Store(uint64_t address, DataBuffer *db) {
+void CheriotIbexHWRevoker::Store(uint64_t address, DataBuffer* db) {
   uint32_t offset = address & 0xffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -180,8 +180,8 @@
 }
 
 // Vector accesses are not supported.
-void CheriotIbexHWRevoker::Store(DataBuffer *address, DataBuffer *mask,
-                                 int el_size, DataBuffer *db) {
+void CheriotIbexHWRevoker::Store(DataBuffer* address, DataBuffer* mask,
+                                 int el_size, DataBuffer* db) {
   // This is left unimplemented. Vector store is not supported.
   LOG(FATAL) << "Vector store not supported";  // Crash OK
 }

diff --git a/cheriot/cheriot_ibex_hw_revoker.h b/cheriot/cheriot_ibex_hw_revoker.h
index 2fd7f5d..8e051ea 100644
--- a/cheriot/cheriot_ibex_hw_revoker.h
+++ b/cheriot/cheriot_ibex_hw_revoker.h

@@ -68,42 +68,42 @@
   static constexpr uint32_t kInterruptEnableOffset = 0x0014;
 
   CheriotIbexHWRevoker() = delete;
-  CheriotIbexHWRevoker(const CheriotIbexHWRevoker &) = delete;
-  CheriotIbexHWRevoker &operator=(const CheriotIbexHWRevoker &) = delete;
-  CheriotIbexHWRevoker(RiscVPlicIrqInterface *plic_irq, uint64_t heap_base,
-                       uint64_t heap_size, TaggedMemoryInterface *heap_memory,
+  CheriotIbexHWRevoker(const CheriotIbexHWRevoker&) = delete;
+  CheriotIbexHWRevoker& operator=(const CheriotIbexHWRevoker&) = delete;
+  CheriotIbexHWRevoker(RiscVPlicIrqInterface* plic_irq, uint64_t heap_base,
+                       uint64_t heap_size, TaggedMemoryInterface* heap_memory,
                        uint64_t revocation_bits_base,
-                       MemoryInterface *revocation_memory);
+                       MemoryInterface* revocation_memory);
   CheriotIbexHWRevoker(uint64_t heap_base, uint64_t heap_size,
-                       TaggedMemoryInterface *heap_memory,
+                       TaggedMemoryInterface* heap_memory,
                        uint64_t revocation_bits_base,
-                       MemoryInterface *revocation_memory);
+                       MemoryInterface* revocation_memory);
   ~CheriotIbexHWRevoker();
   // Resets the interrupt controller.
   void Reset();
   // CounterValueSetInterface override. This is called when the value of the
   // bound counter is modified.
-  void SetValue(const uint64_t &val) override;
+  void SetValue(const uint64_t& val) override;
 
   // MemoryInterface overrides.
   // Non-vector load method.
-  void Load(uint64_t address, DataBuffer *db, DataBuffer *tags,
-            Instruction *inst, ReferenceCount *context) override;
-  void Load(uint64_t address, DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(uint64_t address, DataBuffer* db, DataBuffer* tags,
+            Instruction* inst, ReferenceCount* context) override;
+  void Load(uint64_t address, DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Vector load method - this is stubbed out.
-  void Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-            DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+            DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Non-vector store method.
-  void Store(uint64_t address, DataBuffer *db, DataBuffer *tags) override;
-  void Store(uint64_t address, DataBuffer *dbs) override;
+  void Store(uint64_t address, DataBuffer* db, DataBuffer* tags) override;
+  void Store(uint64_t address, DataBuffer* dbs) override;
   // Vector store method - this is stubbed out.
-  void Store(DataBuffer *address, DataBuffer *mask, int el_size,
-             DataBuffer *db) override;
+  void Store(DataBuffer* address, DataBuffer* mask, int el_size,
+             DataBuffer* db) override;
 
   // Getters & setters.
-  void set_plic_irq(RiscVPlicIrqInterface *plic_irq) { plic_irq_ = plic_irq; }
+  void set_plic_irq(RiscVPlicIrqInterface* plic_irq) { plic_irq_ = plic_irq; }
   int period() const { return period_; }
   void set_period(int period) { period_ = period; }
   int cap_count() const { return cap_count_; }
@@ -134,19 +134,19 @@
   uint64_t current_cap_ = 0;
   // Sweep in progress.
   bool sweep_in_progress_ = false;
-  RiscVPlicIrqInterface *plic_irq_ = nullptr;
+  RiscVPlicIrqInterface* plic_irq_ = nullptr;
   // Heap range.
   uint64_t heap_base_ = 0;
   uint64_t heap_max_ = 0;
   // Memory interface to use for the tagged heap.
-  TaggedMemoryInterface *heap_memory_ = nullptr;
+  TaggedMemoryInterface* heap_memory_ = nullptr;
   // Memory interface to use for the revocation bits.
-  MemoryInterface *revocation_memory_ = nullptr;
+  MemoryInterface* revocation_memory_ = nullptr;
   // Data buffers.
-  DataBuffer *db_ = nullptr;
-  DataBuffer *tag_db_ = nullptr;
+  DataBuffer* db_ = nullptr;
+  DataBuffer* tag_db_ = nullptr;
   // Capability register.
-  CheriotRegister *cap_reg_ = nullptr;
+  CheriotRegister* cap_reg_ = nullptr;
   // Base address of the revocation bits.
   uint64_t revocation_bits_base_ = 0;
   // DB factory.

diff --git a/cheriot/cheriot_instrumentation_control.cc b/cheriot/cheriot_instrumentation_control.cc
index 23aa8ef..2742988 100644
--- a/cheriot/cheriot_instrumentation_control.cc
+++ b/cheriot/cheriot_instrumentation_control.cc

@@ -31,8 +31,8 @@
 namespace mpact::sim::cheriot {
 
 CheriotInstrumentationControl::CheriotInstrumentationControl(
-    DebugCommandShell *shell, CheriotTop *cheriot_top,
-    TaggedMemoryUseProfiler *mem_profiler)
+    DebugCommandShell* shell, CheriotTop* cheriot_top,
+    TaggedMemoryUseProfiler* mem_profiler)
     : shell_(shell),
       top_(cheriot_top),
       mem_profiler_(mem_profiler),
@@ -41,8 +41,8 @@
 }
 
 bool CheriotInstrumentationControl::PerformShellCommand(
-    absl::string_view input, const DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    absl::string_view input, const DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   std::string cmd;
   std::string what;
   std::string where;
@@ -113,7 +113,7 @@
       return true;
     }
     // Let's see if it is a symbol.
-    auto *loader = core_access.loader_getter();
+    auto* loader = core_access.loader_getter();
     if (loader == nullptr) {
       output = "Error: cannot perform symbol lookup";
       return true;

diff --git a/cheriot/cheriot_instrumentation_control.h b/cheriot/cheriot_instrumentation_control.h
index d9185ca..6ef3014 100644
--- a/cheriot/cheriot_instrumentation_control.h
+++ b/cheriot/cheriot_instrumentation_control.h

@@ -31,20 +31,20 @@
 
 class CheriotInstrumentationControl {
  public:
-  CheriotInstrumentationControl(DebugCommandShell *shell,
-                                CheriotTop *cheriot_top,
-                                TaggedMemoryUseProfiler *mem_profiler);
+  CheriotInstrumentationControl(DebugCommandShell* shell,
+                                CheriotTop* cheriot_top,
+                                TaggedMemoryUseProfiler* mem_profiler);
 
   bool PerformShellCommand(absl::string_view input,
-                           const DebugCommandShell::CoreAccess &core_access,
-                           std::string &output);
+                           const DebugCommandShell::CoreAccess& core_access,
+                           std::string& output);
 
   std::string Usage() const;
 
  private:
-  DebugCommandShell *shell_;
-  CheriotTop *top_ = nullptr;
-  TaggedMemoryUseProfiler *mem_profiler_;
+  DebugCommandShell* shell_;
+  CheriotTop* top_ = nullptr;
+  TaggedMemoryUseProfiler* mem_profiler_;
   LazyRE2 pattern_re_;
 };
 

diff --git a/cheriot/cheriot_load_filter.cc b/cheriot/cheriot_load_filter.cc
index f7f3439..41b1e79 100644
--- a/cheriot/cheriot_load_filter.cc
+++ b/cheriot/cheriot_load_filter.cc

@@ -20,7 +20,7 @@
 
 namespace mpact::sim::cheriot {
 
-CheriotLoadFilter::CheriotLoadFilter(TaggedMemoryInterface *tagged_memory,
+CheriotLoadFilter::CheriotLoadFilter(TaggedMemoryInterface* tagged_memory,
                                      int period, int count, uint64_t base,
                                      uint64_t top, uint64_t cap_base,
                                      uint64_t revocation_base)
@@ -53,7 +53,7 @@
 
 // This is called when the linked counter increments. We are not interested
 // in the value of the counter, just the number of increments.
-void CheriotLoadFilter::SetValue(const uint64_t &) {
+void CheriotLoadFilter::SetValue(const uint64_t&) {
   if (++update_counter_ >= period_) {
     update_counter_ = 0;
     // Once triggered, perform count_ filter loads/stores.

diff --git a/cheriot/cheriot_load_filter.h b/cheriot/cheriot_load_filter.h
index 716c139..8f0ab2b 100644
--- a/cheriot/cheriot_load_filter.h
+++ b/cheriot/cheriot_load_filter.h

@@ -52,16 +52,16 @@
   //                  the base of the region of memory to which revokable
   //                  capabilities may use as their base addresses.
   //   revocation_base: The base address of the revocation data area.
-  CheriotLoadFilter(TaggedMemoryInterface *tagged_memory, int period, int count,
+  CheriotLoadFilter(TaggedMemoryInterface* tagged_memory, int period, int count,
                     uint64_t base, uint64_t top, uint64_t cap_base,
                     uint64_t revocation_base);
   CheriotLoadFilter() = delete;
-  CheriotLoadFilter(const CheriotLoadFilter &) = delete;
-  CheriotLoadFilter &operator=(const CheriotLoadFilter &) = delete;
+  CheriotLoadFilter(const CheriotLoadFilter&) = delete;
+  CheriotLoadFilter& operator=(const CheriotLoadFilter&) = delete;
   ~CheriotLoadFilter() override;
 
   // Overridden method called by updates of a linked counter.
-  void SetValue(const uint64_t &value) override;
+  void SetValue(const uint64_t& value) override;
 
  private:
   // Loads the capability at the given address, checks for valid tag and
@@ -73,7 +73,7 @@
   bool MustRevoke(uint64_t address);
 
   // Memory interface to use for loads/stores.
-  TaggedMemoryInterface *tagged_memory_;
+  TaggedMemoryInterface* tagged_memory_;
   // Counter to keep track of the number of times SetValue is called.
   int update_counter_ = 0;
   int period_;
@@ -87,11 +87,11 @@
   // Current capability address.
   uint64_t cap_address_;
   // Capability register used to expand the loaded capability into.
-  CheriotRegister *cap_reg_;
+  CheriotRegister* cap_reg_;
   // Data buffer factory and data buffers used in loads/stores.
   DataBufferFactory db_factory_;
-  DataBuffer *db_;
-  DataBuffer *tag_db_;
+  DataBuffer* db_;
+  DataBuffer* tag_db_;
 };
 
 }  // namespace mpact::sim::cheriot

diff --git a/cheriot/cheriot_register.cc b/cheriot/cheriot_register.cc
index 9ab85ef..1b528e1 100644
--- a/cheriot/cheriot_register.cc
+++ b/cheriot/cheriot_register.cc

@@ -40,7 +40,7 @@
   return (value >> shift) & mask;
 }
 
-CheriotRegister::CheriotRegister(generic::ArchState *state,
+CheriotRegister::CheriotRegister(generic::ArchState* state,
                                  absl::string_view name)
     : generic::Register<uint32_t>(state, name) {
   ResetNull();
@@ -327,7 +327,7 @@
   }
 }
 
-absl::Status CheriotRegister::Seal(const CheriotRegister &source,
+absl::Status CheriotRegister::Seal(const CheriotRegister& source,
                                    uint32_t obj_type) {
   if (is_null_) {
     Expand(address(), 0, /*tag=*/false);
@@ -387,7 +387,7 @@
   return status;
 }
 
-absl::Status CheriotRegister::Unseal(const CheriotRegister &source,
+absl::Status CheriotRegister::Unseal(const CheriotRegister& source,
                                      uint32_t obj_type) {
   if (is_null_) {
     Expand(address(), 0, /*tag=*/false);
@@ -442,7 +442,7 @@
                        (object_type() == kInterruptDisablingBackwardSentry));
 }
 
-void CheriotRegister::CopyFrom(const CheriotRegister &other) {
+void CheriotRegister::CopyFrom(const CheriotRegister& other) {
   data_buffer()->CopyFrom(other.data_buffer());
   if (other.is_null_) {
     Expand(address(), 0, /*tag=*/false);
@@ -460,14 +460,14 @@
   raw_ = other.raw_;
 }
 
-bool CheriotRegister::operator==(const CheriotRegister &other) const {
+bool CheriotRegister::operator==(const CheriotRegister& other) const {
   return (tag() == other.tag()) && (top() == other.top()) &&
          (base() == other.base()) && (permissions() == other.permissions()) &&
          (object_type() == other.object_type()) &&
          (reserved() == other.reserved());
 }
 
-bool CheriotRegister::IsMemoryEqual(const CheriotRegister &other) const {
+bool CheriotRegister::IsMemoryEqual(const CheriotRegister& other) const {
   return (address() == other.address()) && (Compress() == other.Compress());
 }
 

diff --git a/cheriot/cheriot_register.h b/cheriot/cheriot_register.h
index 647b58c..9cfc569 100644
--- a/cheriot/cheriot_register.h
+++ b/cheriot/cheriot_register.h

@@ -101,10 +101,10 @@
   static constexpr int kReserved[2] = {31, 31};
 
   // Constructor. Default constructors and assignment are disabled.
-  CheriotRegister(generic::ArchState *state, absl::string_view name);
+  CheriotRegister(generic::ArchState* state, absl::string_view name);
   CheriotRegister() = delete;
-  CheriotRegister(const CheriotRegister &) = delete;
-  CheriotRegister &operator=(const CheriotRegister &) = delete;
+  CheriotRegister(const CheriotRegister&) = delete;
+  CheriotRegister& operator=(const CheriotRegister&) = delete;
 
   // These functions set the capability register to a known state, either the
   // null capability, or one of the three root capabilities. All capabilities
@@ -139,8 +139,8 @@
   bool IsRepresentable() const;
   // Seal (unseal) the current capability based on permissions and address field
   // in source. Returns ok status if the operation is successful.
-  absl::Status Seal(const CheriotRegister &source, uint32_t obj_type);
-  absl::Status Unseal(const CheriotRegister &source, uint32_t obj_type);
+  absl::Status Seal(const CheriotRegister& source, uint32_t obj_type);
+  absl::Status Unseal(const CheriotRegister& source, uint32_t obj_type);
   // Returns true if the capability is sealed, i.e., that the object type is set
   // to a valid, non-reserved object type.
   bool IsSealed() const;
@@ -162,10 +162,10 @@
            (top() >= (uint64_t)cap_address + (uint64_t)size);
   }
   // Copy fields from other capability register.
-  void CopyFrom(const CheriotRegister &other);
+  void CopyFrom(const CheriotRegister& other);
   // Equal operator.
-  bool operator==(const CheriotRegister &other) const;
-  bool IsMemoryEqual(const CheriotRegister &other) const;
+  bool operator==(const CheriotRegister& other) const;
+  bool IsMemoryEqual(const CheriotRegister& other) const;
   // Text representation.
   std::string AsString() const;
   // Update address with change to base and top as needed.

diff --git a/cheriot/cheriot_renode.cc b/cheriot/cheriot_renode.cc
index 5269cf7..142336c 100644
--- a/cheriot/cheriot_renode.cc
+++ b/cheriot/cheriot_renode.cc

@@ -61,10 +61,10 @@
 #include "riscv//stoull_wrapper.h"
 #include "src/google/protobuf/text_format.h"
 
-::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
+::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
     std::string name, std::string cpu_type,
-    ::mpact::sim::util::MemoryInterface *renode_sysbus) {
-  auto *top = new ::mpact::sim::cheriot::CheriotRenode(name, renode_sysbus);
+    ::mpact::sim::util::MemoryInterface* renode_sysbus) {
+  auto* top = new ::mpact::sim::cheriot::CheriotRenode(name, renode_sysbus);
   auto status = top->InitializeSimulator(cpu_type);
   if (!status.ok()) {
     delete top;
@@ -112,7 +112,7 @@
 // Core version.
 constexpr std::string_view kCoreVersion = "coreVersion";
 
-CheriotRenode::CheriotRenode(std::string name, MemoryInterface *renode_sysbus)
+CheriotRenode::CheriotRenode(std::string name, MemoryInterface* renode_sysbus)
     : name_(name), renode_sysbus_(renode_sysbus) {}
 
 CheriotRenode::~CheriotRenode() {
@@ -181,7 +181,7 @@
 }
 
 absl::StatusOr<uint64_t> CheriotRenode::LoadExecutable(
-    const char *elf_file_name, bool for_symbols_only) {
+    const char* elf_file_name, bool for_symbols_only) {
   program_loader_ = new ElfProgramLoader(this);
   uint64_t entry_pt = 0;
   if (for_symbols_only) {
@@ -205,12 +205,12 @@
     uint64_t tohost_addr = res.value().first;
     // Add to_host watchpoint that halts the execution when program exit is
     // signaled.
-    auto *db = cheriot_top_->state()->db_factory()->Allocate<uint32_t>(2);
+    auto* db = cheriot_top_->state()->db_factory()->Allocate<uint32_t>(2);
     auto status = cheriot_top_->tagged_watcher()->SetStoreWatchCallback(
         TaggedMemoryWatcher::AddressRange{
             tohost_addr, tohost_addr + 2 * sizeof(uint32_t) - 1},
         [this, tohost_addr, db](uint64_t addr, int sz) {
-          static DataBuffer *load_db = db;
+          static DataBuffer* load_db = db;
           if (load_db == nullptr) return;
           tagged_memory_->Load(tohost_addr, load_db, nullptr, nullptr);
           uint32_t code = load_db->Get<uint32_t>(0);
@@ -258,9 +258,9 @@
 
 // Perform direct read of the memory through the renode router. The renode
 // router avoids routing the request back out to the sysbus.
-absl::StatusOr<size_t> CheriotRenode::ReadMemory(uint64_t address, void *buf,
+absl::StatusOr<size_t> CheriotRenode::ReadMemory(uint64_t address, void* buf,
                                                  size_t length) {
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   renode_router_->Load(address, db, nullptr, nullptr);
   std::memcpy(buf, db->raw_ptr(), length);
   db->DecRef();
@@ -270,9 +270,9 @@
 // Perform direct write of the memory through the renode router. The renode
 // router avoids routing the request back out to the sysbus.
 absl::StatusOr<size_t> CheriotRenode::WriteMemory(uint64_t address,
-                                                  const void *buf,
+                                                  const void* buf,
                                                   size_t length) {
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   std::memcpy(db->raw_ptr(), buf, length);
   renode_router_->Store(address, db);
   db->DecRef();
@@ -306,16 +306,16 @@
 }
 
 absl::Status CheriotRenode::GetRenodeRegisterInfo(int32_t index,
-                                                  int32_t max_len, char *name,
-                                                  RenodeCpuRegister &info) {
-  auto const &register_info =
+                                                  int32_t max_len, char* name,
+                                                  RenodeCpuRegister& info) {
+  auto const& register_info =
       CheriotRenodeRegisterInfo::GetRenodeRegisterInfo();
   if ((index < 0) || (index >= register_info.size())) {
     return absl::OutOfRangeError(
         absl::StrCat("Register info index (", index, ") out of range"));
   }
   info = register_info[index];
-  auto const &reg_map = CheriotDebugInfo::Instance()->debug_register_map();
+  auto const& reg_map = CheriotDebugInfo::Instance()->debug_register_map();
   auto ptr = reg_map.find(info.index);
   if (ptr == reg_map.end()) {
     name[0] = '\0';
@@ -325,7 +325,7 @@
   return absl::OkStatus();
 }
 
-static absl::StatusOr<uint64_t> ParseNumber(const std::string &number) {
+static absl::StatusOr<uint64_t> ParseNumber(const std::string& number) {
   if (number.empty()) {
     return absl::InvalidArgumentError("Empty number");
   }
@@ -344,8 +344,8 @@
   return res.value();
 }
 
-absl::Status CheriotRenode::SetConfig(const char *config_names[],
-                                      const char *config_values[], int size) {
+absl::Status CheriotRenode::SetConfig(const char* config_names[],
+                                      const char* config_values[], int size) {
   std::string icache_cfg;
   std::string dcache_cfg;
   uint64_t tagged_memory_base = 0;
@@ -443,7 +443,7 @@
     instrumentation_control_ = new CheriotInstrumentationControl(
         cmd_shell_, cheriot_top_, mem_profiler_);
     cmd_shell_->AddCore(
-        {static_cast<CheriotDebugInterface *>(cheriot_cli_forwarder_),
+        {static_cast<CheriotDebugInterface*>(cheriot_cli_forwarder_),
          [this]() { return program_loader_; }, cheriot_state_});
     cmd_shell_->AddCommand(
         instrumentation_control_->Usage(),
@@ -462,7 +462,7 @@
     ComponentValueEntry icache_value;
     icache_value.set_name("icache");
     icache_value.set_string_value(icache_cfg);
-    auto *cfg = cheriot_top_->GetConfig("icache");
+    auto* cfg = cheriot_top_->GetConfig("icache");
     auto status = cfg->Import(&icache_value);
     if (!status.ok()) return status;
   }
@@ -470,11 +470,11 @@
     ComponentValueEntry dcache_value;
     dcache_value.set_name("dcache");
     dcache_value.set_string_value(dcache_cfg);
-    auto *cfg = cheriot_top_->GetConfig("dcache");
+    auto* cfg = cheriot_top_->GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return status;
     // Hook the cache into the memory port.
-    auto *dcache = cheriot_top_->dcache();
+    auto* dcache = cheriot_top_->dcache();
     dcache->set_tagged_memory(cheriot_top_->state()->tagged_memory());
     cheriot_top_->state()->set_tagged_memory(dcache);
   }
@@ -498,30 +498,30 @@
   }
 }
 
-absl::Status CheriotRenode::InitializeSimulator(const std::string &cpu_type) {
+absl::Status CheriotRenode::InitializeSimulator(const std::string& cpu_type) {
   router_ = new mpact::sim::util::SingleInitiatorRouter(name_ + "_router");
   renode_router_ =
       new mpact::sim::util::SingleInitiatorRouter(name_ + "_renode_router");
-  auto *data_memory = static_cast<TaggedMemoryInterface *>(router_);
+  auto* data_memory = static_cast<TaggedMemoryInterface*>(router_);
   // Instantiate memory profiler, but disable it until the config information
   // has been received.
   mem_profiler_ = new TaggedMemoryUseProfiler(data_memory);
   data_memory = mem_profiler_;
   mem_profiler_->set_is_enabled(false);
   cheriot_state_ = new CheriotState(
-      "CherIoT", data_memory, static_cast<AtomicMemoryOpInterface *>(router_));
+      "CherIoT", data_memory, static_cast<AtomicMemoryOpInterface*>(router_));
   // First create the decoder according to the cpu type.
   if (cpu_type == kBaseName) {
     cheriot_decoder_ = new CheriotDecoder(
-        cheriot_state_, static_cast<MemoryInterface *>(router_));
+        cheriot_state_, static_cast<MemoryInterface*>(router_));
     cpu_type_ = CheriotCpuType::kBase;
   } else if (cpu_type == kRvvName) {
     cheriot_decoder_ = new CheriotRVVDecoder(
-        cheriot_state_, static_cast<MemoryInterface *>(router_));
+        cheriot_state_, static_cast<MemoryInterface*>(router_));
     cpu_type_ = CheriotCpuType::kRvv;
   } else if (cpu_type == kRvvFpName) {
     cheriot_decoder_ = new CheriotRVVFPDecoder(
-        cheriot_state_, static_cast<MemoryInterface *>(router_));
+        cheriot_state_, static_cast<MemoryInterface*>(router_));
     cpu_type_ = CheriotCpuType::kRvvFp;
   } else {
     return absl::NotFoundError(
@@ -538,10 +538,10 @@
     return absl::InternalError(
         absl::StrCat(name_, ": Error while initializing minstret/minstreth\n"));
   }
-  auto *minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
+  auto* minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(
       minstret_res.value());
-  auto *minstreth =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(minstreth_res.value());
+  auto* minstreth =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(minstreth_res.value());
   minstret->set_counter(cheriot_top_->counter_num_instructions());
   minstreth->set_counter(cheriot_top_->counter_num_instructions());
   // Initialize mcycle/mcycleh. Bind the instruction counter to those
@@ -552,10 +552,10 @@
     return absl::InternalError(
         absl::StrCat(name_, ": Error while initializing mcycle/mcycleh\n"));
   }
-  auto *mcycle = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
-      mcycle_res.value());
-  auto *mcycleh =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(mcycleh_res.value());
+  auto* mcycle =
+      static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(mcycle_res.value());
+  auto* mcycleh =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(mcycleh_res.value());
   mcycle->set_counter(cheriot_top_->counter_num_cycles());
   mcycleh->set_counter(cheriot_top_->counter_num_cycles());
   // Set up the memory router with the system bus. Other devices are added once
@@ -586,10 +586,10 @@
   // Set up semihosting.
   semihost_ =
       new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord32,
-                           static_cast<MemoryInterface *>(router_),
-                           static_cast<MemoryInterface *>(renode_router_));
+                           static_cast<MemoryInterface*>(router_),
+                           static_cast<MemoryInterface*>(renode_router_));
   // Set up special handlers (ebreak, wfi, ecall).
-  cheriot_top_->state()->AddEbreakHandler([this](const Instruction *inst) {
+  cheriot_top_->state()->AddEbreakHandler([this](const Instruction* inst) {
     if (this->semihost_->IsSemihostingCall(inst)) {
       this->semihost_->OnEBreak(inst);
       return true;
@@ -600,9 +600,8 @@
     }
     return false;
   });
-  cheriot_top_->state()->set_on_wfi([](const Instruction *) { return true; });
-  cheriot_top_->state()->set_on_ecall(
-      [](const Instruction *) { return false; });
+  cheriot_top_->state()->set_on_wfi([](const Instruction*) { return true; });
+  cheriot_top_->state()->set_on_ecall([](const Instruction*) { return false; });
   semihost_->set_exit_callback([this]() {
     this->cheriot_top_->RequestHalt(HaltReason::kProgramDone, nullptr);
   });

diff --git a/cheriot/cheriot_renode.h b/cheriot/cheriot_renode.h
index 44b603c..c61db7a 100644
--- a/cheriot/cheriot_renode.h
+++ b/cheriot/cheriot_renode.h

@@ -56,8 +56,8 @@
 // a combined ReNode/CLI interface that manages the priorities and access of
 // ReNode and command line commands to the simulator control class.
 
-extern ::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
-    std::string name, ::mpact::sim::util::MemoryInterface *renode_sysbus);
+extern ::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
+    std::string name, ::mpact::sim::util::MemoryInterface* renode_sysbus);
 
 namespace mpact {
 namespace sim {
@@ -107,10 +107,10 @@
 
   // Constructor takes a name and a memory interface that is used for memory
   // transactions routed to the system bus.
-  CheriotRenode(std::string name, MemoryInterface *renode_sysbus);
+  CheriotRenode(std::string name, MemoryInterface* renode_sysbus);
   ~CheriotRenode() override;
 
-  absl::StatusOr<uint64_t> LoadExecutable(const char *elf_file_name,
+  absl::StatusOr<uint64_t> LoadExecutable(const char* elf_file_name,
                                           bool for_symbols_only) override;
   // Step the core by num instructions.
   absl::StatusOr<int> Step(int num) override;
@@ -121,18 +121,18 @@
   absl::Status WriteRegister(uint32_t reg_id, uint64_t value) override;
   // Get register data buffer call. Not implemented, stubbed out to return null.
   // Read/write the buffers to memory.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
   // Return register information.
   int32_t GetRenodeRegisterInfoSize() const override;
-  absl::Status GetRenodeRegisterInfo(int32_t index, int32_t max_len, char *name,
-                                     RenodeCpuRegister &info) override;
+  absl::Status GetRenodeRegisterInfo(int32_t index, int32_t max_len, char* name,
+                                     RenodeCpuRegister& info) override;
 
   // Set configuration value.
-  absl::Status SetConfig(const char *config_names[],
-                         const char *config_values[], int size) override;
+  absl::Status SetConfig(const char* config_names[],
+                         const char* config_values[], int size) override;
 
   // Set IRQ value for supported IRQs. Supported irq_nums are:
   //          MachineSoftwareInterrupt = 0x3
@@ -141,31 +141,31 @@
   // These correspond to the msip and meip bits of the mip register.
   absl::Status SetIrqValue(int32_t irq_num, bool irq_value) override;
 
-  absl::Status InitializeSimulator(const std::string &cpu_type);
+  absl::Status InitializeSimulator(const std::string& cpu_type);
 
  private:
   std::string name_;
-  MemoryInterface *renode_sysbus_ = nullptr;
-  TaggedMemoryInterface *data_memory_ = nullptr;
-  TaggedMemoryInterface *tagged_sysbus_ = nullptr;
-  CheriotState *cheriot_state_ = nullptr;
-  DecoderInterface *cheriot_decoder_ = nullptr;
-  CheriotTop *cheriot_top_ = nullptr;
-  RiscVArmSemihost *semihost_ = nullptr;
-  SingleInitiatorRouter *router_ = nullptr;
-  SingleInitiatorRouter *renode_router_ = nullptr;
+  MemoryInterface* renode_sysbus_ = nullptr;
+  TaggedMemoryInterface* data_memory_ = nullptr;
+  TaggedMemoryInterface* tagged_sysbus_ = nullptr;
+  CheriotState* cheriot_state_ = nullptr;
+  DecoderInterface* cheriot_decoder_ = nullptr;
+  CheriotTop* cheriot_top_ = nullptr;
+  RiscVArmSemihost* semihost_ = nullptr;
+  SingleInitiatorRouter* router_ = nullptr;
+  SingleInitiatorRouter* renode_router_ = nullptr;
   DataBufferFactory db_factory_;
-  AtomicMemory *atomic_memory_ = nullptr;
-  TaggedFlatDemandMemory *tagged_memory_ = nullptr;
-  RiscVClint *clint_ = nullptr;
-  SocketCLI *socket_cli_ = nullptr;
-  CheriotRenodeCLITop *cheriot_renode_cli_top_ = nullptr;
-  CheriotCLIForwarder *cheriot_cli_forwarder_ = nullptr;
-  ElfProgramLoader *program_loader_ = nullptr;
-  DebugCommandShell *cmd_shell_ = nullptr;
-  InstructionProfiler *inst_profiler_ = nullptr;
-  TaggedMemoryUseProfiler *mem_profiler_ = nullptr;
-  CheriotInstrumentationControl *instrumentation_control_ = nullptr;
+  AtomicMemory* atomic_memory_ = nullptr;
+  TaggedFlatDemandMemory* tagged_memory_ = nullptr;
+  RiscVClint* clint_ = nullptr;
+  SocketCLI* socket_cli_ = nullptr;
+  CheriotRenodeCLITop* cheriot_renode_cli_top_ = nullptr;
+  CheriotCLIForwarder* cheriot_cli_forwarder_ = nullptr;
+  ElfProgramLoader* program_loader_ = nullptr;
+  DebugCommandShell* cmd_shell_ = nullptr;
+  InstructionProfiler* inst_profiler_ = nullptr;
+  TaggedMemoryUseProfiler* mem_profiler_ = nullptr;
+  CheriotInstrumentationControl* instrumentation_control_ = nullptr;
   CheriotCpuType cpu_type_ = CheriotCpuType::kBase;
 };
 

diff --git a/cheriot/cheriot_renode_cli_top.cc b/cheriot/cheriot_renode_cli_top.cc
index 32ebab0..69635ef 100644
--- a/cheriot/cheriot_renode_cli_top.cc
+++ b/cheriot/cheriot_renode_cli_top.cc

@@ -31,13 +31,13 @@
 namespace sim {
 namespace cheriot {
 
-CheriotRenodeCLITop::CheriotRenodeCLITop(CheriotTop *cheriot_top,
+CheriotRenodeCLITop::CheriotRenodeCLITop(CheriotTop* cheriot_top,
                                          bool wait_for_cli)
     : util::renode::RenodeCLITop(cheriot_top, wait_for_cli),
       cheriot_top_(cheriot_top) {}
 
 absl::StatusOr<size_t> CheriotRenodeCLITop::CLIReadTagMemory(uint64_t address,
-                                                             void *buf,
+                                                             void* buf,
                                                              size_t length) {
   return DoWhenInControl<absl::StatusOr<size_t>>(
       [this, address, buf, length]() {

diff --git a/cheriot/cheriot_renode_cli_top.h b/cheriot/cheriot_renode_cli_top.h
index 0aa4320..e37266f 100644
--- a/cheriot/cheriot_renode_cli_top.h
+++ b/cheriot/cheriot_renode_cli_top.h

@@ -35,9 +35,9 @@
 // CherIoT CLI.
 class CheriotRenodeCLITop : public util::renode::RenodeCLITop {
  public:
-  CheriotRenodeCLITop(CheriotTop *cheriot_top, bool wait_for_cli);
+  CheriotRenodeCLITop(CheriotTop* cheriot_top, bool wait_for_cli);
 
-  absl::StatusOr<size_t> CLIReadTagMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> CLIReadTagMemory(uint64_t address, void* buf,
                                           size_t length);
 
   absl::Status CLISetDataWatchpoint(uint64_t address, size_t length,
@@ -53,7 +53,7 @@
   absl::Status CLIDisableAction(uint64_t address, int id);
 
  private:
-  CheriotTop *cheriot_top_ = nullptr;
+  CheriotTop* cheriot_top_ = nullptr;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_renode_register_info.cc b/cheriot/cheriot_renode_register_info.cc
index 96f0dba..3ff7e7c 100644
--- a/cheriot/cheriot_renode_register_info.cc
+++ b/cheriot/cheriot_renode_register_info.cc

@@ -23,7 +23,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT - used below.
 
-CheriotRenodeRegisterInfo *CheriotRenodeRegisterInfo::instance_ = nullptr;
+CheriotRenodeRegisterInfo* CheriotRenodeRegisterInfo::instance_ = nullptr;
 
 void CheriotRenodeRegisterInfo::InitializeRenodeRegisterInfo() {
   using DbgReg = DebugRegisterEnum;
@@ -69,19 +69,19 @@
   InitializeRenodeRegisterInfo();
 }
 
-const CheriotRenodeRegisterInfo::RenodeRegisterInfo &
+const CheriotRenodeRegisterInfo::RenodeRegisterInfo&
 CheriotRenodeRegisterInfo::GetRenodeRegisterInfo() {
   return Instance()->GetRenodeRegisterInfoPrivate();
 }
 
-CheriotRenodeRegisterInfo *CheriotRenodeRegisterInfo::Instance() {
+CheriotRenodeRegisterInfo* CheriotRenodeRegisterInfo::Instance() {
   if (instance_ == nullptr) {
     instance_ = new CheriotRenodeRegisterInfo();
   }
   return instance_;
 }
 
-const CheriotRenodeRegisterInfo::RenodeRegisterInfo &
+const CheriotRenodeRegisterInfo::RenodeRegisterInfo&
 CheriotRenodeRegisterInfo::GetRenodeRegisterInfoPrivate() {
   return renode_register_info_;
 }

diff --git a/cheriot/cheriot_renode_register_info.h b/cheriot/cheriot_renode_register_info.h
index 84d5a00..7fbfc7c 100644
--- a/cheriot/cheriot_renode_register_info.h
+++ b/cheriot/cheriot_renode_register_info.h

@@ -32,15 +32,15 @@
  public:
   using RenodeRegisterInfo = std::vector<util::renode::RenodeCpuRegister>;
 
-  static const RenodeRegisterInfo &GetRenodeRegisterInfo();
+  static const RenodeRegisterInfo& GetRenodeRegisterInfo();
 
  private:
   CheriotRenodeRegisterInfo();
-  static CheriotRenodeRegisterInfo *Instance();
+  static CheriotRenodeRegisterInfo* Instance();
   void InitializeRenodeRegisterInfo();
-  const RenodeRegisterInfo &GetRenodeRegisterInfoPrivate();
+  const RenodeRegisterInfo& GetRenodeRegisterInfoPrivate();
 
-  static CheriotRenodeRegisterInfo *instance_;
+  static CheriotRenodeRegisterInfo* instance_;
   RenodeRegisterInfo renode_register_info_;
 };
 

diff --git a/cheriot/cheriot_rvv_decoder.cc b/cheriot/cheriot_rvv_decoder.cc
index bd576d8..4315da3 100644
--- a/cheriot/cheriot_rvv_decoder.cc
+++ b/cheriot/cheriot_rvv_decoder.cc

@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-CheriotRVVDecoder::CheriotRVVDecoder(CheriotState *state,
-                                     util::MemoryInterface *memory)
+CheriotRVVDecoder::CheriotRVVDecoder(CheriotState* state,
+                                     util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Need a data buffer to load instructions from memory. Allocate a single
   // buffer that can be reused for each instruction word.
@@ -55,16 +55,16 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *CheriotRVVDecoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* CheriotRVVDecoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32_rvv::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAddressMisaligned, inst->address() ^ 0x1,
                    inst);
@@ -75,12 +75,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32_rvv::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAccessFault, inst->address(), nullptr);
     });
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = cheriot_rvv_isa_->Decode(address, cheriot_rvv_encoding_);
+  auto* instruction = cheriot_rvv_isa_->Decode(address, cheriot_rvv_encoding_);
   return instruction;
 }
 

diff --git a/cheriot/cheriot_rvv_decoder.h b/cheriot/cheriot_rvv_decoder.h
index 6731ab1..7567494 100644
--- a/cheriot/cheriot_rvv_decoder.h
+++ b/cheriot/cheriot_rvv_decoder.h

@@ -43,7 +43,7 @@
     : public isa32_rvv::RiscVCheriotRVVInstructionSetFactory {
  public:
   std::unique_ptr<isa32_rvv::RiscvCheriotRvvSlot> CreateRiscvCheriotRvvSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32_rvv::RiscvCheriotRvvSlot>(state);
   }
 };
@@ -55,37 +55,37 @@
   using SlotEnum = isa32_rvv::SlotEnum;
   using OpcodeEnum = isa32_rvv::OpcodeEnum;
 
-  CheriotRVVDecoder(CheriotState *state, util::MemoryInterface *memory);
+  CheriotRVVDecoder(CheriotState* state, util::MemoryInterface* memory);
   CheriotRVVDecoder() = delete;
   ~CheriotRVVDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
 
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override {
     return static_cast<int>(OpcodeEnum::kPastMaxValue);
   }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32_rvv::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32_rvv::RiscVCheriotRVVEncoding *cheriot_rvv_encoding() const {
+  isa32_rvv::RiscVCheriotRVVEncoding* cheriot_rvv_encoding() const {
     return cheriot_rvv_encoding_;
   }
 
  private:
-  CheriotState *state_;
-  util::MemoryInterface *memory_;
+  CheriotState* state_;
+  util::MemoryInterface* memory_;
   generic::DataBufferFactory db_factory_;
-  generic::DataBuffer *inst_db_;
-  isa32_rvv::RiscVCheriotRVVEncoding *cheriot_rvv_encoding_;
-  isa32_rvv::RiscVCheriotRVVInstructionSetFactory *cheriot_rvv_isa_factory_;
-  isa32_rvv::RiscVCheriotRVVInstructionSet *cheriot_rvv_isa_;
+  generic::DataBuffer* inst_db_;
+  isa32_rvv::RiscVCheriotRVVEncoding* cheriot_rvv_encoding_;
+  isa32_rvv::RiscVCheriotRVVInstructionSetFactory* cheriot_rvv_isa_factory_;
+  isa32_rvv::RiscVCheriotRVVInstructionSet* cheriot_rvv_isa_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_rvv_fp_decoder.cc b/cheriot/cheriot_rvv_fp_decoder.cc
index d6d3b74..dff3ea9 100644
--- a/cheriot/cheriot_rvv_fp_decoder.cc
+++ b/cheriot/cheriot_rvv_fp_decoder.cc

@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-CheriotRVVFPDecoder::CheriotRVVFPDecoder(CheriotState *state,
-                                         util::MemoryInterface *memory)
+CheriotRVVFPDecoder::CheriotRVVFPDecoder(CheriotState* state,
+                                         util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Need a data buffer to load instructions from memory. Allocate a single
   // buffer that can be reused for each instruction word.
@@ -55,16 +55,16 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *CheriotRVVFPDecoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* CheriotRVVFPDecoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32_rvv_fp::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAddressMisaligned, inst->address() ^ 0x1,
                    inst);
@@ -75,12 +75,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32_rvv_fp::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAccessFault, inst->address(), nullptr);
     });
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction =
+  auto* instruction =
       cheriot_rvv_fp_isa_->Decode(address, cheriot_rvv_fp_encoding_);
   return instruction;
 }

diff --git a/cheriot/cheriot_rvv_fp_decoder.h b/cheriot/cheriot_rvv_fp_decoder.h
index 3693dea..504d572 100644
--- a/cheriot/cheriot_rvv_fp_decoder.h
+++ b/cheriot/cheriot_rvv_fp_decoder.h

@@ -43,7 +43,7 @@
     : public isa32_rvv_fp::RiscVCheriotRVVFpInstructionSetFactory {
  public:
   std::unique_ptr<isa32_rvv_fp::RiscvCheriotRvvFpSlot>
-  CreateRiscvCheriotRvvFpSlot(ArchState *state) override {
+  CreateRiscvCheriotRvvFpSlot(ArchState* state) override {
     return std::make_unique<isa32_rvv_fp::RiscvCheriotRvvFpSlot>(state);
   }
 };
@@ -55,38 +55,38 @@
   using SlotEnum = isa32_rvv_fp::SlotEnum;
   using OpcodeEnum = isa32_rvv_fp::OpcodeEnum;
 
-  CheriotRVVFPDecoder(CheriotState *state, util::MemoryInterface *memory);
+  CheriotRVVFPDecoder(CheriotState* state, util::MemoryInterface* memory);
   CheriotRVVFPDecoder() = delete;
   ~CheriotRVVFPDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
 
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override {
     return static_cast<int>(OpcodeEnum::kPastMaxValue);
   }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32_rvv_fp::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32_rvv_fp::RiscVCheriotRVVFPEncoding *cheriot_rvv_fp_encoding() const {
+  isa32_rvv_fp::RiscVCheriotRVVFPEncoding* cheriot_rvv_fp_encoding() const {
     return cheriot_rvv_fp_encoding_;
   }
 
  private:
-  CheriotState *state_;
-  util::MemoryInterface *memory_;
+  CheriotState* state_;
+  util::MemoryInterface* memory_;
   generic::DataBufferFactory db_factory_;
-  generic::DataBuffer *inst_db_;
-  isa32_rvv_fp::RiscVCheriotRVVFPEncoding *cheriot_rvv_fp_encoding_;
-  isa32_rvv_fp::RiscVCheriotRVVFpInstructionSetFactory
-      *cheriot_rvv_fp_isa_factory_;
-  isa32_rvv_fp::RiscVCheriotRVVFpInstructionSet *cheriot_rvv_fp_isa_;
+  generic::DataBuffer* inst_db_;
+  isa32_rvv_fp::RiscVCheriotRVVFPEncoding* cheriot_rvv_fp_encoding_;
+  isa32_rvv_fp::RiscVCheriotRVVFpInstructionSetFactory*
+      cheriot_rvv_fp_isa_factory_;
+  isa32_rvv_fp::RiscVCheriotRVVFpInstructionSet* cheriot_rvv_fp_isa_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_rvv_fp_getters.h b/cheriot/cheriot_rvv_fp_getters.h
index c3eee6b..ef4795c 100644
--- a/cheriot/cheriot_rvv_fp_getters.h
+++ b/cheriot/cheriot_rvv_fp_getters.h

@@ -34,14 +34,14 @@
 using ::mpact::sim::riscv::RVFpRegister;
 
 using SourceOpGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
 using DestOpGetterMap =
     absl::flat_hash_map<int,
-                        absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+                        absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
 template <typename Enum, typename Extractors>
-void AddCheriotRVVFPSourceGetters(SourceOpGetterMap &getter_map,
-                                  RiscVCheriotEncodingCommon *common) {
+void AddCheriotRVVFPSourceGetters(SourceOpGetterMap& getter_map,
+                                  RiscVCheriotEncodingCommon* common) {
   Insert(getter_map, *Enum::kFs1, [common]() {
     int num = Extractors::VArith::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<RVFpRegister>(
@@ -50,8 +50,8 @@
 }
 
 template <typename Enum, typename Extractors>
-void AddCheriotRVVFPDestGetters(DestOpGetterMap &getter_map,
-                                RiscVCheriotEncodingCommon *common) {
+void AddCheriotRVVFPDestGetters(DestOpGetterMap& getter_map,
+                                RiscVCheriotEncodingCommon* common) {
   Insert(getter_map, *Enum::kFd, [common](int latency) {
     int num = Extractors::VArith::ExtractRd(common->inst_word());
     return GetRegisterDestinationOp<RVFpRegister>(

diff --git a/cheriot/cheriot_rvv_getters.h b/cheriot/cheriot_rvv_getters.h
index 2b34d93..aaa36d9 100644
--- a/cheriot/cheriot_rvv_getters.h
+++ b/cheriot/cheriot_rvv_getters.h

@@ -41,47 +41,47 @@
 using ::mpact::sim::riscv::RVVectorRegister;
 
 using SourceOpGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
 using DestOpGetterMap =
     absl::flat_hash_map<int,
-                        absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+                        absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
 template <typename Enum, typename Extractors>
-void AddCheriotRVVSourceGetters(SourceOpGetterMap &getter_map,
-                                RiscVCheriotEncodingCommon *common) {
-  Insert(getter_map, *Enum::kConst1, []() -> SourceOperandInterface * {
+void AddCheriotRVVSourceGetters(SourceOpGetterMap& getter_map,
+                                RiscVCheriotEncodingCommon* common) {
+  Insert(getter_map, *Enum::kConst1, []() -> SourceOperandInterface* {
     return new IntLiteralOperand<1>();
   });
-  Insert(getter_map, *Enum::kConst2, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst2, []() -> SourceOperandInterface* {
     return new IntLiteralOperand<2>();
   });
-  Insert(getter_map, *Enum::kConst4, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst4, []() -> SourceOperandInterface* {
     return new IntLiteralOperand<4>();
   });
-  Insert(getter_map, *Enum::kConst8, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst8, []() -> SourceOperandInterface* {
     return new IntLiteralOperand<8>();
   });
-  Insert(getter_map, *Enum::kNf, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kNf, [common]() -> SourceOperandInterface* {
     auto imm = Extractors::VMem::ExtractNf(common->inst_word());
     return new ImmediateOperand<uint32_t>(imm);
   });
-  Insert(getter_map, *Enum::kSimm5, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kSimm5, [common]() -> SourceOperandInterface* {
     auto imm = Extractors::VArith::ExtractSimm5(common->inst_word());
     return new ImmediateOperand<uint32_t>(imm);
   });
-  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface* {
     auto imm = Extractors::VArith::ExtractUimm5(common->inst_word());
     return new ImmediateOperand<int32_t>(imm);
   });
-  Insert(getter_map, *Enum::kVd, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVd, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVd(common->inst_word());
     return GetVectorRegisterSourceOp<RVVectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVm, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVm, [common]() -> SourceOperandInterface* {
     auto vm = Extractors::VArith::ExtractVm(common->inst_word());
     return new ImmediateOperand<uint32_t>(vm);
   });
-  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface* {
     auto vm = Extractors::VArith::ExtractVm(common->inst_word());
     if (vm == 1) {
       // Unmasked, return the True mask.
@@ -90,36 +90,36 @@
     // Masked. Return the mask register.
     return GetVectorMaskRegisterSourceOp<RVVectorRegister>(common->state(), 0);
   });
-  Insert(getter_map, *Enum::kVmaskTrue, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVmaskTrue, [common]() -> SourceOperandInterface* {
     return new CheriotVectorTrueOperand(common->state());
   });
-  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs1(common->inst_word());
     return GetVectorRegisterSourceOp<RVVectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs2(common->inst_word());
     return GetVectorRegisterSourceOp<RVVectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVs3, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs3, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VMem::ExtractVs3(common->inst_word());
     return GetVectorRegisterSourceOp<RVVectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kZimm10, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kZimm10, [common]() -> SourceOperandInterface* {
     auto imm = Extractors::VConfig::ExtractZimm10(common->inst_word());
     return new ImmediateOperand<uint32_t>(imm);
   });
-  Insert(getter_map, *Enum::kZimm11, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kZimm11, [common]() -> SourceOperandInterface* {
     auto imm = Extractors::VConfig::ExtractZimm11(common->inst_word());
     return new ImmediateOperand<uint32_t>(imm);
   });
 }
 
 template <typename Enum, typename Extractors>
-void AddCheriotRVVDestGetters(DestOpGetterMap &getter_map,
-                              RiscVCheriotEncodingCommon *common) {
+void AddCheriotRVVDestGetters(DestOpGetterMap& getter_map,
+                              RiscVCheriotEncodingCommon* common) {
   Insert(getter_map, Enum::kVd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            auto num = Extractors::VArith::ExtractVd(common->inst_word());
            return GetVectorRegisterDestinationOp<RVVectorRegister>(
                common->state(), latency, num);

diff --git a/cheriot/cheriot_state.cc b/cheriot/cheriot_state.cc
index 6caa2c0..d1dff0f 100644
--- a/cheriot/cheriot_state.cc
+++ b/cheriot/cheriot_state.cc

@@ -87,9 +87,9 @@
 // This creates the CSR and assigns it to a pointer in the state object. Type
 // can be inferred from the state object pointer.
 template <typename T, typename... Ps>
-T *CreateCsr(CheriotState *state, T *&ptr,
-             std::vector<RiscVCsrInterface *> &csr_vec, Ps... pargs) {
-  auto *csr = new T(pargs...);
+T* CreateCsr(CheriotState* state, T*& ptr,
+             std::vector<RiscVCsrInterface*>& csr_vec, Ps... pargs) {
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -106,9 +106,9 @@
 // that pointer is of abstract type, so the CSR type cannot be inferred, but
 // has to be specified in the call.
 template <typename T, typename... Ps>
-T *CreateCsr(CheriotState *state, RiscVCsrInterface *&ptr,
-             std::vector<RiscVCsrInterface *> &csr_vec, Ps... pargs) {
-  auto *csr = new T(pargs...);
+T* CreateCsr(CheriotState* state, RiscVCsrInterface*& ptr,
+             std::vector<RiscVCsrInterface*>& csr_vec, Ps... pargs) {
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -125,9 +125,9 @@
 // object. That means the type cannot be inferred, but has to be specified
 // in the call.
 template <typename T, typename... Ps>
-T *CreateCsr(CheriotState *state, std::vector<RiscVCsrInterface *> &csr_vec,
+T* CreateCsr(CheriotState* state, std::vector<RiscVCsrInterface*>& csr_vec,
              Ps... pargs) {
-  auto *csr = new T(pargs...);
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -142,12 +142,11 @@
 // Templated helper function that is used to create the set of CSRs needed
 // for simulation.
 template <typename T>
-void CreateCsrs(CheriotState *state,
-                std::vector<RiscVCsrInterface *> &csr_vec) {
+void CreateCsrs(CheriotState* state, std::vector<RiscVCsrInterface*>& csr_vec) {
   absl::Status result;
   // Create CSRs.
   // misa
-  auto *misa = CreateCsr(state, state->misa_, csr_vec,
+  auto* misa = CreateCsr(state, state->misa_, csr_vec,
                          CsrInfo<T>::kMisaInitialValue, state);
   CHECK_NE(misa, nullptr);
   // mtvec is replaced by mtcc
@@ -160,11 +159,11 @@
 
   // Mip and Mie are always 32 bit.
   // mip
-  auto *mip = CreateCsr(state, state->mip_, csr_vec, 0, state);
+  auto* mip = CreateCsr(state, state->mip_, csr_vec, 0, state);
   CHECK_NE(mip, nullptr);
 
   // mie
-  auto *mie = CreateCsr(state, state->mie_, csr_vec, 0, state);
+  auto* mie = CreateCsr(state, state->mie_, csr_vec, 0, state);
   CHECK_NE(mie, nullptr);
 
   // mhartid
@@ -185,48 +184,48 @@
   // mideleg - machine mode interrupt delegation register. Not used.
 
   // mstatus
-  auto *mstatus =
+  auto* mstatus =
       CreateCsr(state, state->mstatus_, csr_vec,
                 CsrInfo<uint32_t>::kMstatusInitialValue, state, misa);
   CHECK_NE(mstatus, nullptr);
   // mtval
-  auto *mtval = CreateCsr<RiscVSimpleCsr<T>>(
+  auto* mtval = CreateCsr<RiscVSimpleCsr<T>>(
       state, state->mtval_, csr_vec, "mtval", *RiscVCsrEnum::kMTval, 0, state);
   CHECK_NE(mtval, nullptr);
 
   // minstret/minstreth
-  auto *minstret = CreateCsr<RiscVCounterCsr<T, CheriotState>>(
+  auto* minstret = CreateCsr<RiscVCounterCsr<T, CheriotState>>(
       state, csr_vec, "minstret", RiscVCsrEnum ::kMInstret, state);
   CHECK_NE(minstret, nullptr);
   auto minstreth = CreateCsr<RiscVCounterCsrHigh<CheriotState>>(
       state, csr_vec, "minstreth", RiscVCsrEnum::kMInstretH, state,
-      reinterpret_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(minstret));
+      reinterpret_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(minstret));
   CHECK_NE(minstreth, nullptr);
   // mcycle/mcycleh
-  auto *mcycle = CreateCsr<RiscVCounterCsr<T, CheriotState>>(
+  auto* mcycle = CreateCsr<RiscVCounterCsr<T, CheriotState>>(
       state, csr_vec, "mcycle", RiscVCsrEnum::kMCycle, state);
   CHECK_NE(mcycle, nullptr);
-  auto *mcycleh = CreateCsr<RiscVCounterCsrHigh<CheriotState>>(
+  auto* mcycleh = CreateCsr<RiscVCounterCsrHigh<CheriotState>>(
       state, csr_vec, "mcycleh", RiscVCsrEnum::kMCycleH, state,
-      reinterpret_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(mcycle));
+      reinterpret_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(mcycle));
   CHECK_NE(mcycleh, nullptr);
 
   // Stack high water mark CSRs. Mshwm gets updated automatically during
   // execution. mshwm
-  auto *mshwm = CreateCsr<RiscVSimpleCsr<T>>(
+  auto* mshwm = CreateCsr<RiscVSimpleCsr<T>>(
       state, state->mshwm_, csr_vec, "mshwm", *RiscVCheriotCsrEnum::kMshwm,
       /*initial_value=*/0,
       /*read_mask=*/0xffff'fff0, /*write_mask=*/0xffff'fff0, state);
   CHECK_NE(mshwm, nullptr);
   // mshwmb
-  auto *mshwmb = CreateCsr<RiscVSimpleCsr<T>>(
+  auto* mshwmb = CreateCsr<RiscVSimpleCsr<T>>(
       state, state->mshwmb_, csr_vec, "mshwmb", *RiscVCheriotCsrEnum::kMshwmb,
       /*initial_value=*/0,
       /*read_mask=*/0xffff'fff0, /*write_mask=*/0xffff'fff0, state);
   CHECK_NE(mshwmb, nullptr);
 
   // mccsr.
-  auto *mccsr = CreateCsr<RiscVSimpleCsr<T>>(
+  auto* mccsr = CreateCsr<RiscVSimpleCsr<T>>(
       state, csr_vec, "mccsr", *RiscVCheriotCsrEnum::kMCcsr,
       /*initial_value=*/0x3,
       /*read_mask=*/0x3, /*write_mask=*/0x2, state);
@@ -269,14 +268,14 @@
 constexpr uint64_t kRiscv32MaxMemorySize = 0x3f'ffff'ffffULL;
 
 CheriotState::CheriotState(std::string_view id,
-                           util::TaggedMemoryInterface *memory,
-                           util::AtomicMemoryOpInterface *atomic_memory)
+                           util::TaggedMemoryInterface* memory,
+                           util::AtomicMemoryOpInterface* atomic_memory)
     : generic::ArchState(id),
       tagged_memory_(memory),
       atomic_tagged_memory_(atomic_memory),
       counter_interrupts_taken_("interrupts_taken", 0),
       counter_interrupt_returns_("interrupt_returns", 0) {
-  for (auto &[name, index] : std::vector<std::pair<std::string, unsigned>>{
+  for (auto& [name, index] : std::vector<std::pair<std::string, unsigned>>{
            {"c0", 0b0'00000},   {"c1", 0b0'00001},   {"c2", 0b0'00010},
            {"c3", 0b0'00011},   {"c4", 0b0'00100},   {"c5", 0b0'00101},
            {"c6", 0b0'00110},   {"c7", 0b0'00111},   {"c8", 0b0'01000},
@@ -346,7 +345,7 @@
   delete sealing_root_;
   delete memory_root_;
   delete pc_src_operand_;
-  for (auto *csr : csr_vec_) delete csr;
+  for (auto* csr : csr_vec_) delete csr;
   delete csr_set_;
   delete pmp_;
   delete temp_reg_;
@@ -354,7 +353,7 @@
 }
 
 void CheriotState::Reset() {
-  for (auto &[unused, reg_ptr] : *registers()) {
+  for (auto& [unused, reg_ptr] : *registers()) {
     reg_ptr->data_buffer()->Set<uint32_t>(0, 0);
   }
   // Reset CSRs.
@@ -375,13 +374,13 @@
   csr_set_->GetCsr("misa").value()->Set(CsrInfo<uint32_t>::kMisaInitialValue);
 }
 
-void CheriotState::HandleCheriRegException(const Instruction *instruction,
+void CheriotState::HandleCheriRegException(const Instruction* instruction,
                                            uint64_t epc, ExceptionCode code,
-                                           const CheriotRegister *reg) {
+                                           const CheriotRegister* reg) {
   // Map the CHERIoT exception to a RiscV trap.
   unsigned mcause = kCheriExceptionCode;
   uint32_t mtval = *code & 0b1'1111;
-  auto const &name = reg->name();
+  auto const& name = reg->name();
   auto iter = cap_index_map_.find(name);
   uint32_t cap_index = 0x1f;  // Set to a default value.
   if (iter != cap_index_map_.end()) {
@@ -399,10 +398,10 @@
   min_physical_address_ = std::min(min_physical_address, max_physical_address_);
 }
 
-void CheriotState::LoadCapability(const Instruction *instruction,
-                                  uint32_t address, DataBuffer *db,
-                                  DataBuffer *tags, Instruction *child,
-                                  CapabilityLoadContext32 *context) {
+void CheriotState::LoadCapability(const Instruction* instruction,
+                                  uint32_t address, DataBuffer* db,
+                                  DataBuffer* tags, Instruction* child,
+                                  CapabilityLoadContext32* context) {
   // Check for alignment.
   uint64_t mask = db->size<uint8_t>() - 1;
   if ((address & mask) != 0) {
@@ -426,9 +425,9 @@
   load_tags_->IncRef();
 }
 
-void CheriotState::StoreCapability(const Instruction *instruction,
-                                   uint32_t address, DataBuffer *db,
-                                   DataBuffer *tags) {
+void CheriotState::StoreCapability(const Instruction* instruction,
+                                   uint32_t address, DataBuffer* db,
+                                   DataBuffer* tags) {
   // Check for alignment.
   uint64_t mask = db->size<uint8_t>() - 1;
   if ((address & mask) != 0) {
@@ -456,9 +455,9 @@
   store_tags_->IncRef();
 }
 
-void CheriotState::LoadMemory(const Instruction *inst, uint64_t address,
-                              DataBuffer *db, Instruction *child_inst,
-                              ReferenceCount *context) {
+void CheriotState::LoadMemory(const Instruction* inst, uint64_t address,
+                              DataBuffer* db, Instruction* child_inst,
+                              ReferenceCount* context) {
   // Check for physical address violation.
   if (address < min_physical_address_ || address > max_physical_address_) {
     Trap(/*is_interrupt*/ false, address, *EC::kLoadAccessFault,
@@ -474,10 +473,10 @@
   load_tags_ = nullptr;
 }
 
-void CheriotState::LoadMemory(const Instruction *inst, DataBuffer *address_db,
-                              DataBuffer *mask_db, int el_size, DataBuffer *db,
-                              Instruction *child_inst,
-                              ReferenceCount *context) {
+void CheriotState::LoadMemory(const Instruction* inst, DataBuffer* address_db,
+                              DataBuffer* mask_db, int el_size, DataBuffer* db,
+                              Instruction* child_inst,
+                              ReferenceCount* context) {
   // For now, we don't check for alignment on vector memory accesses.
 
   // Check for physical address violation.
@@ -492,8 +491,8 @@
   tagged_memory_->Load(address_db, mask_db, el_size, db, child_inst, context);
 }
 
-void CheriotState::StoreMemory(const Instruction *inst, uint64_t address,
-                               DataBuffer *db) {
+void CheriotState::StoreMemory(const Instruction* inst, uint64_t address,
+                               DataBuffer* db) {
   // Check for physical address violation.
   if (address < min_physical_address_ || address > max_physical_address_) {
     Trap(/*is_interrupt*/ false, address, *EC::kStoreAccessFault,
@@ -515,9 +514,9 @@
   store_tags_ = nullptr;
 }
 
-void CheriotState::StoreMemory(const Instruction *inst, DataBuffer *address_db,
-                               DataBuffer *mask_db, int el_size,
-                               DataBuffer *db) {
+void CheriotState::StoreMemory(const Instruction* inst, DataBuffer* address_db,
+                               DataBuffer* mask_db, int el_size,
+                               DataBuffer* db) {
   // Ignore alignment check for vector memory accesses.
 
   // Check for physical address violation.
@@ -540,24 +539,24 @@
   tagged_memory_->Store(address_db, mask_db, el_size, db);
 }
 
-void CheriotState::DbgStoreMemory(uint64_t address, DataBuffer *db) {
+void CheriotState::DbgStoreMemory(uint64_t address, DataBuffer* db) {
   tagged_memory_->Store(address, db);
 }
 
-void CheriotState::DbgLoadMemory(uint64_t address, DataBuffer *db) {
+void CheriotState::DbgLoadMemory(uint64_t address, DataBuffer* db) {
   tagged_memory_->Load(address, db, nullptr, nullptr);
 }
 
-void CheriotState::Fence(const Instruction *inst, int fm, int predecessor,
+void CheriotState::Fence(const Instruction* inst, int fm, int predecessor,
                          int successor) {
   // TODO: Add fence operation once operations have non-zero latency.
 }
 
-void CheriotState::FenceI(const Instruction *inst) {
+void CheriotState::FenceI(const Instruction* inst) {
   // TODO: Add instruction fence operation when needed.
 }
 
-void CheriotState::ECall(const Instruction *inst) {
+void CheriotState::ECall(const Instruction* inst) {
   // If there is a handler, call it.
   if (on_ecall_ != nullptr) {
     auto res = on_ecall_(inst);
@@ -577,9 +576,9 @@
   Trap(/*is_interrupt*/ false, 0, *code, epc, inst);
 }
 
-void CheriotState::EBreak(const Instruction *inst) {
+void CheriotState::EBreak(const Instruction* inst) {
   // Call the handlers.
-  for (auto &handler : on_ebreak_) {
+  for (auto& handler : on_ebreak_) {
     bool res = handler(inst);
     // If a handler returns true, the ebreak has been handled. Just return.
     if (res) return;
@@ -590,7 +589,7 @@
   Trap(/*is_interrupt=*/false, /*trap_value=*/epc, 3, epc, inst);
 }
 
-void CheriotState::WFI(const Instruction *inst) {
+void CheriotState::WFI(const Instruction* inst) {
   // Call the handler.
   if (on_wfi_ != nullptr) {
     bool res = on_wfi_(inst);
@@ -606,7 +605,7 @@
   LOG(INFO) << "No handler for wfi: treating as nop: " << where;
 }
 
-void CheriotState::Cease(const Instruction *inst) {
+void CheriotState::Cease(const Instruction* inst) {
   // Call the handler.
   if (on_cease_ != nullptr) {
     const bool res = on_cease_(inst);
@@ -625,7 +624,7 @@
 
 void CheriotState::Trap(bool is_interrupt, uint64_t trap_value,
                         uint64_t exception_code, uint64_t epc,
-                        const Instruction *inst) {
+                        const Instruction* inst) {
   // LOG(INFO) << "Trap: " << std::hex << is_interrupt << " " << trap_value
   //  << " " << exception_code << " " << epc;  // Call the handler.
   if (on_trap_ != nullptr) {
@@ -693,7 +692,7 @@
     if (epc == trap_target) {
       std::string trap_list;
       int i = 0;
-      for (auto &info : interrupt_info_list_) {
+      for (auto& info : interrupt_info_list_) {
         absl::StrAppend(&trap_list, "    [", i++,
                         "]: ", info.is_interrupt ? "Interrupt" : "Trap",
                         " was taken", " at 0x",
@@ -791,7 +790,7 @@
 }
 
 uint64_t RiscVCheri32PcSourceOperand::GetPC() {
-  auto *pcc = state_->pcc();
+  auto* pcc = state_->pcc();
   // PCC should always be a valid capability, otherwise an exception would
   // have been taken. It should also have execute permissions. The only thing
   // to check for is that the address is within bounds.

diff --git a/cheriot/cheriot_state.h b/cheriot/cheriot_state.h
index 31df622..43704d7 100644
--- a/cheriot/cheriot_state.h
+++ b/cheriot/cheriot_state.h

@@ -99,7 +99,7 @@
 // Load context used for capability tag loads. See below for the context type
 // for capability loads.
 struct CapabilityTagsLoadContext32 : public generic::ReferenceCount {
-  CapabilityTagsLoadContext32(DataBuffer *tags, CheriotRegister *dest)
+  CapabilityTagsLoadContext32(DataBuffer* tags, CheriotRegister* dest)
       : tags(tags), dest(dest) {}
   ~CapabilityTagsLoadContext32() override {
     if (tags != nullptr) tags->DecRef();
@@ -111,14 +111,14 @@
     generic::ReferenceCount::OnRefCountIsZero();
   }
   // Data buffer for the tags. One tag bit is stored in each byte.
-  DataBuffer *tags;
+  DataBuffer* tags;
   // The destination register.
-  CheriotRegister *dest;
+  CheriotRegister* dest;
 };
 
 // Load context used for capability loads.
 struct CapabilityLoadContext32 : public generic::ReferenceCount {
-  CapabilityLoadContext32(DataBuffer *db, DataBuffer *tag_db,
+  CapabilityLoadContext32(DataBuffer* db, DataBuffer* tag_db,
                           uint32_t permissions, bool clear_tag)
       : db(db),
         tag_db(tag_db),
@@ -138,9 +138,9 @@
   }
 
   // Data buffer for the memory content.
-  DataBuffer *db;
+  DataBuffer* db;
   // Data buffer for the tags. One tag bit is stored in each byte.
-  DataBuffer *tag_db;
+  DataBuffer* tag_db;
   // The permissions of the capability used for the load.
   uint32_t permissions;
   // If true, clear the tag upon writing the result to the capability register.
@@ -152,7 +152,7 @@
 // Forward declare a template function defined in the .cc file that is
 // a friend of the state class.
 template <typename T>
-void CreateCsrs(CheriotState *, std::vector<RiscVCsrInterface *> &);
+void CreateCsrs(CheriotState*, std::vector<RiscVCsrInterface*>&);
 
 class RiscVCheri32PcSourceOperand;
 
@@ -177,10 +177,10 @@
   static constexpr char kFregPrefix[] = "f";
   static constexpr char kXregPrefix[] = "x";
   static constexpr char kCsrName[] = "csr";
-  friend void CreateCsrs<uint32_t>(CheriotState *,
-                                   std::vector<RiscVCsrInterface *> &);
-  friend void CreateCsrs<uint64_t>(CheriotState *,
-                                   std::vector<RiscVCsrInterface *> &);
+  friend void CreateCsrs<uint32_t>(CheriotState*,
+                                   std::vector<RiscVCsrInterface*>&);
+  friend void CreateCsrs<uint64_t>(CheriotState*,
+                                   std::vector<RiscVCsrInterface*>&);
   auto static constexpr kVregPrefix =
       ::mpact::sim::riscv::RiscVState::kVregPrefix;
 
@@ -189,17 +189,17 @@
   // Pc name.
   static constexpr char kPcName[] = "pcc";
   // Constructors and destructor.
-  CheriotState(std::string_view id, util::TaggedMemoryInterface *memory,
-               util::AtomicMemoryOpInterface *atomic_memory);
-  CheriotState(std::string_view id, util::TaggedMemoryInterface *memory)
+  CheriotState(std::string_view id, util::TaggedMemoryInterface* memory,
+               util::AtomicMemoryOpInterface* atomic_memory);
+  CheriotState(std::string_view id, util::TaggedMemoryInterface* memory)
       : CheriotState(id, memory, nullptr) {}
   ~CheriotState() override;
 
   // Deleted constructors and operators.
-  CheriotState(const CheriotState &) = delete;
-  CheriotState &operator=(const CheriotState &) = delete;
-  CheriotState(CheriotState &&) = delete;
-  CheriotState &operator=(CheriotState &&) = delete;
+  CheriotState(const CheriotState&) = delete;
+  CheriotState& operator=(const CheriotState&) = delete;
+  CheriotState(CheriotState&&) = delete;
+  CheriotState& operator=(CheriotState&&) = delete;
 
   // Reset all registers and CSRs to initial values.
   void Reset();
@@ -207,25 +207,24 @@
   // is true if the register had to be created, and false if it was found
   // in the register map (or if nullptr is returned).
   template <typename RegisterType>
-  std::pair<RegisterType *, bool> GetRegister(absl::string_view name) {
+  std::pair<RegisterType*, bool> GetRegister(absl::string_view name) {
     // If the register already exists, return a pointer to the register.
     auto ptr = registers()->find(std::string(name));
     if (ptr != registers()->end())
-      return std::make_pair(static_cast<RegisterType *>(ptr->second), false);
+      return std::make_pair(static_cast<RegisterType*>(ptr->second), false);
     // Create a new register and return a pointer to the object.
     return std::make_pair(AddRegister<RegisterType>(name), true);
   }
 
   // Specialization for RiscV vector registers.
   template <>
-  std::pair<RVVectorRegister *, bool> GetRegister<RVVectorRegister>(
+  std::pair<RVVectorRegister*, bool> GetRegister<RVVectorRegister>(
       absl::string_view name) {
     int vector_byte_width = vector_register_width();
     if (vector_byte_width == 0) return std::make_pair(nullptr, false);
     auto ptr = registers()->find(std::string(name));
     if (ptr != registers()->end())
-      return std::make_pair(static_cast<RVVectorRegister *>(ptr->second),
-                            false);
+      return std::make_pair(static_cast<RVVectorRegister*>(ptr->second), false);
     // Create a new register and return a pointer to the object.
     return std::make_pair(
         AddRegister<RVVectorRegister>(name, vector_byte_width), true);
@@ -245,50 +244,50 @@
   }
   // This is called by instruction semantic functions to register a CHERIoT
   // specific exception.
-  void HandleCheriRegException(const Instruction *inst, uint64_t epc,
-                               ExceptionCode code, const CheriotRegister *reg);
+  void HandleCheriRegException(const Instruction* inst, uint64_t epc,
+                               ExceptionCode code, const CheriotRegister* reg);
 
   // Methods called by instruction semantic functions to load from memory.
-  void LoadMemory(const Instruction *inst, uint64_t address, DataBuffer *db,
-                  Instruction *child_inst, ReferenceCount *context);
-  void LoadMemory(const Instruction *inst, DataBuffer *address_db,
-                  DataBuffer *mask_db, int el_size, DataBuffer *db,
-                  Instruction *child_inst, ReferenceCount *context);
+  void LoadMemory(const Instruction* inst, uint64_t address, DataBuffer* db,
+                  Instruction* child_inst, ReferenceCount* context);
+  void LoadMemory(const Instruction* inst, DataBuffer* address_db,
+                  DataBuffer* mask_db, int el_size, DataBuffer* db,
+                  Instruction* child_inst, ReferenceCount* context);
   // Methods called by instruction semantic functions to store to memory.
-  void StoreMemory(const Instruction *inst, uint64_t address, DataBuffer *db);
-  void StoreMemory(const Instruction *inst, DataBuffer *address_db,
-                   DataBuffer *mask_db, int el_size, DataBuffer *db);
+  void StoreMemory(const Instruction* inst, uint64_t address, DataBuffer* db);
+  void StoreMemory(const Instruction* inst, DataBuffer* address_db,
+                   DataBuffer* mask_db, int el_size, DataBuffer* db);
   // Methods called by instruction semantic functions to load and store
   // capabilities.
-  void LoadCapability(const Instruction *instruction, uint32_t address,
-                      DataBuffer *db, DataBuffer *tags, Instruction *child,
-                      CapabilityLoadContext32 *context);
-  void StoreCapability(const Instruction *instruction, uint32_t address,
-                       DataBuffer *db, DataBuffer *tags);
+  void LoadCapability(const Instruction* instruction, uint32_t address,
+                      DataBuffer* db, DataBuffer* tags, Instruction* child,
+                      CapabilityLoadContext32* context);
+  void StoreCapability(const Instruction* instruction, uint32_t address,
+                       DataBuffer* db, DataBuffer* tags);
 
   // Debug memory methods.
-  void DbgLoadMemory(uint64_t address, DataBuffer *db);
-  void DbgStoreMemory(uint64_t address, DataBuffer *db);
+  void DbgLoadMemory(uint64_t address, DataBuffer* db);
+  void DbgStoreMemory(uint64_t address, DataBuffer* db);
   // Called by the fence instruction semantic function to signal a fence
   // operation.
-  void Fence(const Instruction *inst, int fm, int predecessor, int successor);
+  void Fence(const Instruction* inst, int fm, int predecessor, int successor);
   // Synchronize instruction and data streams.
-  void FenceI(const Instruction *inst);
+  void FenceI(const Instruction* inst);
   // System call.
-  void ECall(const Instruction *inst);
+  void ECall(const Instruction* inst);
   // Breakpoint.
-  void EBreak(const Instruction *inst);
+  void EBreak(const Instruction* inst);
   // WFI
-  void WFI(const Instruction *inst);
+  void WFI(const Instruction* inst);
   // Ceases execution on the core. This is a non-standard instruction that
   // quiesces traffic for embedded cores before halting. The core must be reset
   // to come out of this state.
-  void Cease(const Instruction *inst);
+  void Cease(const Instruction* inst);
   // This method is called to trigger a RiscV trap.
   void Trap(bool is_interrupt, uint64_t trap_value, uint64_t exception_code,
-            uint64_t epc, const Instruction *inst);
+            uint64_t epc, const Instruction* inst);
   // Add ebreak handler.
-  void AddEbreakHandler(absl::AnyInvocable<bool(const Instruction *)> handler) {
+  void AddEbreakHandler(absl::AnyInvocable<bool(const Instruction*)> handler) {
     on_ebreak_.emplace_back(std::move(handler));
   }
   // This function is called after any event that may have caused an interrupt
@@ -312,11 +311,11 @@
   }
   // Returns the interrupt counters. This allows code to be connected to the
   // counters when the value changes.
-  SimpleCounter<int64_t> *counter_interrupts_taken() {
+  SimpleCounter<int64_t>* counter_interrupts_taken() {
     return &counter_interrupts_taken_;
   }
 
-  SimpleCounter<int64_t> *counter_interrupt_returns() {
+  SimpleCounter<int64_t>* counter_interrupt_returns() {
     return &counter_interrupt_returns_;
   }
 
@@ -337,15 +336,15 @@
   inline void reset_is_interrupt_available() {
     is_interrupt_available_ = false;
   }
-  void set_tagged_memory(util::TaggedMemoryInterface *tagged_memory) {
+  void set_tagged_memory(util::TaggedMemoryInterface* tagged_memory) {
     tagged_memory_ = tagged_memory;
   }
-  util::TaggedMemoryInterface *tagged_memory() const { return tagged_memory_; }
-  util::AtomicMemoryOpInterface *atomic_tagged_memory() const {
+  util::TaggedMemoryInterface* tagged_memory() const { return tagged_memory_; }
+  util::AtomicMemoryOpInterface* atomic_tagged_memory() const {
     return atomic_tagged_memory_;
   }
   void set_atomic_tagged_memory(
-      util::AtomicMemoryOpInterface *atomic_tagged_memory) {
+      util::AtomicMemoryOpInterface* atomic_tagged_memory) {
     atomic_tagged_memory_ = atomic_tagged_memory;
   }
 
@@ -358,13 +357,13 @@
   uint64_t min_physical_address() const { return min_physical_address_; }
   // These root capabilities are clean versions of each type of capability with
   // maximum permissions.
-  const CheriotRegister *executable_root() const { return executable_root_; }
-  const CheriotRegister *sealing_root() const { return sealing_root_; }
-  const CheriotRegister *memory_root() const { return memory_root_; }
+  const CheriotRegister* executable_root() const { return executable_root_; }
+  const CheriotRegister* sealing_root() const { return sealing_root_; }
+  const CheriotRegister* memory_root() const { return memory_root_; }
   // Special capability registers. Pcc replaces the pc. Cgp is a global pointer
   // capability that is aliased with c3.
-  CheriotRegister *pcc() const { return pcc_; }
-  CheriotRegister *cgp() const { return cgp_; }
+  CheriotRegister* pcc() const { return pcc_; }
+  CheriotRegister* cgp() const { return cgp_; }
   // True if the misa register encodes support for compact instructions.
   bool has_compact() const {
     return (misa_->AsUint64() & *IsaExtension::kCompressed) != 0;
@@ -373,48 +372,48 @@
   // instruction.
   int num_tags_per_load() const { return num_tags_per_load_; }
   // Provides access to the set of CSRs of this architectural state instance.
-  RiscVCsrSet *csr_set() { return csr_set_; }
+  RiscVCsrSet* csr_set() { return csr_set_; }
   // Setters for handlers for ecall, and trap. The handler returns true
   // if the instruction/event was handled, and false otherwise.
 
-  void set_on_ecall(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_ecall(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_ecall_ = std::move(callback);
   }
 
-  void set_on_wfi(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_wfi(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_wfi_ = std::move(callback);
   }
 
-  void set_on_cease(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_cease(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_cease_ = std::move(callback);
   }
 
   void set_on_trap(
       absl::AnyInvocable<bool(bool /*is_interrupt*/, uint64_t /*trap_value*/,
                               uint64_t /*exception_code*/, uint64_t /*epc*/,
-                              const Instruction *)>
+                              const Instruction*)>
           callback) {
     on_trap_ = std::move(callback);
   }
 
-  RiscVFPState *rv_fp() { return rv_fp_; }
-  void set_rv_fp(RiscVFPState *rv_fp) { rv_fp_ = rv_fp; }
-  CheriotVectorState *rv_vector() { return rv_vector_; }
-  void set_rv_vector(CheriotVectorState *rv_vector) { rv_vector_ = rv_vector; }
+  RiscVFPState* rv_fp() { return rv_fp_; }
+  void set_rv_fp(RiscVFPState* rv_fp) { rv_fp_ = rv_fp; }
+  CheriotVectorState* rv_vector() { return rv_vector_; }
+  void set_rv_vector(CheriotVectorState* rv_vector) { rv_vector_ = rv_vector; }
   void set_vector_register_width(int value) { vector_register_width_ = value; }
   int vector_register_width() const { return vector_register_width_; }
-  RiscVMStatus *mstatus() { return mstatus_; }
-  RiscVMIsa *misa() { return misa_; }
-  RiscVMIp *mip() { return mip_; }
-  RiscVMIe *mie() { return mie_; }
-  CheriotRegister *mtcc() { return mtcc_; }
-  CheriotRegister *mepcc() { return mepcc_; }
-  CheriotRegister *mscratchc() { return mscratchc_; }
-  CheriotRegister *mtdc() { return mtdc_; }
-  CheriotRegister *temp_reg() { return temp_reg_; }
-  RiscVCsrInterface *mcause() { return mcause_; }
-  RiscVCheri32PcSourceOperand *pc_src_operand() { return pc_src_operand_; }
-  const InterruptInfoList &interrupt_info_list() const {
+  RiscVMStatus* mstatus() { return mstatus_; }
+  RiscVMIsa* misa() { return misa_; }
+  RiscVMIp* mip() { return mip_; }
+  RiscVMIe* mie() { return mie_; }
+  CheriotRegister* mtcc() { return mtcc_; }
+  CheriotRegister* mepcc() { return mepcc_; }
+  CheriotRegister* mscratchc() { return mscratchc_; }
+  CheriotRegister* mtdc() { return mtdc_; }
+  CheriotRegister* temp_reg() { return temp_reg_; }
+  RiscVCsrInterface* mcause() { return mcause_; }
+  RiscVCheri32PcSourceOperand* pc_src_operand() { return pc_src_operand_; }
+  const InterruptInfoList& interrupt_info_list() const {
     return interrupt_info_list_;
   }
   uint64_t revocation_mem_base() const { return revocation_mem_base_; }
@@ -424,15 +423,15 @@
   bool tracing_active() const { return tracing_active_; }
   void set_tracing_active(bool active) { tracing_active_ = active; }
   uint64_t load_address() const { return load_address_; }
-  DataBuffer *load_db() const { return load_db_; }
-  void set_load_db(DataBuffer *db) { load_db_ = db; }
-  DataBuffer *load_tags() const { return load_tags_; }
-  void set_load_tags(DataBuffer *tags) { load_tags_ = tags; }
+  DataBuffer* load_db() const { return load_db_; }
+  void set_load_db(DataBuffer* db) { load_db_ = db; }
+  DataBuffer* load_tags() const { return load_tags_; }
+  void set_load_tags(DataBuffer* tags) { load_tags_ = tags; }
   uint64_t store_address() const { return store_address_; }
-  DataBuffer *store_db() const { return store_db_; }
-  void set_store_db(DataBuffer *db) { store_db_ = db; }
-  DataBuffer *store_tags() const { return store_tags_; }
-  void set_store_tags(DataBuffer *tags) { store_tags_ = tags; }
+  DataBuffer* store_db() const { return store_db_; }
+  void set_store_db(DataBuffer* db) { store_db_ = db; }
+  DataBuffer* store_tags() const { return store_tags_; }
+  void set_store_tags(DataBuffer* tags) { store_tags_ = tags; }
 
  private:
   InterruptCode PickInterrupt(uint32_t interrupts);
@@ -442,30 +441,30 @@
   // A map from register name to entry in the mtval register.
   absl::flat_hash_map<std::string, uint32_t> cap_index_map_;
   // These are root capabilities
-  CheriotRegister *executable_root_ = nullptr;
-  CheriotRegister *sealing_root_ = nullptr;
-  CheriotRegister *memory_root_ = nullptr;
+  CheriotRegister* executable_root_ = nullptr;
+  CheriotRegister* sealing_root_ = nullptr;
+  CheriotRegister* memory_root_ = nullptr;
   // Special capability registers.
-  CheriotRegister *pcc_ = nullptr;
-  CheriotRegister *cgp_ = nullptr;
+  CheriotRegister* pcc_ = nullptr;
+  CheriotRegister* cgp_ = nullptr;
   bool branch_ = false;
   int vector_register_width_ = 0;
   uint64_t max_physical_address_;
   uint64_t min_physical_address_ = 0;
   int num_tags_per_load_;
-  util::TaggedMemoryInterface *tagged_memory_;
-  util::AtomicMemoryOpInterface *atomic_tagged_memory_;
-  RiscVCsrSet *csr_set_;
-  std::vector<absl::AnyInvocable<bool(const Instruction *)>> on_ebreak_;
-  absl::AnyInvocable<bool(const Instruction *)> on_ecall_;
+  util::TaggedMemoryInterface* tagged_memory_;
+  util::AtomicMemoryOpInterface* atomic_tagged_memory_;
+  RiscVCsrSet* csr_set_;
+  std::vector<absl::AnyInvocable<bool(const Instruction*)>> on_ebreak_;
+  absl::AnyInvocable<bool(const Instruction*)> on_ecall_;
   absl::AnyInvocable<bool(bool, uint64_t, uint64_t, uint64_t,
-                          const Instruction *)>
+                          const Instruction*)>
       on_trap_;
-  absl::AnyInvocable<bool(const Instruction *)> on_wfi_;
-  absl::AnyInvocable<bool(const Instruction *)> on_cease_;
-  std::vector<RiscVCsrInterface *> csr_vec_;
-  RiscVFPState *rv_fp_ = nullptr;
-  CheriotVectorState *rv_vector_ = nullptr;
+  absl::AnyInvocable<bool(const Instruction*)> on_wfi_;
+  absl::AnyInvocable<bool(const Instruction*)> on_cease_;
+  std::vector<RiscVCsrInterface*> csr_vec_;
+  RiscVFPState* rv_fp_ = nullptr;
+  CheriotVectorState* rv_vector_ = nullptr;
   // For interrupt handling.
   bool is_interrupt_available_ = false;
   SimpleCounter<int64_t> counter_interrupts_taken_;
@@ -475,44 +474,44 @@
   // By default, execute in machine mode.
   PrivilegeMode privilege_mode_ = PrivilegeMode::kMachine;
   // Handles to frequently used CSRs.
-  RiscVMStatus *mstatus_ = nullptr;
-  RiscVMIsa *misa_ = nullptr;
-  RiscVMIp *mip_ = nullptr;
-  RiscVMIe *mie_ = nullptr;
-  RiscVSimpleCsr<uint32_t> *mshwm_ = nullptr;
-  RiscVSimpleCsr<uint32_t> *mshwmb_ = nullptr;
-  CheriotRegister *mtcc_ = nullptr;
-  CheriotRegister *mepcc_ = nullptr;
-  CheriotRegister *mscratchc_ = nullptr;
-  CheriotRegister *mtdc_ = nullptr;
-  CheriotRegister *temp_reg_ = nullptr;
-  RiscVPmp *pmp_ = nullptr;
-  RiscVCsrInterface *mtval_ = nullptr;
-  RiscVCsrInterface *mcause_ = nullptr;
-  RiscVCheri32PcSourceOperand *pc_src_operand_ = nullptr;
+  RiscVMStatus* mstatus_ = nullptr;
+  RiscVMIsa* misa_ = nullptr;
+  RiscVMIp* mip_ = nullptr;
+  RiscVMIe* mie_ = nullptr;
+  RiscVSimpleCsr<uint32_t>* mshwm_ = nullptr;
+  RiscVSimpleCsr<uint32_t>* mshwmb_ = nullptr;
+  CheriotRegister* mtcc_ = nullptr;
+  CheriotRegister* mepcc_ = nullptr;
+  CheriotRegister* mscratchc_ = nullptr;
+  CheriotRegister* mtdc_ = nullptr;
+  CheriotRegister* temp_reg_ = nullptr;
+  RiscVPmp* pmp_ = nullptr;
+  RiscVCsrInterface* mtval_ = nullptr;
+  RiscVCsrInterface* mcause_ = nullptr;
+  RiscVCheri32PcSourceOperand* pc_src_operand_ = nullptr;
   // DataBuffer and info used to check for revocation.
-  DataBuffer *revocation_db_ = nullptr;
+  DataBuffer* revocation_db_ = nullptr;
   uint64_t revocation_mem_base_;
   uint64_t revocation_ram_base_;
   // Active tracing flag.
   bool tracing_active_ = false;
   // Members for collecting trace data.
   uint64_t load_address_;
-  DataBuffer *load_db_ = nullptr;
-  DataBuffer *load_tags_ = nullptr;
+  DataBuffer* load_db_ = nullptr;
+  DataBuffer* load_tags_ = nullptr;
   uint64_t store_address_;
-  DataBuffer *store_db_ = nullptr;
-  DataBuffer *store_tags_ = nullptr;
+  DataBuffer* store_db_ = nullptr;
+  DataBuffer* store_tags_ = nullptr;
 };
 
 // This class implements the source operand interface on top of a capability
 // register so that its value (contained address) can be read as an operand.
 class RiscVCheri32PcSourceOperand : public generic::SourceOperandInterface {
  public:
-  explicit RiscVCheri32PcSourceOperand(CheriotState *state) : state_(state) {}
+  explicit RiscVCheri32PcSourceOperand(CheriotState* state) : state_(state) {}
   RiscVCheri32PcSourceOperand() = delete;
-  RiscVCheri32PcSourceOperand(const RiscVCheri32PcSourceOperand &) = delete;
-  RiscVCheri32PcSourceOperand &operator=(const RiscVCheri32PcSourceOperand &) =
+  RiscVCheri32PcSourceOperand(const RiscVCheri32PcSourceOperand&) = delete;
+  RiscVCheri32PcSourceOperand& operator=(const RiscVCheri32PcSourceOperand&) =
       delete;
   ~RiscVCheri32PcSourceOperand() override = default;
   // Methods for accessing the nth value element.
@@ -544,7 +543,7 @@
 
  private:
   uint64_t GetPC();
-  CheriotState *state_;
+  CheriotState* state_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_test_rig.cc b/cheriot/cheriot_test_rig.cc
index 91e17ec..9cc2a5a 100644
--- a/cheriot/cheriot_test_rig.cc
+++ b/cheriot/cheriot_test_rig.cc

@@ -16,7 +16,6 @@
 
 #include <cstdint>
 #include <cstring>
-#include <new>
 #include <string>
 
 #include "absl/functional/bind_front.h"
@@ -64,7 +63,7 @@
   // Set up sim state.
   state_ = new CheriotState(kCheriotTestRigName, tagged_memory_watcher_);
   // Initialize pcc to 0x8000'0000.
-  pcc_ = static_cast<CheriotRegister *>(
+  pcc_ = static_cast<CheriotRegister*>(
       state_->registers()->at(CheriotState::kPcName));
   pcc_->set_address(0x8000'0000);
   cheriot_decoder_ = new CheriotTestRigDecoder(state_);
@@ -110,10 +109,10 @@
   auto minstreth_res = state_->csr_set()->GetCsr("minstreth");
   CHECK_OK(minstret_res.status());
   CHECK_OK(minstreth_res.status());
-  auto *minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
+  auto* minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(
       minstret_res.value());
-  auto *minstreth =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(minstreth_res.value());
+  auto* minstreth =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(minstreth_res.value());
   minstret->set_counter(&counter_num_instructions_);
   minstreth->set_counter(&counter_num_instructions_);
 
@@ -123,10 +122,10 @@
   auto mcycleh_res = state_->csr_set()->GetCsr("mcycleh");
   CHECK_OK(mcycle_res.status());
   CHECK_OK(mcycleh_res.status());
-  auto *mcycle = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
-      mcycle_res.value());
-  auto *mcycleh =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(mcycleh_res.value());
+  auto* mcycle =
+      static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(mcycle_res.value());
+  auto* mcycleh =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(mcycleh_res.value());
   mcycle->set_counter(&counter_num_instructions_);
   mcycleh->set_counter(&counter_num_instructions_);
   // Set memory limits according to the memory space for TestRIG.
@@ -148,7 +147,7 @@
 }
 
 absl::Status CheriotTestRig::Execute(
-    const test_rig::InstructionPacket &inst_packet, int fd) {
+    const test_rig::InstructionPacket& inst_packet, int fd) {
   switch (trace_version_) {
     case 1:
       return ExecuteV1(inst_packet, fd);
@@ -171,7 +170,7 @@
 }
 
 absl::Status CheriotTestRig::ExecuteV1(
-    const test_rig::InstructionPacket &inst_packet, int fd) {
+    const test_rig::InstructionPacket& inst_packet, int fd) {
   test_rig::ExecutionPacket ep;
   uint32_t inst_word = inst_packet.rvfi_insn;
   ep.rvfi_halt = 0;
@@ -188,7 +187,7 @@
   ep.rvfi_pc_rdata = pc;
   // Decode fills in rd_addr, rs2_addr, rs1_addr.
   CheriotTestRigDecoder::DecodeInfo decode_info;
-  auto *inst = cheriot_decoder_->DecodeInstruction(pc, inst_word, decode_info);
+  auto* inst = cheriot_decoder_->DecodeInstruction(pc, inst_word, decode_info);
   ep.rvfi_rd_addr = decode_info.rd;
   ep.rvfi_rs1_addr = decode_info.rs1;
   ep.rvfi_rs2_addr = decode_info.rs2;
@@ -261,12 +260,12 @@
 }
 
 absl::Status CheriotTestRig::ExecuteV2(
-    const test_rig::InstructionPacket &inst_packet, int fd) {
+    const test_rig::InstructionPacket& inst_packet, int fd) {
   test_rig::ExecutionPacketExtInteger ep_ext_integer;
   test_rig::ExecutionPacketExtMemAccess ep_ext_mem_access;
   test_rig::ExecutionPacketV2 ep_v2;
-  test_rig::ExecutionPacketMetaData &ep_metadata = ep_v2.basic_data;
-  test_rig::ExecutionPacketPC &ep_pc = ep_v2.pc_data;
+  test_rig::ExecutionPacketMetaData& ep_metadata = ep_v2.basic_data;
+  test_rig::ExecutionPacketPC& ep_pc = ep_v2.pc_data;
 
   uint32_t inst_word = inst_packet.rvfi_insn;
   ep_metadata.rvfi_halt = 0;
@@ -283,7 +282,7 @@
   ep_pc.rvfi_pc_rdata = pc;
   // Decode fills in rd_addr, rs2_addr, rs1_addr.
   CheriotTestRigDecoder::DecodeInfo decode_info;
-  auto *inst = cheriot_decoder_->DecodeInstruction(pc, inst_word, decode_info);
+  auto* inst = cheriot_decoder_->DecodeInstruction(pc, inst_word, decode_info);
   ep_ext_integer.rvfi_rd_addr = decode_info.rd;
   ep_ext_integer.rvfi_rs1_addr = decode_info.rs1;
   ep_ext_integer.rvfi_rs2_addr = decode_info.rs2;
@@ -418,12 +417,12 @@
   // Reset instruction counter.
   counter_num_instructions_.SetValue(0);
   // Set all capability registers to memory root capability.
-  for (auto const &name :
+  for (auto const& name :
        {"c1",  "c2",  "c3",  "c4",  "c5",  "c6",  "c7",  "c8",
         "c9",  "c10", "c11", "c12", "c13", "c14", "c15", "c16",
         "c17", "c18", "c19", "c20", "c21", "c22", "c23", "c24",
         "c25", "c26", "c27", "c28", "c29", "c30", "c31"}) {
-    auto *cap_reg = state_->GetRegister<CheriotRegister>(name).first;
+    auto* cap_reg = state_->GetRegister<CheriotRegister>(name).first;
     cap_reg->ResetMemoryRoot();
   }
 }
@@ -475,7 +474,7 @@
 // Just capture that a trap occurred.
 bool CheriotTestRig::OnTrap(bool is_interrupt, uint64_t trap_value,
                             uint64_t exception_code, uint64_t epc,
-                            const Instruction *inst) {
+                            const Instruction* inst) {
   trap_set_ = true;
   return false;
 }
@@ -545,8 +544,8 @@
   if (ptr == state_->registers()->end()) {
     return 0;
   } else {
-    auto *reg = ptr->second;
-    auto *creg = static_cast<CheriotRegister *>(reg);
+    auto* reg = ptr->second;
+    auto* creg = static_cast<CheriotRegister*>(reg);
     return creg->address();
   }
 }

diff --git a/cheriot/cheriot_test_rig.h b/cheriot/cheriot_test_rig.h
index f8f714c..78d86c6 100644
--- a/cheriot/cheriot_test_rig.h
+++ b/cheriot/cheriot_test_rig.h

@@ -42,7 +42,7 @@
   ~CheriotTestRig() override;
   // Execute the instruction word specified in the instruction packet. Fill out
   // the fields in the execution packet accordingly.
-  absl::Status Execute(const test_rig::InstructionPacket &inst_packet, int fd);
+  absl::Status Execute(const test_rig::InstructionPacket& inst_packet, int fd);
   // Return the highest version of RVFI supported.
   int GetMaxSupportedVersion() { return 2; }
   // Set the version of RVFI to use.
@@ -53,9 +53,9 @@
 
  private:
   // Version specific instances of execute and reset.
-  absl::Status ExecuteV1(const test_rig::InstructionPacket &inst_packet,
+  absl::Status ExecuteV1(const test_rig::InstructionPacket& inst_packet,
                          int fd);
-  absl::Status ExecuteV2(const test_rig::InstructionPacket &inst_packet,
+  absl::Status ExecuteV2(const test_rig::InstructionPacket& inst_packet,
                          int fd);
   absl::Status ResetV1(uint8_t halt, int fd);
   absl::Status ResetV2(uint8_t halt, int fd);
@@ -63,7 +63,7 @@
   void ResetArch();
   // Callback when a trap is encountered.
   bool OnTrap(bool is_interrupt, uint64_t trap_value, uint64_t exception_code,
-              uint64_t epc, const Instruction *inst);
+              uint64_t epc, const Instruction* inst);
   // Callback when a memory load/store encountered.
   void OnLoad(uint64_t address, int size);
   void OnStore(uint64_t address, int size);
@@ -71,11 +71,11 @@
   uint32_t GetRegister(uint32_t reg_id);
 
   int trace_version_ = 1;
-  CheriotState *state_;
-  CheriotRegister *pcc_;
-  CheriotTestRigDecoder *cheriot_decoder_ = nullptr;
-  util::TaggedMemoryInterface *tagged_memory_ = nullptr;
-  util::TaggedMemoryWatcher *tagged_memory_watcher_ = nullptr;
+  CheriotState* state_;
+  CheriotRegister* pcc_;
+  CheriotTestRigDecoder* cheriot_decoder_ = nullptr;
+  util::TaggedMemoryInterface* tagged_memory_ = nullptr;
+  util::TaggedMemoryWatcher* tagged_memory_watcher_ = nullptr;
   // Instruction counter.
   generic::SimpleCounter<uint64_t> counter_num_instructions_;
   // Fields for capturing information during execution of an instruction that
@@ -88,10 +88,10 @@
   uint64_t mem_w_data_[4];
   // Handling data buffers for ld/st.
   generic::DataBufferFactory db_factory_;
-  generic::DataBuffer *db1_ = nullptr;
-  generic::DataBuffer *db2_ = nullptr;
-  generic::DataBuffer *db4_ = nullptr;
-  generic::DataBuffer *db8_ = nullptr;
+  generic::DataBuffer* db1_ = nullptr;
+  generic::DataBuffer* db2_ = nullptr;
+  generic::DataBuffer* db4_ = nullptr;
+  generic::DataBuffer* db8_ = nullptr;
 };
 
 }  // namespace mpact::sim::cheriot

diff --git a/cheriot/cheriot_test_rig_decoder.cc b/cheriot/cheriot_test_rig_decoder.cc
index 3a77023..3d375ad 100644
--- a/cheriot/cheriot_test_rig_decoder.cc
+++ b/cheriot/cheriot_test_rig_decoder.cc

@@ -35,7 +35,7 @@
 using RV_EC = ::mpact::sim::riscv::ExceptionCode;
 using ::mpact::sim::cheriot::isa32::OpcodeEnum;  // NOLINT: is used below.
 
-CheriotTestRigDecoder::CheriotTestRigDecoder(CheriotState *state)
+CheriotTestRigDecoder::CheriotTestRigDecoder(CheriotState* state)
     : state_(state) {
   // Get a handle to the internal error in the program error controller.
   decode_error_ = state->program_error_controller()->GetProgramError(
@@ -54,18 +54,18 @@
   delete cheriot_isa_factory_;
 }
 
-generic::Instruction *CheriotTestRigDecoder::DecodeInstruction(
-    uint64_t address, uint32_t inst_word, DecodeInfo &decode_info) {
+generic::Instruction* CheriotTestRigDecoder::DecodeInstruction(
+    uint64_t address, uint32_t inst_word, DecodeInfo& decode_info) {
   uint16_t inst_word16 = static_cast<uint16_t>(inst_word & 0xffff);
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *RV_EC::kInstructionAddressMisaligned, inst->address() ^ 0x1,
                    inst);
@@ -244,7 +244,7 @@
   }
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = cheriot_isa_->Decode(address, cheriot_encoding_);
+  auto* instruction = cheriot_isa_->Decode(address, cheriot_encoding_);
   // For these formats, sail does not populate the rs1/rs2 address fields.
   if (format == FormatEnum::kIType || format == FormatEnum::kI5Type ||
       format == FormatEnum::kR2Type || format == FormatEnum::kCB ||

diff --git a/cheriot/cheriot_test_rig_decoder.h b/cheriot/cheriot_test_rig_decoder.h
index 46fe4b1..8b44559 100644
--- a/cheriot/cheriot_test_rig_decoder.h
+++ b/cheriot/cheriot_test_rig_decoder.h

@@ -24,7 +24,6 @@
 #include "cheriot/riscv_cheriot_decoder.h"
 #include "cheriot/riscv_cheriot_encoding.h"
 #include "cheriot/riscv_cheriot_enums.h"
-#include "cheriot/test_rig_packets.h"
 #include "mpact/sim/generic/arch_state.h"
 #include "mpact/sim/generic/decoder_interface.h"
 #include "mpact/sim/generic/instruction.h"
@@ -44,7 +43,7 @@
     : public isa32::RiscVCheriotInstructionSetFactory {
  public:
   std::unique_ptr<isa32::Riscv32CheriotSlot> CreateRiscv32CheriotSlot(
-      generic::ArchState *state) override {
+      generic::ArchState* state) override {
     return std::make_unique<isa32::Riscv32CheriotSlot>(state);
   }
 };
@@ -60,23 +59,23 @@
     int rs2;
   };
 
-  explicit CheriotTestRigDecoder(CheriotState *state);
+  explicit CheriotTestRigDecoder(CheriotState* state);
   CheriotTestRigDecoder() = delete;
-  CheriotTestRigDecoder(const CheriotTestRigDecoder &) = delete;
-  CheriotTestRigDecoder &operator=(const CheriotTestRigDecoder &) = delete;
+  CheriotTestRigDecoder(const CheriotTestRigDecoder&) = delete;
+  CheriotTestRigDecoder& operator=(const CheriotTestRigDecoder&) = delete;
   virtual ~CheriotTestRigDecoder();
 
   // Decode a single instruction and fill in decode time information in the
   // TestRIG execution packet.
-  generic::Instruction *DecodeInstruction(uint64_t address, uint32_t inst_word,
-                                          DecodeInfo &decode_info);
+  generic::Instruction* DecodeInstruction(uint64_t address, uint32_t inst_word,
+                                          DecodeInfo& decode_info);
 
  private:
-  CheriotState *state_;
+  CheriotState* state_;
   std::unique_ptr<generic::ProgramError> decode_error_;
-  isa32::RiscVCheriotEncoding *cheriot_encoding_;
-  isa32::RiscVCheriotInstructionSetFactory *cheriot_isa_factory_;
-  isa32::RiscVCheriotInstructionSet *cheriot_isa_;
+  isa32::RiscVCheriotEncoding* cheriot_encoding_;
+  isa32::RiscVCheriotInstructionSetFactory* cheriot_isa_factory_;
+  isa32::RiscVCheriotInstructionSet* cheriot_isa_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_test_rig_main.cc b/cheriot/cheriot_test_rig_main.cc
index cf7fcae..c164c69 100644
--- a/cheriot/cheriot_test_rig_main.cc
+++ b/cheriot/cheriot_test_rig_main.cc

@@ -18,7 +18,6 @@
 
 #include <cerrno>
 #include <cstdint>
-#include <cstring>
 #include <memory>
 
 #include "absl/flags/flag.h"
@@ -36,7 +35,7 @@
 
 ABSL_FLAG(int, trace_port, 0, "Trace port number");
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   absl::SetProgramUsageMessage(argv[0]);
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
@@ -74,7 +73,7 @@
   const sockaddr_in trace_address_in = {
       AF_INET, htons(absl::GetFlag(FLAGS_trace_port)), {INADDR_ANY}};
   int res =
-      bind(trace_socket, reinterpret_cast<const sockaddr *>(&trace_address_in),
+      bind(trace_socket, reinterpret_cast<const sockaddr*>(&trace_address_in),
            sizeof(trace_address_in));
   if (res != 0) {
     LOG(ERROR) << "Error connecting to trace_socket (" << res << ")\n";

diff --git a/cheriot/cheriot_top.cc b/cheriot/cheriot_top.cc
index 798ccfe..f549ec8 100644
--- a/cheriot/cheriot_top.cc
+++ b/cheriot/cheriot_top.cc

@@ -65,8 +65,8 @@
 using EC = ::mpact::sim::cheriot::ExceptionCode;
 using PB = ::mpact::sim::cheriot::CheriotRegister::PermissionBits;
 
-CheriotTop::CheriotTop(std::string name, CheriotState *state,
-                       DecoderInterface *decoder)
+CheriotTop::CheriotTop(std::string name, CheriotState* state,
+                       DecoderInterface* decoder)
     : Component(name),
       state_(state),
       cheriot_decoder_(decoder),
@@ -114,13 +114,13 @@
 
 void CheriotTop::Initialize() {
   // Create the watchers.
-  auto *memory = static_cast<util::MemoryInterface *>(state_->tagged_memory());
+  auto* memory = static_cast<util::MemoryInterface*>(state_->tagged_memory());
   tagged_watcher_ = new util::TaggedMemoryWatcher(state_->tagged_memory());
   memory_watcher_ = new util::MemoryWatcher(memory);
   atomic_memory_ = new util::AtomicMemory(memory_watcher_);
   state_->set_tagged_memory(tagged_watcher_);
   state_->set_atomic_tagged_memory(atomic_memory_);
-  pcc_ = static_cast<CheriotRegister *>(
+  pcc_ = static_cast<CheriotRegister*>(
       state_->registers()->at(CheriotState::kPcName));
   // Register opcode counters.
   int num_opcodes = cheriot_decoder_->GetNumOpcodes();
@@ -150,7 +150,7 @@
     RequestHalt(HaltReason::kSoftwareBreakpoint, nullptr);
   });
   // Set the software action callback.
-  state_->AddEbreakHandler([this](const Instruction *inst) {
+  state_->AddEbreakHandler([this](const Instruction* inst) {
     if (rv_ap_manager_->IsActionPointActive(inst->address())) {
       // Need to request a halt so that the action point can be stepped past
       // after executing the actions. However, an action may override the
@@ -185,13 +185,13 @@
   // Branch trace.
   branch_trace_db_ = db_factory_.Allocate<BranchTraceEntry>(kBranchTraceSize);
   branch_trace_ =
-      reinterpret_cast<BranchTraceEntry *>(branch_trace_db_->raw_ptr());
+      reinterpret_cast<BranchTraceEntry*>(branch_trace_db_->raw_ptr());
   for (int i = 0; i < kBranchTraceSize; i++) {
     branch_trace_[i] = {0, 0, 0};
   }
 }
 
-void CheriotTop::ConfigureCache(Cache *&cache, Config<std::string> &config) {
+void CheriotTop::ConfigureCache(Cache*& cache, Config<std::string>& config) {
   if (cache != nullptr) {
     LOG(WARNING) << "Cache already configured - ignored";
     return;
@@ -207,7 +207,7 @@
   }
 }
 
-bool CheriotTop::ExecuteInstruction(Instruction *inst) {
+bool CheriotTop::ExecuteInstruction(Instruction* inst) {
   // Check that pcc has tag set.
   if (!pcc_->tag()) {
     state_->HandleCheriRegException(inst, inst->address(),
@@ -334,7 +334,7 @@
   uint64_t pc = next_pc;
   while (!halted_ && (count < num)) {
     SetPc(pc);
-    auto *inst = cheriot_decode_cache_->GetDecodedInstruction(pc);
+    auto* inst = cheriot_decode_cache_->GetDecodedInstruction(pc);
     // Set the next_pc to the next sequential instruction.
     next_pc = pc + inst->size();
     bool executed = false;
@@ -435,7 +435,7 @@
     // the most recently executed instruction.
     uint64_t pc = next_pc;
     while (!halted_) {
-      auto *inst = cheriot_decode_cache_->GetDecodedInstruction(pc);
+      auto* inst = cheriot_decode_cache_->GetDecodedInstruction(pc);
       SetPc(pc);
       next_pc = pc + inst->size();
       bool executed = false;
@@ -532,7 +532,7 @@
   return halt_reason_;
 }
 
-absl::StatusOr<uint64_t> CheriotTop::ReadRegister(const std::string &name) {
+absl::StatusOr<uint64_t> CheriotTop::ReadRegister(const std::string& name) {
   auto iter = state_->registers()->find(name);
   // If the register was not found, see if it refers to a capability component.
   // Capability components are named c<n>.top, c<n>.base, etc.
@@ -545,7 +545,7 @@
         return absl::NotFoundError(
             absl::StrCat("Register '", name, "' not found"));
       }
-      auto *cap_reg = static_cast<CheriotRegister *>(iter->second);
+      auto* cap_reg = static_cast<CheriotRegister*>(iter->second);
       if (component == "top") return cap_reg->top();
       if (component == "base") return cap_reg->base();
       if (component == "length") return cap_reg->length();
@@ -561,7 +561,7 @@
   if (iter == state_->registers()->end()) {
     auto result = state_->csr_set()->GetCsr(name);
     if (result.ok()) {
-      auto *csr = *result;
+      auto* csr = *result;
       return csr->GetUint32();
     }
     // See if it is $branch_trace_head.
@@ -573,7 +573,7 @@
     }
   }
 
-  auto *db = (iter->second)->data_buffer();
+  auto* db = (iter->second)->data_buffer();
   uint64_t value;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -594,7 +594,7 @@
   return value;
 }
 
-absl::Status CheriotTop::WriteRegister(const std::string &name,
+absl::Status CheriotTop::WriteRegister(const std::string& name,
                                        uint64_t value) {
   // The registers aren't protected by a mutex, so let's not write them while
   // the simulator is running.
@@ -608,7 +608,7 @@
     std::string component;
     std::string cap_reg_name;
     if (RE2::FullMatch(name, *cap_reg_re_, &cap_reg_name, &component)) {
-      auto *cap_reg = static_cast<CheriotRegister *>(iter->second);
+      auto* cap_reg = static_cast<CheriotRegister*>(iter->second);
       if (component == "top") {
         value = std::min<uint64_t>(value, 0x1'0000'0000ULL);
         if (value < cap_reg->base()) {
@@ -660,7 +660,7 @@
       return absl::NotFoundError(
           absl::StrCat("Register '", name, "' not found"));
     }
-    auto *csr = *result;
+    auto* csr = *result;
     csr->Set(static_cast<uint32_t>(value));
   }
 
@@ -671,7 +671,7 @@
     halt_reason_ = *HaltReason::kNone;
   }
 
-  auto *db = (iter->second)->data_buffer();
+  auto* db = (iter->second)->data_buffer();
   switch (db->size<uint8_t>()) {
     case 1:
       db->Set<uint8_t>(0, static_cast<uint8_t>(value));
@@ -691,8 +691,8 @@
   return absl::OkStatus();
 }
 
-absl::StatusOr<DataBuffer *> CheriotTop::GetRegisterDataBuffer(
-    const std::string &name) {
+absl::StatusOr<DataBuffer*> CheriotTop::GetRegisterDataBuffer(
+    const std::string& name) {
   // The registers aren't protected by a mutex, so let's not access them while
   // the simulator is running.
   if (run_status_ != RunStatus::kHalted) {
@@ -707,7 +707,7 @@
   return iter->second->data_buffer();
 }
 
-absl::StatusOr<size_t> CheriotTop::ReadMemory(uint64_t address, void *buffer,
+absl::StatusOr<size_t> CheriotTop::ReadMemory(uint64_t address, void* buffer,
                                               size_t length) {
   if (run_status_ != RunStatus::kHalted) {
     return absl::FailedPreconditionError("ReadMemory: Core must be halted");
@@ -716,7 +716,7 @@
     return absl::InvalidArgumentError("Invalid memory address");
   }
   length = std::min(length, state_->max_physical_address() - address + 1);
-  auto *db = db_factory_.Allocate(length);
+  auto* db = db_factory_.Allocate(length);
   // Load bypassing any watch points/semihosting.
   state_->tagged_memory()->Load(address, db, nullptr, nullptr);
   std::memcpy(buffer, db->raw_ptr(), length);
@@ -724,7 +724,7 @@
   return length;
 }
 
-absl::StatusOr<size_t> CheriotTop::ReadTagMemory(uint64_t address, void *buf,
+absl::StatusOr<size_t> CheriotTop::ReadTagMemory(uint64_t address, void* buf,
                                                  size_t length) {
   if (run_status_ != RunStatus::kHalted) {
     return absl::FailedPreconditionError("ReadTagMemory: Core must be halted");
@@ -734,7 +734,7 @@
   }
   uint64_t length64 = static_cast<uint64_t>(length);
   length = std::min(length64, state_->max_physical_address() - address + 1);
-  auto *tag_db = db_factory_.Allocate<uint8_t>(length);
+  auto* tag_db = db_factory_.Allocate<uint8_t>(length);
   state_->tagged_memory()->Load(address, nullptr, tag_db, nullptr, nullptr);
   std::memcpy(buf, tag_db->raw_ptr(), length);
   tag_db->DecRef();
@@ -742,7 +742,7 @@
 }
 
 absl::StatusOr<size_t> CheriotTop::WriteMemory(uint64_t address,
-                                               const void *buffer,
+                                               const void* buffer,
                                                size_t length) {
   if (run_status_ != RunStatus::kHalted) {
     return absl::FailedPreconditionError("WriteMemory: Core must be halted");
@@ -752,7 +752,7 @@
   }
   uint64_t length64 = static_cast<uint64_t>(length);
   length = std::min(length64, state_->max_physical_address() - address + 1);
-  auto *db = db_factory_.Allocate(length);
+  auto* db = db_factory_.Allocate(length);
   std::memcpy(db->raw_ptr(), buffer, length);
   // Store bypassing any watch points/semihosting.
   state_->tagged_memory()->Store(address, db);
@@ -926,7 +926,7 @@
   break_on_control_flow_change_ = value;
 }
 
-absl::StatusOr<Instruction *> CheriotTop::GetInstruction(uint64_t address) {
+absl::StatusOr<Instruction*> CheriotTop::GetInstruction(uint64_t address) {
   // If requesting the instruction at an action point, we need to write the
   // original instruction back to memory before getting the disassembly.
   bool inst_swap = rv_ap_manager_->IsActionPointActive(address);
@@ -935,7 +935,7 @@
         address);
   }
   // Get the decoded instruction.
-  Instruction *inst = cheriot_decode_cache_->GetDecodedInstruction(address);
+  Instruction* inst = cheriot_decode_cache_->GetDecodedInstruction(address);
   inst->IncRef();
   // Swap back if required.
   if (inst_swap) {
@@ -953,14 +953,14 @@
 
   auto res = GetInstruction(address);
   if (!res.ok()) return res.status();
-  Instruction *inst = res.value();
+  Instruction* inst = res.value();
   auto disasm = inst != nullptr ? inst->AsString() : "Invalid instruction";
   inst->DecRef();
   return disasm;
 }
 
 void CheriotTop::RequestHalt(HaltReasonValueType halt_reason,
-                             const Instruction *inst) {
+                             const Instruction* inst) {
   // First set the halt_reason_, then the halt flag.
   halt_reason_ = halt_reason;
   halted_ = true;
@@ -972,7 +972,7 @@
   }
 }
 
-void CheriotTop::RequestHalt(HaltReason halt_reason, const Instruction *inst) {
+void CheriotTop::RequestHalt(HaltReason halt_reason, const Instruction* inst) {
   RequestHalt(*halt_reason, inst);
 }
 
@@ -988,8 +988,8 @@
   if (absl::popcount(size) != 1) {
     return absl::InvalidArgumentError("Invalid size - must be a power of 2");
   }
-  auto *new_db = db_factory_.Allocate<BranchTraceEntry>(size);
-  auto *new_trace = reinterpret_cast<BranchTraceEntry *>(new_db->raw_ptr());
+  auto* new_db = db_factory_.Allocate<BranchTraceEntry>(size);
+  auto* new_trace = reinterpret_cast<BranchTraceEntry*>(new_db->raw_ptr());
   if (new_db == nullptr) {
     return absl::InternalError("Failed to allocate new branch trace buffer");
   }
@@ -1024,7 +1024,7 @@
 
 void CheriotTop::AddToBranchTrace(uint64_t from, uint64_t to) {
   // Get the most recent entry.
-  auto &entry = branch_trace_[branch_trace_head_];
+  auto& entry = branch_trace_[branch_trace_head_];
   // If the branch is the same as the previous, just increment its count.
   if ((from == entry.from) && (to == entry.to)) {
     entry.count++;
@@ -1036,14 +1036,14 @@
 }
 
 void CheriotTop::EnableStatistics() {
-  for (auto &[unused, counter_ptr] : counter_map()) {
+  for (auto& [unused, counter_ptr] : counter_map()) {
     if (counter_ptr->GetName() == "pc") continue;
     counter_ptr->SetIsEnabled(true);
   }
 }
 
 void CheriotTop::DisableStatistics() {
-  for (auto &[unused, counter_ptr] : counter_map()) {
+  for (auto& [unused, counter_ptr] : counter_map()) {
     if (counter_ptr->GetName() == "pc") continue;
     counter_ptr->SetIsEnabled(false);
   }

diff --git a/cheriot/cheriot_top.h b/cheriot/cheriot_top.h
index ea3ed27..c9afe50 100644
--- a/cheriot/cheriot_top.h
+++ b/cheriot/cheriot_top.h

@@ -72,7 +72,7 @@
   using RunStatus = generic::CoreDebugInterface::RunStatus;
   using HaltReason = generic::CoreDebugInterface::HaltReason;
 
-  CheriotTop(std::string name, CheriotState *state, DecoderInterface *decoder);
+  CheriotTop(std::string name, CheriotState* state, DecoderInterface* decoder);
   ~CheriotTop() override;
 
   // Methods inherited from CoreDebugInterface.
@@ -87,16 +87,16 @@
   absl::StatusOr<HaltReasonValueType> GetLastHaltReason() override;
 
   // Register access by register name.
-  absl::StatusOr<uint64_t> ReadRegister(const std::string &name) override;
-  absl::Status WriteRegister(const std::string &name, uint64_t value) override;
-  absl::StatusOr<generic::DataBuffer *> GetRegisterDataBuffer(
-      const std::string &name) override;
+  absl::StatusOr<uint64_t> ReadRegister(const std::string& name) override;
+  absl::Status WriteRegister(const std::string& name, uint64_t value) override;
+  absl::StatusOr<generic::DataBuffer*> GetRegisterDataBuffer(
+      const std::string& name) override;
   // Read and Write memory methods bypass any semihosting.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
-  absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadTagMemory(uint64_t address, void* buf,
                                        size_t length) override;
 
   // Breakpoints.
@@ -125,12 +125,12 @@
   // If successful, returns a pointer to the instruction at the given address.
   // The instruction object is IncRef'ed, and the caller must DecRef the object
   // when it is done with it.
-  absl::StatusOr<Instruction *> GetInstruction(uint64_t address) override;
+  absl::StatusOr<Instruction*> GetInstruction(uint64_t address) override;
   absl::StatusOr<std::string> GetDisassembly(uint64_t address) override;
 
   // Called when a halt is requested.
-  void RequestHalt(HaltReason halt_reason, const Instruction *inst);
-  void RequestHalt(HaltReasonValueType halt_reason, const Instruction *inst);
+  void RequestHalt(HaltReason halt_reason, const Instruction* inst);
+  void RequestHalt(HaltReasonValueType halt_reason, const Instruction* inst);
 
   // Resize branch trace.
   absl::Status ResizeBranchTrace(size_t size);
@@ -140,34 +140,34 @@
   void DisableStatistics();
 
   // Accessors.
-  CheriotState *state() const { return state_; }
+  CheriotState* state() const { return state_; }
   // The following are not const as callers may need to call non-const methods
   // of the counter.
-  generic::SimpleCounter<uint64_t> *counter_num_instructions() {
+  generic::SimpleCounter<uint64_t>* counter_num_instructions() {
     return &counter_num_instructions_;
   }
-  generic::SimpleCounter<uint64_t> *counter_num_cycles() {
+  generic::SimpleCounter<uint64_t>* counter_num_cycles() {
     return &counter_num_cycles_;
   }
-  generic::SimpleCounter<uint64_t> *counter_pc() { return &counter_pc_; }
+  generic::SimpleCounter<uint64_t>* counter_pc() { return &counter_pc_; }
   // Memory watchers used for data watch points.
-  util::TaggedMemoryWatcher *tagged_watcher() { return tagged_watcher_; }
-  util::MemoryWatcher *memory_watcher() { return memory_watcher_; }
+  util::TaggedMemoryWatcher* tagged_watcher() { return tagged_watcher_; }
+  util::MemoryWatcher* memory_watcher() { return memory_watcher_; }
 
-  const std::string &halt_string() const { return halt_string_; }
+  const std::string& halt_string() const { return halt_string_; }
   void set_halt_string(std::string halt_string) { halt_string_ = halt_string; }
 
-  Cache *icache() const { return icache_; }
-  Cache *dcache() const { return dcache_; }
+  Cache* icache() const { return icache_; }
+  Cache* dcache() const { return dcache_; }
 
  private:
   // Initialize the top.
   void Initialize();
   // Configure cache helper method.
-  void ConfigureCache(Cache *&cache, Config<std::string> &config);
+  void ConfigureCache(Cache*& cache, Config<std::string>& config);
   // Execute instruction. Returns true if the instruction was executed (or
   // an exception was triggered).
-  bool ExecuteInstruction(Instruction *inst);
+  bool ExecuteInstruction(Instruction* inst);
   // Helper method to step past a breakpoint.
   absl::Status StepPastBreakpoint();
   // Set the pc value.
@@ -182,35 +182,35 @@
   HaltReasonValueType halt_reason_ = *HaltReason::kNone;
   // Halting flag. This is set to true when execution must halt.
   bool halted_ = false;
-  absl::Notification *run_halted_ = nullptr;
+  absl::Notification* run_halted_ = nullptr;
   // The local CherIoT state.
-  CheriotState *state_;
+  CheriotState* state_;
   // Flag that indicates an instruction needs to be stepped over.
   bool need_to_step_over_ = false;
   // Action point memory interface.
-  RiscVActionPointMemoryInterface *rv_ap_memory_if_ = nullptr;
+  RiscVActionPointMemoryInterface* rv_ap_memory_if_ = nullptr;
   // Action point manager.
-  ActionPointManagerBase *rv_ap_manager_ = nullptr;
+  ActionPointManagerBase* rv_ap_manager_ = nullptr;
   // Breakpoint manager.
-  BreakpointManager *rv_bp_manager_ = nullptr;
+  BreakpointManager* rv_bp_manager_ = nullptr;
   // Textual description of halt reason.
   std::string halt_string_;
   // The pc register instance.
-  CheriotRegister *pcc_;
+  CheriotRegister* pcc_;
   // RiscV32 decoder instance.
-  generic::DecoderInterface *cheriot_decoder_ = nullptr;
+  generic::DecoderInterface* cheriot_decoder_ = nullptr;
   // Decode cache, memory and memory watcher.
-  generic::DecodeCache *cheriot_decode_cache_ = nullptr;
-  util::AtomicMemoryOpInterface *atomic_memory_ = nullptr;
-  util::TaggedMemoryWatcher *tagged_watcher_ = nullptr;
-  util::MemoryWatcher *memory_watcher_ = nullptr;
+  generic::DecodeCache* cheriot_decode_cache_ = nullptr;
+  util::AtomicMemoryOpInterface* atomic_memory_ = nullptr;
+  util::TaggedMemoryWatcher* tagged_watcher_ = nullptr;
+  util::MemoryWatcher* memory_watcher_ = nullptr;
   // Branch trace info - uses a circular buffer. The size is defined by the
   // constant kBranchTraceSize in the .cc file.
-  BranchTraceEntry *branch_trace_;
+  BranchTraceEntry* branch_trace_;
   // Data buffer used to hold the branch trace info. This is used so that it
   // can be returned to the debug command shell using the GetRegisterDataBuffer
   // call.
-  DataBuffer *branch_trace_db_ = nullptr;
+  DataBuffer* branch_trace_db_ = nullptr;
   // Points to the most recently written entry in the circular buffer.
   int branch_trace_head_ = 0;
   int branch_trace_mask_ = kBranchTraceSize - 1;
@@ -232,9 +232,9 @@
   Config<std::string> icache_config_;
   Config<std::string> dcache_config_;
   // ICache & DCache.
-  Cache *dcache_ = nullptr;
-  Cache *icache_ = nullptr;
-  DataBuffer *inst_db_ = nullptr;
+  Cache* dcache_ = nullptr;
+  Cache* icache_ = nullptr;
+  DataBuffer* inst_db_ = nullptr;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/cheriot_vector_true_operand.cc b/cheriot/cheriot_vector_true_operand.cc
index 549020d..dd8d177 100644
--- a/cheriot/cheriot_vector_true_operand.cc
+++ b/cheriot/cheriot_vector_true_operand.cc

@@ -24,11 +24,11 @@
 namespace sim {
 namespace cheriot {
 
-CheriotVectorTrueOperand::CheriotVectorTrueOperand(CheriotState *state)
+CheriotVectorTrueOperand::CheriotVectorTrueOperand(CheriotState* state)
     : RV32VectorSourceOperand(
           state->GetRegister<RVVectorRegister>(kName).first) {
   // Ensure the value is all ones.
-  auto *reg = state->GetRegister<RVVectorRegister>(kName).first;
+  auto* reg = state->GetRegister<RVVectorRegister>(kName).first;
   auto data = reg->data_buffer()->Get<uint64_t>();
   for (int i = 0; i < data.size(); i++) {
     data[i] = std::numeric_limits<uint64_t>::max();

diff --git a/cheriot/cheriot_vector_true_operand.h b/cheriot/cheriot_vector_true_operand.h
index 2a880c1..afa4bbc 100644
--- a/cheriot/cheriot_vector_true_operand.h
+++ b/cheriot/cheriot_vector_true_operand.h

@@ -32,7 +32,7 @@
 
 class CheriotVectorTrueOperand : public RV32VectorSourceOperand {
  public:
-  explicit CheriotVectorTrueOperand(CheriotState *state);
+  explicit CheriotVectorTrueOperand(CheriotState* state);
 
   CheriotVectorTrueOperand() = delete;
   bool AsBool(int) final { return true; }

diff --git a/cheriot/debug_command_shell.cc b/cheriot/debug_command_shell.cc
index a76aa82..eb724f4 100644
--- a/cheriot/debug_command_shell.cc
+++ b/cheriot/debug_command_shell.cc

@@ -55,10 +55,10 @@
 using HaltReason = ::mpact::sim::generic::CoreDebugInterface::HaltReason;
 using ::mpact::sim::generic::operator*;  // NOLINT: used below (clang error).
 
-DebugCommandShell::InterruptListener::InterruptListener(CoreAccess *core_access)
+DebugCommandShell::InterruptListener::InterruptListener(CoreAccess* core_access)
     : core_access_(core_access),
-      state_(static_cast<CheriotState *>(core_access_->state)),
-      dbg_if_(static_cast<CheriotTop *>(core_access->debug_interface)),
+      state_(static_cast<CheriotState*>(core_access_->state)),
+      dbg_if_(static_cast<CheriotTop*>(core_access->debug_interface)),
       taken_listener_(
           absl::bind_front(&InterruptListener::SetTakenValue, this)),
       return_listener_(
@@ -68,7 +68,7 @@
 }
 
 void DebugCommandShell::InterruptListener::SetReturnValue(int64_t value) {
-  auto &interrupt_info_list = state_->interrupt_info_list();
+  auto& interrupt_info_list = state_->interrupt_info_list();
   if (interrupt_info_list.empty()) {
     LOG(ERROR) << "Interrupt stack is empty";
     return;
@@ -231,26 +231,26 @@
 }
 
 DebugCommandShell::~DebugCommandShell() {
-  for (auto *listener : interrupt_listeners_) {
+  for (auto* listener : interrupt_listeners_) {
     delete listener;
   }
 }
 
-void DebugCommandShell::AddCore(const CoreAccess &core_access) {
+void DebugCommandShell::AddCore(const CoreAccess& core_access) {
   core_access_.push_back(core_access);
   interrupt_listeners_.push_back(new InterruptListener(&core_access_.back()));
   core_action_point_id_.push_back(0);
   core_action_point_info_.emplace_back();
 }
 
-void DebugCommandShell::AddCores(const std::vector<CoreAccess> &core_access) {
-  for (const auto &core_access : core_access) {
+void DebugCommandShell::AddCores(const std::vector<CoreAccess>& core_access) {
+  for (const auto& core_access : core_access) {
     AddCore(core_access);
   }
 }
 
 // NOLINTBEGIN(readability/fn_size)
-void DebugCommandShell::Run(std::istream &is, std::ostream &os) {
+void DebugCommandShell::Run(std::istream& is, std::ostream& os) {
   // TODO(torerik): refactor this function.
   // Assumes the max linesize is 512.
   command_streams_.push_back(&is);
@@ -307,7 +307,7 @@
       }
     }
     if (pcc_result.ok()) {
-      auto *loader = core_access_[current_core_].loader_getter();
+      auto* loader = core_access_[current_core_].loader_getter();
       if (loader != nullptr) {
         auto fcn_result = loader->GetFunctionName(pcc_result.value());
         if (fcn_result.ok()) {
@@ -329,11 +329,11 @@
       absl::StrAppend(&prompt, "\n");
     }
     auto cheriot_state =
-        static_cast<CheriotState *>(core_access_[current_core_].state);
-    auto &info_list = cheriot_state->interrupt_info_list();
+        static_cast<CheriotState*>(core_access_[current_core_].state);
+    auto& info_list = cheriot_state->interrupt_info_list();
     // Check if there is a new interrupt, if so print the info.
     if (info_list.size() > last_info_list_size) {
-      auto const &info = *info_list.rbegin();
+      auto const& info = *info_list.rbegin();
       absl::StrAppend(&prompt, info.is_interrupt ? "interrupt " : "exception ",
                       info.is_interrupt ? GetInterruptDescription(info)
                                         : GetExceptionDescription(info));
@@ -341,7 +341,7 @@
     last_info_list_size = info_list.size();
     absl::StrAppend(&prompt, "[", current_core_, "] > ");
     while (!command_streams_.empty()) {
-      auto &current_is = *command_streams_.back();
+      auto& current_is = *command_streams_.back();
       // Ignore comments or empty lines.
       bool is_file = command_streams_.size() > 1;
       // Read a command from the input stream. If it's from a file, then ignore
@@ -385,7 +385,7 @@
 
     // First try any added custom commands.
     bool executed = false;
-    for (auto &fcn : command_functions_) {
+    for (auto& fcn : command_functions_) {
       std::string output;
       executed = fcn(line_view, core_access_[current_core_], output);
       if (executed) {
@@ -545,7 +545,7 @@
         RE2::FullMatch(line_view, *set_break_re_, &str_value) ||
         RE2::FullMatch(line_view, *set_break2_re_, &str_value)) {
       if (str_value == "$branch") {
-        auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+        auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
             core_access_[current_core_].debug_interface);
         cheriot_interface->SetBreakOnControlFlowChange(true);
         continue;
@@ -648,7 +648,7 @@
 
     // break clear-all
     if (RE2::FullMatch(line_view, *clear_all_break_re_)) {
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       cheriot_interface->SetBreakOnControlFlowChange(false);
       interrupt_listeners_[current_core_]->SetEnableExceptions(false);
@@ -668,7 +668,7 @@
     if (std::string str_value;
         RE2::FullMatch(line_view, *clear_break_re_, &str_value)) {
       if (str_value == "$branch") {
-        auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+        auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
             core_access_[current_core_].debug_interface);
         cheriot_interface->SetBreakOnControlFlowChange(false);
         continue;
@@ -718,7 +718,7 @@
         bool active =
             core_access_[current_core_].debug_interface->HasBreakpoint(address);
         std::string symbol;
-        auto *loader = core_access_[current_core_].loader_getter();
+        auto* loader = core_access_[current_core_].loader_getter();
         if (loader != nullptr) {
           auto res = loader->GetFcnSymbolName(address);
           if (res.ok()) symbol = std::move(res.value());
@@ -728,7 +728,7 @@
                                         active ? "active" : "inactive", address,
                                         symbol.empty() ? "-" : symbol));
       }
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       if (cheriot_interface->BreakOnControlFlowChange()) {
         absl::StrAppend(&bp_list,
@@ -751,7 +751,7 @@
 
     // help
     if (RE2::FullMatch(line_view, *help_re_)) {
-      for (auto const &usage : command_usage_) {
+      for (auto const& usage : command_usage_) {
         os << usage << std::endl;
       }
       os << help_message_;
@@ -801,7 +801,7 @@
         continue;
       }
       size_t length = result.value();
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto cmd_result =
           cheriot_interface->SetDataWatchpoint(address, length, access_type);
@@ -840,7 +840,7 @@
       uint64_t address = iter->second.address;
       size_t length = iter->second.length;
       AccessType access_type = iter->second.access_type;
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto status =
           cheriot_interface->SetDataWatchpoint(address, length, access_type);
@@ -869,7 +869,7 @@
       if (!iter->second.active) continue;
       uint64_t address = iter->second.address;
       auto access_type = iter->second.access_type;
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto status =
           cheriot_interface->ClearDataWatchpoint(address, access_type);
@@ -883,12 +883,12 @@
 
     // watch clear-all
     if (RE2::FullMatch(line_view, *clear_all_watch_re_)) {
-      for (auto &[index, info] : core_access_[current_core_].watchpoint_map) {
+      for (auto& [index, info] : core_access_[current_core_].watchpoint_map) {
         if (!info.active) continue;
 
         uint64_t address = info.address;
         auto access_type = info.access_type;
-        auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+        auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
             core_access_[current_core_].debug_interface);
         auto status =
             cheriot_interface->ClearDataWatchpoint(address, access_type);
@@ -923,10 +923,10 @@
         access_type = AccessType::kLoadStore;
       }
       bool done = false;
-      for (auto &[index, info] : core_access_[current_core_].watchpoint_map) {
+      for (auto& [index, info] : core_access_[current_core_].watchpoint_map) {
         if ((info.address == result.value()) &&
             (info.access_type == access_type)) {
-          auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+          auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
               core_access_[current_core_].debug_interface);
           auto cmd_result = cheriot_interface->ClearDataWatchpoint(
               result.value(), access_type);
@@ -978,7 +978,7 @@
         continue;
       }
       size_t length = result.value();
-      auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+      auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto cmd_result =
           cheriot_interface->SetDataWatchpoint(address, length, access_type);
@@ -999,10 +999,10 @@
     // watch list
     if (RE2::FullMatch(line_view, *list_watch_re_)) {
       std::string bp_list;
-      for (auto const &[index, info] :
+      for (auto const& [index, info] :
            core_access_[current_core_].watchpoint_map) {
         std::string symbol;
-        auto *loader = core_access_[current_core_].loader_getter();
+        auto* loader = core_access_[current_core_].loader_getter();
         if (loader != nullptr) {
           auto res = loader->GetFcnSymbolName(info.address);
           if (res.ok()) symbol = std::move(res.value());
@@ -1082,7 +1082,7 @@
         os << "Error: " << result.status().message() << "\n";
         continue;
       }
-      auto *db = result.value();
+      auto* db = result.value();
       // Check for null data buffer.
       if (db == nullptr) {
         os << "Error: register '$branch_trace' has no data buffer\n";
@@ -1116,7 +1116,7 @@
 
     if (std::string file_name;
         RE2::FullMatch(line_view, *exec_re_, &file_name)) {
-      auto *ifile = new std::ifstream(file_name);
+      auto* ifile = new std::ifstream(file_name);
       if (!ifile->is_open() || !ifile->good()) {
         os << "Error: unable to open '" << file_name << "'\n";
         os.flush();
@@ -1166,7 +1166,7 @@
 
 // Templated helper function to help format integer values of different widths.
 template <typename T>
-std::string FormatDbValue(generic::DataBuffer *db, absl::string_view format,
+std::string FormatDbValue(generic::DataBuffer* db, absl::string_view format,
                           int index) {
   std::string output;
   if (index < 0 || index >= db->size<T>()) return "Error: index out of range";
@@ -1196,7 +1196,7 @@
 
 template <typename T>
 absl::Status WriteDbValue(absl::string_view str_value, absl::string_view format,
-                          int index, generic::DataBuffer *db) {
+                          int index, generic::DataBuffer* db) {
   if (index < 0 || index >= db->size<T>())
     return absl::OutOfRangeError("Error: index out of range");
   if (format[0] == 'd') {
@@ -1231,8 +1231,8 @@
 
 }  // namespace
 
-std::string DebugCommandShell::FormatSingleDbValue(generic::DataBuffer *db,
-                                                   const std::string &format,
+std::string DebugCommandShell::FormatSingleDbValue(generic::DataBuffer* db,
+                                                   const std::string& format,
                                                    int width, int index) const {
   switch (width) {
     case 8:
@@ -1248,8 +1248,8 @@
   }
 }
 
-std::string DebugCommandShell::FormatAllDbValues(generic::DataBuffer *db,
-                                                 const std::string &format,
+std::string DebugCommandShell::FormatAllDbValues(generic::DataBuffer* db,
+                                                 const std::string& format,
                                                  int width) const {
   std::string output;
   std::string sep;
@@ -1286,7 +1286,7 @@
 }
 
 absl::Status DebugCommandShell::WriteSingleValueToDb(
-    absl::string_view str_value, generic::DataBuffer *db, std::string format,
+    absl::string_view str_value, generic::DataBuffer* db, std::string format,
     int width, int index) const {
   switch (width) {
     case 8:
@@ -1304,7 +1304,7 @@
 }
 
 std::string DebugCommandShell::ReadMemory(int core,
-                                          const std::string &str_value,
+                                          const std::string& str_value,
                                           absl::string_view format) {
   int size = 0;
   char format_char = 'x';
@@ -1361,7 +1361,7 @@
   // that need to be loaded, taking into account misalignment.
   auto tag_address = address & ~0x7ULL;
   int tag_size = (address + size - tag_address + 7) / 8;
-  auto *cheriot_interface = reinterpret_cast<CheriotDebugInterface *>(
+  auto* cheriot_interface = reinterpret_cast<CheriotDebugInterface*>(
       core_access_[current_core_].debug_interface);
   auto tag_result =
       cheriot_interface->ReadTagMemory(tag_address, tag_buffer_, tag_size);
@@ -1376,15 +1376,15 @@
   }
   absl::StrAppend(&tag_string, "]");
   // Get the result and format it.
-  void *void_buffer = mem_buffer_;
+  void* void_buffer = mem_buffer_;
   std::string output;
   if ((format_char == 'f') && (bit_width >= 32)) {
     switch (bit_width) {
       case 32:
-        output = absl::StrCat(*reinterpret_cast<float *>(void_buffer));
+        output = absl::StrCat(*reinterpret_cast<float*>(void_buffer));
         break;
       case 64:
-        output = absl::StrCat(*reinterpret_cast<double *>(void_buffer));
+        output = absl::StrCat(*reinterpret_cast<double*>(void_buffer));
         break;
       default:
         break;
@@ -1392,16 +1392,16 @@
   } else if (format_char == 'd') {
     switch (bit_width) {
       case 8:
-        output = absl::StrCat(*static_cast<int8_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int8_t*>(void_buffer));
         break;
       case 16:
-        output = absl::StrCat(*static_cast<int16_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int16_t*>(void_buffer));
         break;
       case 32:
-        output = absl::StrCat(*static_cast<int32_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int32_t*>(void_buffer));
         break;
       case 64:
-        output = absl::StrCat(*static_cast<int64_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int64_t*>(void_buffer));
         break;
       default:
         break;
@@ -1411,19 +1411,19 @@
     auto pad = absl::PadSpec::kNoPad;
     switch (bit_width) {
       case 8:
-        val = *static_cast<uint8_t *>(void_buffer);
+        val = *static_cast<uint8_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad2;
         break;
       case 16:
-        val = *static_cast<uint16_t *>(void_buffer);
+        val = *static_cast<uint16_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad4;
         break;
       case 32:
-        val = *static_cast<uint32_t *>(void_buffer);
+        val = *static_cast<uint32_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad8;
         break;
       case 64:
-        val = *static_cast<uint64_t *>(void_buffer);
+        val = *static_cast<uint64_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad16;
         break;
     }
@@ -1441,9 +1441,9 @@
 }
 
 std::string DebugCommandShell::WriteMemory(int core,
-                                           const std::string &str_value1,
-                                           const std::string &format,
-                                           const std::string &str_value2) {
+                                           const std::string& str_value1,
+                                           const std::string& format,
+                                           const std::string& str_value2) {
   int size = 0;
   char format_char = '\0';
   int radix = 0;
@@ -1512,7 +1512,7 @@
 }
 
 absl::StatusOr<uint64_t> DebugCommandShell::GetValueFromString(
-    int core, const std::string &str_value, int radix) {
+    int core, const std::string& str_value, int radix) {
   size_t index;
   // Attempt to convert to a number.
   auto convert_result = riscv::internal::stoull(str_value, &index, radix);
@@ -1525,7 +1525,7 @@
     return convert_result.status();
   }
   // If all else fails, let's see if it's a symbol.
-  auto *loader = core_access_[core].loader_getter();
+  auto* loader = core_access_[core].loader_getter();
   if (loader == nullptr)
     return absl::NotFoundError("No symbol table available");
   auto result = loader->GetSymbol(str_value);
@@ -1533,7 +1533,7 @@
   return result.value().first;
 }
 
-absl::Status DebugCommandShell::StepOverCall(int core, std::ostream &os) {
+absl::Status DebugCommandShell::StepOverCall(int core, std::ostream& os) {
   auto pcc_result =
       core_access_[current_core_].debug_interface->ReadRegister("pcc");
   if (!pcc_result.ok()) {
@@ -1545,7 +1545,7 @@
   if (!inst_res.ok()) {
     return absl::UnavailableError(inst_res.status().message());
   }
-  auto *inst = inst_res.value();
+  auto* inst = inst_res.value();
   auto opcode = inst->opcode();
   // If it's not a jump-and-link, it's a single step.
   if ((opcode != *isa32::OpcodeEnum::kCheriotJal) &&
@@ -1596,7 +1596,7 @@
 }
 
 std::string DebugCommandShell::FormatCapabilityRegister(
-    int core, const std::string &reg_name) const {
+    int core, const std::string& reg_name) const {
   std::string output;
   std::vector<uint64_t> values;
   auto res =
@@ -1607,7 +1607,7 @@
   }
   values.push_back(res.value());
   // Read the capability components.
-  for (auto const &suffix :
+  for (auto const& suffix :
        {"tag", "base", "top", "length", "object_type", "permissions"}) {
     res = core_access_[current_core_].debug_interface->ReadRegister(
         absl::StrCat(reg_name, ".", suffix));
@@ -1644,12 +1644,12 @@
 }
 
 bool DebugCommandShell::IsCapabilityRegister(
-    const std::string &reg_name) const {
+    const std::string& reg_name) const {
   return capability_registers_.contains(reg_name);
 }
 
 std::string DebugCommandShell::FormatRegister(
-    int core, const std::string &reg_name) const {
+    int core, const std::string& reg_name) const {
   if (IsCapabilityRegister(reg_name)) {
     return FormatCapabilityRegister(current_core_, reg_name);
   }
@@ -1669,13 +1669,13 @@
   std::string output;
   // Interrupt stack.
   auto cheriot_state =
-      static_cast<CheriotState *>(core_access_[current_core_].state);
-  auto &info_list = cheriot_state->interrupt_info_list();
+      static_cast<CheriotState*>(core_access_[current_core_].state);
+  auto& info_list = cheriot_state->interrupt_info_list();
   int count = 0;
   if (!info_list.empty()) {
     absl::StrAppend(&output, "Interrupt stack:\n");
     for (auto iter = info_list.rbegin(); iter != info_list.rend(); ++iter) {
-      auto const &info = *iter;
+      auto const& info = *iter;
       absl::StrAppend(&output, "[", count++, "] ",
                       info.is_interrupt ? "interrupt" : "exception", " ",
                       info.is_interrupt ? GetInterruptDescription(info)
@@ -1684,7 +1684,7 @@
     absl::StrAppend(&output, "\n");
   }
   // Registers.
-  for (auto const &reg_name : reg_vector_) {
+  for (auto const& reg_name : reg_vector_) {
     absl::StrAppend(&output, FormatRegister(current_core_, reg_name), "\n");
   }
   return output;
@@ -1693,8 +1693,8 @@
 // Action point methods.
 std::string DebugCommandShell::ListActionPoints() {
   std::string output;
-  auto &action_map = core_action_point_info_[current_core_];
-  for (auto const &[local_id, info] : action_map) {
+  auto& action_map = core_action_point_info_[current_core_];
+  for (auto const& [local_id, info] : action_map) {
     absl::StrAppend(
         &output,
         absl::StrFormat("%02d  [0x%08lx] %8s  %s\n", local_id, info.address,
@@ -1704,24 +1704,24 @@
 }
 
 std::string DebugCommandShell::EnableActionPointN(
-    const std::string &index_str) {
+    const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
+  auto& info = it->second;
   if (info.is_enabled) {
     return absl::StrCat("Action point ", index, " is already enabled");
   }
   info.is_enabled = true;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *cheriot_dbg_if = static_cast<CheriotDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* cheriot_dbg_if = static_cast<CheriotDebugInterface*>(dbg_if);
   auto status = cheriot_dbg_if->EnableAction(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1730,24 +1730,24 @@
 }
 
 std::string DebugCommandShell::DisableActionPointN(
-    const std::string &index_str) {
+    const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
+  auto& info = it->second;
   if (!info.is_enabled) {
     return absl::StrCat("Action point ", index, " is already disabled");
   }
   info.is_enabled = false;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *cheriot_dbg_if = static_cast<CheriotDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* cheriot_dbg_if = static_cast<CheriotDebugInterface*>(dbg_if);
   auto status = cheriot_dbg_if->DisableAction(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1755,20 +1755,20 @@
   return "";
 }
 
-std::string DebugCommandShell::ClearActionPointN(const std::string &index_str) {
+std::string DebugCommandShell::ClearActionPointN(const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *cheriot_dbg_if = static_cast<CheriotDebugInterface *>(dbg_if);
+  auto& info = it->second;
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* cheriot_dbg_if = static_cast<CheriotDebugInterface*>(dbg_if);
   auto status = cheriot_dbg_if->ClearActionPoint(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1779,9 +1779,9 @@
 
 std::string DebugCommandShell::ClearAllActionPoints() {
   std::string output;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *cheriot_dbg_if = static_cast<CheriotDebugInterface *>(dbg_if);
-  for (auto &[local_id, info] : core_action_point_info_[current_core_]) {
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* cheriot_dbg_if = static_cast<CheriotDebugInterface*>(dbg_if);
+  for (auto& [local_id, info] : core_action_point_info_[current_core_]) {
     auto status = cheriot_dbg_if->ClearActionPoint(info.address, info.id);
     if (!status.ok()) {
       absl::StrAppend(&output, "Error: ", status.message());
@@ -1793,21 +1793,21 @@
 absl::Status DebugCommandShell::SetActionPoint(
     uint64_t address, std::string name,
     absl::AnyInvocable<void(uint64_t, int)> function) {
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *cheriot_dbg_if = static_cast<CheriotDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* cheriot_dbg_if = static_cast<CheriotDebugInterface*>(dbg_if);
   auto result = cheriot_dbg_if->SetActionPoint(address, std::move(function));
   if (!result.ok()) {
     return absl::InternalError(result.status().message());
   }
   int id = result.value();
   int local_id = core_action_point_id_[current_core_]++;
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   action_map.emplace(local_id, ActionPointInfo{address, id, name, true});
   return absl::OkStatus();
 }
 
 std::string DebugCommandShell::GetInterruptDescription(
-    const InterruptInfo &info) const {
+    const InterruptInfo& info) const {
   std::string output;
   if (!info.is_interrupt) return output;
   switch (info.cause & 0x7fff'ffff) {
@@ -1847,7 +1847,7 @@
 }
 
 std::string DebugCommandShell::GetExceptionDescription(
-    const InterruptInfo &info) const {
+    const InterruptInfo& info) const {
   std::string output;
   if (info.is_interrupt) return output;
   absl::StrAppend(&output, " Exception taken at ", absl::Hex(info.epc), ": ");

diff --git a/cheriot/debug_command_shell.h b/cheriot/debug_command_shell.h
index b32545f..36d52d1 100644
--- a/cheriot/debug_command_shell.h
+++ b/cheriot/debug_command_shell.h

@@ -61,12 +61,12 @@
   ~DebugCommandShell() override;
 
   // Add core access to the system. All cores must be added before calling Run.
-  void AddCore(const CoreAccess &core_access) override;
-  void AddCores(const std::vector<CoreAccess> &core_access) override;
+  void AddCore(const CoreAccess& core_access) override;
+  void AddCores(const std::vector<CoreAccess>& core_access) override;
 
   // The run method is the command interpreter. It parses the command strings,
   // executes the corresponding commands, displays results and error messages.
-  void Run(std::istream &is, std::ostream &os) override;
+  void Run(std::istream& is, std::ostream& os) override;
 
   // This adds a custom command to the command interpreter. Usage will be added
   // to the standard command usage. The callable will be called before the
@@ -101,7 +101,7 @@
           : callback_(std::move(callback)) {}
 
      private:
-      void SetValue(const int64_t &value) override { callback_(value); }
+      void SetValue(const int64_t& value) override { callback_(value); }
       absl::AnyInvocable<void(int64_t)> callback_;
     };
 
@@ -114,7 +114,7 @@
     static constexpr uint32_t kExceptionReturn =
         *HaltReason::kUserSpecifiedMin + 4;
 
-    explicit InterruptListener(CoreAccess *core_access);
+    explicit InterruptListener(CoreAccess* core_access);
     void SetEnableExceptions(bool value) { exceptions_enabled_ = value; }
     void SetEnableInterrupts(bool value) { interrupts_enabled_ = value; }
     bool AreExceptionsEnabled() const { return exceptions_enabled_; }
@@ -124,9 +124,9 @@
     void SetReturnValue(int64_t value);
     void SetTakenValue(int64_t value);
 
-    CoreAccess *core_access_;
-    CheriotState *state_ = nullptr;
-    CheriotDebugInterface *dbg_if_ = nullptr;
+    CoreAccess* core_access_;
+    CheriotState* state_ = nullptr;
+    CheriotDebugInterface* dbg_if_ = nullptr;
     bool interrupts_enabled_ = false;
     bool exceptions_enabled_ = false;
     Listener taken_listener_;
@@ -134,52 +134,52 @@
   };
 
   // Helper method to get the interrupt description.
-  std::string GetInterruptDescription(const InterruptInfo &info) const;
-  std::string GetExceptionDescription(const InterruptInfo &info) const;
+  std::string GetInterruptDescription(const InterruptInfo& info) const;
+  std::string GetExceptionDescription(const InterruptInfo& info) const;
 
   // Helper method for formatting single data buffer value.
-  std::string FormatSingleDbValue(generic::DataBuffer *db,
-                                  const std::string &format, int width,
+  std::string FormatSingleDbValue(generic::DataBuffer* db,
+                                  const std::string& format, int width,
                                   int index) const;
   // Helper method for formatting multiple data buffer values.
-  std::string FormatAllDbValues(generic::DataBuffer *db,
-                                const std::string &format, int width) const;
+  std::string FormatAllDbValues(generic::DataBuffer* db,
+                                const std::string& format, int width) const;
   // Helper method for writing single data buffer value.
   absl::Status WriteSingleValueToDb(absl::string_view str_value,
-                                    generic::DataBuffer *db, std::string format,
+                                    generic::DataBuffer* db, std::string format,
                                     int width, int index) const;
 
   // Helper method for processing read memory command.
-  std::string ReadMemory(int core, const std::string &str_value,
+  std::string ReadMemory(int core, const std::string& str_value,
                          absl::string_view format);
   // Helper method for processing write memory command.
-  std::string WriteMemory(int core, const std::string &str_value1,
-                          const std::string &format,
-                          const std::string &str_value2);
+  std::string WriteMemory(int core, const std::string& str_value1,
+                          const std::string& format,
+                          const std::string& str_value2);
   // Helper method used to parse a numeric string or use the string as a
   // symbol name for lookup in the loader.
   absl::StatusOr<uint64_t> GetValueFromString(int core,
-                                              const std::string &str_value,
+                                              const std::string& str_value,
                                               int radix);
 
   // Method to step over call instructions.
-  absl::Status StepOverCall(int core, std::ostream &os);
+  absl::Status StepOverCall(int core, std::ostream& os);
 
   // Returns true if the given register name is a known capability register.
-  bool IsCapabilityRegister(const std::string &reg_name) const;
+  bool IsCapabilityRegister(const std::string& reg_name) const;
   // Reads and formats a capability register.
   std::string FormatCapabilityRegister(int core,
-                                       const std::string &reg_name) const;
+                                       const std::string& reg_name) const;
   // Reads and formats a register.
-  std::string FormatRegister(int core, const std::string &reg_name) const;
+  std::string FormatRegister(int core, const std::string& reg_name) const;
   // Reads and formats $all registers - stored in reg_vec_.
   std::string FormatAllRegisters(int core) const;
 
   // Action point handling.
   std::string ListActionPoints();
-  std::string EnableActionPointN(const std::string &index_str);
-  std::string DisableActionPointN(const std::string &index_str);
-  std::string ClearActionPointN(const std::string &index_str);
+  std::string EnableActionPointN(const std::string& index_str);
+  std::string DisableActionPointN(const std::string& index_str);
+  std::string ClearActionPointN(const std::string& index_str);
   std::string ClearAllActionPoints();
 
   std::vector<CoreAccess> core_access_;
@@ -246,11 +246,11 @@
   absl::flat_hash_set<std::string> capability_registers_;
   std::vector<std::string> reg_vector_;
   absl::flat_hash_set<std::string> exec_file_names_;
-  std::deque<std::istream *> command_streams_;
+  std::deque<std::istream*> command_streams_;
   std::deque<std::string> previous_commands_;
   std::vector<absl::btree_map<int, ActionPointInfo>> core_action_point_info_;
   std::vector<int> core_action_point_id_;
-  std::vector<InterruptListener *> interrupt_listeners_;
+  std::vector<InterruptListener*> interrupt_listeners_;
 };
 
 }  // namespace cheriot

diff --git a/cheriot/mpact_cheriot.cc b/cheriot/mpact_cheriot.cc
index fa40b27..fd2e1a2 100644
--- a/cheriot/mpact_cheriot.cc
+++ b/cheriot/mpact_cheriot.cc

@@ -180,7 +180,7 @@
 using ::mpact::sim::util::TaggedMemoryWatcher;
 
 // Static pointer to the top instance. Used by the control-C handler.
-static CheriotTop *top = nullptr;
+static CheriotTop* top = nullptr;
 
 // Control-c handler to interrupt any running simulation.
 static void sim_sigint_handler(int arg) {
@@ -196,8 +196,8 @@
 // debug command shell.
 static bool PrintRegisters(
     absl::string_view input,
-    const mpact::sim::cheriot::DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    const mpact::sim::cheriot::DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   static const LazyRE2 reg_info_re{R"(\s*xyzreg\s+info\s*)"};
   if (!RE2::FullMatch(input, *reg_info_re)) return false;
 
@@ -219,7 +219,7 @@
 
 // Trap handler.
 bool HandleSimulatorTrap(bool is_interrupt, uint64_t trap_value, uint64_t ec,
-                         uint64_t epc, const Instruction *instruction) {
+                         uint64_t epc, const Instruction* instruction) {
   if (is_interrupt) return false;
   std::cerr << absl::StrCat(
       "Exception\n"
@@ -240,7 +240,7 @@
 }
 
 // Main function for the simulator.
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   absl::SetProgramUsageMessage(argv[0]);
   auto arg_vec = absl::ParseCommandLine(argc, argv);
   int exit_code = 0;
@@ -255,7 +255,7 @@
       full_file_name.substr(full_file_name.find_last_of('/') + 1);
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
-  auto *tagged_memory =
+  auto* tagged_memory =
       new mpact::sim::util::TaggedFlatDemandMemory(kCapabilityGranule);
   // Load the elf segments into memory.
   mpact::sim::util::ElfProgramLoader elf_loader(tagged_memory);
@@ -265,10 +265,10 @@
               << "': " << load_result.status().message();
     return -1;
   }
-  auto *router = new mpact::sim::util::SingleInitiatorRouter("router");
-  TaggedMemoryInterface *data_memory =
-      static_cast<TaggedMemoryInterface *>(router);
-  TaggedMemoryUseProfiler *memory_use_profiler = nullptr;
+  auto* router = new mpact::sim::util::SingleInitiatorRouter("router");
+  TaggedMemoryInterface* data_memory =
+      static_cast<TaggedMemoryInterface*>(router);
+  TaggedMemoryUseProfiler* memory_use_profiler = nullptr;
   // Check to see if memory use profiling is enabled, and if so, set it up.
   if (absl::GetFlag(FLAGS_mem_profile)) {
     memory_use_profiler = new TaggedMemoryUseProfiler(data_memory);
@@ -277,19 +277,19 @@
     data_memory = memory_use_profiler;
   }
   CheriotState cheriot_state("CherIoT", data_memory,
-                             static_cast<AtomicMemoryOpInterface *>(router));
+                             static_cast<AtomicMemoryOpInterface*>(router));
   cheriot_state.set_core_version(absl::GetFlag(FLAGS_core_version));
 
-  DecoderInterface *decoder = nullptr;
+  DecoderInterface* decoder = nullptr;
   if (absl::GetFlag(FLAGS_rvv_fp)) {
     decoder = new CheriotRVVFPDecoder(&cheriot_state,
-                                      static_cast<MemoryInterface *>(router));
+                                      static_cast<MemoryInterface*>(router));
   } else if (absl::GetFlag(FLAGS_rvv_fp)) {
     decoder = new CheriotRVVDecoder(&cheriot_state,
-                                    static_cast<MemoryInterface *>(router));
+                                    static_cast<MemoryInterface*>(router));
   } else {
     decoder = new CheriotDecoder(&cheriot_state,
-                                 static_cast<MemoryInterface *>(router));
+                                 static_cast<MemoryInterface*>(router));
   }
 
   CheriotTop cheriot_top("Cheriot", &cheriot_state, decoder);
@@ -298,7 +298,7 @@
     ComponentValueEntry icache_value;
     icache_value.set_name("icache");
     icache_value.set_string_value(absl::GetFlag(FLAGS_icache));
-    auto *cfg = cheriot_top.GetConfig("icache");
+    auto* cfg = cheriot_top.GetConfig("icache");
     auto status = cfg->Import(&icache_value);
     if (!status.ok()) return -1;
   }
@@ -307,17 +307,17 @@
     ComponentValueEntry dcache_value;
     dcache_value.set_name("dcache");
     dcache_value.set_string_value(absl::GetFlag(FLAGS_dcache));
-    auto *cfg = cheriot_top.GetConfig("dcache");
+    auto* cfg = cheriot_top.GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return -1;
     // Hook the cache into the memory port.
-    auto *dcache = cheriot_top.dcache();
+    auto* dcache = cheriot_top.dcache();
     dcache->set_memory(cheriot_top.state()->tagged_memory());
     cheriot_top.state()->set_tagged_memory(dcache);
   }
 
   // Enable instruction profiling if the flag is set.
-  InstructionProfiler *inst_profiler = nullptr;
+  InstructionProfiler* inst_profiler = nullptr;
   if (absl::GetFlag(FLAGS_inst_profile)) {
     inst_profiler = new InstructionProfiler(elf_loader, 2);
     cheriot_top.counter_pc()->AddListener(inst_profiler);
@@ -325,7 +325,7 @@
     cheriot_top.counter_pc()->SetIsEnabled(false);
   }
 
-  mpact::sim::generic::DataBuffer *db = nullptr;
+  mpact::sim::generic::DataBuffer* db = nullptr;
 
   // If tohost exists, add a memory watcher to look for exit signal.
   auto tohost_res = elf_loader.GetSymbol("tohost");
@@ -369,10 +369,10 @@
     std::cerr << "Error while initializing minstret/minstreth";
     return -1;
   }
-  auto *minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
+  auto* minstret = static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(
       minstret_res.value());
-  auto *minstreth =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(minstreth_res.value());
+  auto* minstreth =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(minstreth_res.value());
   minstret->set_counter(cheriot_top.counter_num_instructions());
   minstreth->set_counter(cheriot_top.counter_num_instructions());
 
@@ -384,24 +384,24 @@
     std::cerr << "Error while initializing mcycle/mcycleh";
     return -1;
   }
-  auto *mcycle = static_cast<RiscVCounterCsr<uint32_t, CheriotState> *>(
-      mcycle_res.value());
-  auto *mcycleh =
-      static_cast<RiscVCounterCsrHigh<CheriotState> *>(mcycleh_res.value());
+  auto* mcycle =
+      static_cast<RiscVCounterCsr<uint32_t, CheriotState>*>(mcycle_res.value());
+  auto* mcycleh =
+      static_cast<RiscVCounterCsrHigh<CheriotState>*>(mcycleh_res.value());
   mcycle->set_counter(cheriot_top.counter_num_cycles());
   mcycleh->set_counter(cheriot_top.counter_num_cycles());
 
   // Set up the memory router with the appropriate targets.
-  ::mpact::sim::util::AtomicMemory *atomic_memory = nullptr;
+  ::mpact::sim::util::AtomicMemory* atomic_memory = nullptr;
   atomic_memory = new mpact::sim::util::AtomicMemory(tagged_memory);
 
-  auto *uart = new SimpleUart(cheriot_top.state());
+  auto* uart = new SimpleUart(cheriot_top.state());
 
   auto uart_base = absl::GetFlag(FLAGS_uart);
   auto clint_base = absl::GetFlag(FLAGS_clint);
   CHECK_OK(router->AddTarget<MemoryInterface>(uart, uart_base,
                                               uart_base + 0x100ULL - 1));
-  auto *clint = new RiscVClint(/*period=*/100, cheriot_top.state()->mip());
+  auto* clint = new RiscVClint(/*period=*/100, cheriot_top.state()->mip());
   cheriot_top.counter_num_cycles()->AddListener(clint);
   CHECK_OK(router->AddTarget<MemoryInterface>(clint, clint_base,
                                               clint_base + 0x10000ULL - 1));
@@ -409,8 +409,8 @@
   CHECK_OK(router->AddDefaultTarget<TaggedMemoryInterface>(tagged_memory));
 
   // Set up a dummy WFI handler.
-  cheriot_top.state()->set_on_wfi([](const Instruction *) { return true; });
-  cheriot_top.state()->set_on_ecall([](const Instruction *) { return false; });
+  cheriot_top.state()->set_on_wfi([](const Instruction*) { return true; });
+  cheriot_top.state()->set_on_ecall([](const Instruction*) { return false; });
   // Initialize the PC to the entry point.
   uint32_t entry_point = load_result.value();
   auto pcc_write = cheriot_top.WriteRegister("pcc", entry_point);
@@ -420,11 +420,11 @@
   }
 
   // Set up semihosting.
-  auto *memory = static_cast<MemoryInterface *>(router);
-  auto *semihost =
+  auto* memory = static_cast<MemoryInterface*>(router);
+  auto* semihost =
       new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord32, memory, memory);
   semihost->SetCmdLine(arg_vec);
-  cheriot_top.state()->AddEbreakHandler([semihost](const Instruction *inst) {
+  cheriot_top.state()->AddEbreakHandler([semihost](const Instruction* inst) {
     if (semihost->IsSemihostingCall(inst)) {
       semihost->OnEBreak(inst);
       return true;
@@ -509,7 +509,7 @@
 
   // Determine if this is being run interactively or as a batch job.
   bool interactive = absl::GetFlag(FLAGS_i) || absl::GetFlag(FLAGS_interactive);
-  CheriotInstrumentationControl *cheriot_instrumentation_control = nullptr;
+  CheriotInstrumentationControl* cheriot_instrumentation_control = nullptr;
   if (interactive) {
     mpact::sim::cheriot::DebugCommandShell cmd_shell;
     cmd_shell.AddCore({&cheriot_top, [&elf_loader]() { return &elf_loader; },

diff --git a/cheriot/riscv_cheriot_a_instructions.cc b/cheriot/riscv_cheriot_a_instructions.cc
index 26d79cb..314b2a2 100644
--- a/cheriot/riscv_cheriot_a_instructions.cc
+++ b/cheriot/riscv_cheriot_a_instructions.cc

@@ -38,10 +38,10 @@
 
 // Helper function for the atomic memory operation semantic functions.
 template <typename T>
-static inline void AInstructionHelper(Instruction *inst, Operation op,
+static inline void AInstructionHelper(Instruction* inst, Operation op,
                                       bool has_store_value) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *atomic = state->atomic_tagged_memory();
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* atomic = state->atomic_tagged_memory();
   // If the atomic memory operation interface is nullptr, this is an illegal
   // instruction.
   if (atomic == nullptr) {
@@ -51,14 +51,14 @@
   }
   // Submit the memory operation.
   auto address = generic::GetInstructionSource<uint64_t>(inst, 0);
-  auto *db = inst->state()->db_factory()->Allocate<T>(1);
+  auto* db = inst->state()->db_factory()->Allocate<T>(1);
   db->set_latency(0);
   // Only access the operand if there is a value to be read.
   if (has_store_value) {
     db->template Set<T>(0, generic::GetInstructionSource<T>(inst, 1));
   }
   // This transfers ownership of db to context. Don't DecRef.
-  auto *context = new riscv::LoadContext(db);
+  auto* context = new riscv::LoadContext(db);
   auto status = state->atomic_tagged_memory()->PerformMemoryOp(
       address, op, db, inst->child(), context);
   // If the operation is unimplemented, this is an illegal instruction.
@@ -70,57 +70,57 @@
   context->DecRef();
 }
 
-void ALrw(Instruction *instruction) {
+void ALrw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kLoadLinked,
                                /*has_store_value*/ false);
 }
 
-void AScw(Instruction *instruction) {
+void AScw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kStoreConditional,
                                /*has_store_value*/ true);
 }
 
-void AAmoswapw(Instruction *instruction) {
+void AAmoswapw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicSwap,
                                /*has_store_value*/ true);
 }
 
-void AAmoaddw(Instruction *instruction) {
+void AAmoaddw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicAdd,
                                /*has_store_value*/ true);
 }
 
-void AAmoandw(Instruction *instruction) {
+void AAmoandw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicAnd,
                                /*has_store_value*/ true);
 }
 
-void AAmoorw(Instruction *instruction) {
+void AAmoorw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicOr,
                                /*has_store_value*/ true);
 }
 
-void AAmoxorw(Instruction *instruction) {
+void AAmoxorw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicXor,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxw(Instruction *instruction) {
+void AAmomaxw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMax,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxuw(Instruction *instruction) {
+void AAmomaxuw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMaxu,
                                /*has_store_value*/ true);
 }
 
-void AAmominw(Instruction *instruction) {
+void AAmominw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMin,
                                /*has_store_value*/ true);
 }
 
-void AAmominuw(Instruction *instruction) {
+void AAmominuw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMinu,
                                /*has_store_value*/ true);
 }

diff --git a/cheriot/riscv_cheriot_a_instructions.h b/cheriot/riscv_cheriot_a_instructions.h
index 55babb7..3366639 100644
--- a/cheriot/riscv_cheriot_a_instructions.h
+++ b/cheriot/riscv_cheriot_a_instructions.h

@@ -34,23 +34,23 @@
 // memory to access, the second is the acquire bit, and the third, the release
 // bit. The instruction has a single destination operand which is the register
 // to write the result to.
-void ALrw(Instruction *instruction);
+void ALrw(Instruction* instruction);
 // The following instructions take 4 source operands and one destination
 // operand. The first source is the register holding the address of the
 // memory to access, the second is the register value used in the memory
 // operation (to store, swap, etc), the third is the acquire bit, and the
 // fourth, the release bit. The instruction has a single destination operand
 // which is the register to write the result to.
-void AScw(Instruction *instruction);
-void AAmoswapw(Instruction *instruction);
-void AAmoaddw(Instruction *instruction);
-void AAmoandw(Instruction *instruction);
-void AAmoorw(Instruction *instruction);
-void AAmoxorw(Instruction *instruction);
-void AAmomaxw(Instruction *instruction);
-void AAmomaxuw(Instruction *instruction);
-void AAmominw(Instruction *instruction);
-void AAmominuw(Instruction *instruction);
+void AScw(Instruction* instruction);
+void AAmoswapw(Instruction* instruction);
+void AAmoaddw(Instruction* instruction);
+void AAmoandw(Instruction* instruction);
+void AAmoorw(Instruction* instruction);
+void AAmoxorw(Instruction* instruction);
+void AAmomaxw(Instruction* instruction);
+void AAmomaxuw(Instruction* instruction);
+void AAmominw(Instruction* instruction);
+void AAmominuw(Instruction* instruction);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_encoding.cc b/cheriot/riscv_cheriot_encoding.cc
index be376d7..787267f 100644
--- a/cheriot/riscv_cheriot_encoding.cc
+++ b/cheriot/riscv_cheriot_encoding.cc

@@ -33,7 +33,7 @@
 
 using Extractors = ::mpact::sim::cheriot::encoding::Extractors;
 
-RiscVCheriotEncoding::RiscVCheriotEncoding(CheriotState *state)
+RiscVCheriotEncoding::RiscVCheriotEncoding(CheriotState* state)
     : RiscVCheriotEncodingCommon(state) {
   source_op_getters_.emplace(*SourceOpEnum::kNone, []() { return nullptr; });
   dest_op_getters_.emplace(*DestOpEnum::kNone,
@@ -73,7 +73,7 @@
   format_ = format;
 }
 
-DestinationOperandInterface *RiscVCheriotEncoding::GetDestination(
+DestinationOperandInterface* RiscVCheriotEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -87,7 +87,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscVCheriotEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscVCheriotEncoding::GetSource(SlotEnum, int,
                                                         OpcodeEnum opcode,
                                                         SourceOpEnum source_op,
                                                         int source_no) {

diff --git a/cheriot/riscv_cheriot_encoding.h b/cheriot/riscv_cheriot_encoding.h
index 7bcaa72..1ede3ee 100644
--- a/cheriot/riscv_cheriot_encoding.h
+++ b/cheriot/riscv_cheriot_encoding.h

@@ -43,11 +43,11 @@
                              public RiscVCheriotEncodingBase {
  public:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
-  explicit RiscVCheriotEncoding(CheriotState *state);
+  explicit RiscVCheriotEncoding(CheriotState* state);
 
   // Parses an instruction and determines the opcode.
   void ParseInstruction(uint32_t inst_word);
@@ -62,19 +62,19 @@
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
   // Currently no resources modeled for RiscV CHERIoT.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override {
     return nullptr;
@@ -82,12 +82,12 @@
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -97,8 +97,8 @@
     return 0;
   }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
 
  private:
   SourceOpGetterMap source_op_getters_;

diff --git a/cheriot/riscv_cheriot_encoding_common.h b/cheriot/riscv_cheriot_encoding_common.h
index 7a355b9..bc1c139 100644
--- a/cheriot/riscv_cheriot_encoding_common.h
+++ b/cheriot/riscv_cheriot_encoding_common.h

@@ -29,14 +29,14 @@
 
 class RiscVCheriotEncodingCommon {
  public:
-  explicit RiscVCheriotEncodingCommon(CheriotState *state) : state_(state) {}
+  explicit RiscVCheriotEncodingCommon(CheriotState* state) : state_(state) {}
 
   // Accessors.
-  CheriotState *state() const { return state_; }
+  CheriotState* state() const { return state_; }
   uint32_t inst_word() const { return inst_word_; }
 
  protected:
-  CheriotState *state_;
+  CheriotState* state_;
   uint32_t inst_word_;
 };
 

diff --git a/cheriot/riscv_cheriot_f_instructions.cc b/cheriot/riscv_cheriot_f_instructions.cc
index 26e2dd6..1bf82ae 100644
--- a/cheriot/riscv_cheriot_f_instructions.cc
+++ b/cheriot/riscv_cheriot_f_instructions.cc

@@ -63,25 +63,25 @@
 
 // Convert float to signed 32 bit integer.
 template <typename XInt>
-static inline void RVFCvtWs(const Instruction *instruction) {
+static inline void RVFCvtWs(const Instruction* instruction) {
   RVCheriotConvertFloatWithFflagsOp<XInt, float, int32_t>(instruction);
 }
 
 // Convert float to unsigned 32 bit integer.
 template <typename XInt>
-static inline void RVFCvtWus(const Instruction *instruction) {
+static inline void RVFCvtWus(const Instruction* instruction) {
   RVCheriotConvertFloatWithFflagsOp<XInt, float, uint32_t>(instruction);
 }
 
 // Single precision compare equal.
 template <typename XRegister>
-static inline void RVFCmpeq(const Instruction *instruction) {
+static inline void RVFCmpeq(const Instruction* instruction) {
   RVCheriotBinaryOp<typename XRegister::ValueType,
                     typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -91,13 +91,13 @@
 
 // Single precicion compare less than.
 template <typename XRegister>
-static inline void RVFCmplt(const Instruction *instruction) {
+static inline void RVFCmplt(const Instruction* instruction) {
   RVCheriotBinaryOp<typename XRegister::ValueType,
                     typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsNaN(a) || FPTypeInfo<float>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -107,13 +107,13 @@
 
 // Single precision compare less than or equal.
 template <typename XRegister>
-static inline void RVFCmple(const Instruction *instruction) {
+static inline void RVFCmple(const Instruction* instruction) {
   RVCheriotBinaryOp<typename XRegister::ValueType,
                     typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsNaN(a) || FPTypeInfo<float>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -125,17 +125,17 @@
 static inline T CanonicalizeNaN(T value) {
   if (!std::isnan(value)) return value;
   auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-  return *reinterpret_cast<T *>(&nan_value);
+  return *reinterpret_cast<T*>(&nan_value);
 }
 
 }  // namespace internal
 
 // Load child instruction.
-void RiscVIFlwChild(const Instruction *instruction) {
-  LoadContext *context = static_cast<LoadContext *>(instruction->context());
+void RiscVIFlwChild(const Instruction* instruction) {
+  LoadContext* context = static_cast<LoadContext*>(instruction->context());
   auto value = context->value_db->Get<FPUInt>(0);
-  auto *reg =
-      static_cast<generic::RegisterDestinationOperand<FPRegister::ValueType> *>(
+  auto* reg =
+      static_cast<generic::RegisterDestinationOperand<FPRegister::ValueType>*>(
           instruction->Destination(0))
           ->GetRegister();
   if (sizeof(FPRegister::ValueType) > sizeof(FPUInt)) {
@@ -150,44 +150,43 @@
 }
 
 // Basic arithmetic instructions.
-void RiscVFAdd(const Instruction *instruction) {
+void RiscVFAdd(const Instruction* instruction) {
   RVCheriotBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a + b; });
 }
 
-void RiscVFSub(const Instruction *instruction) {
+void RiscVFSub(const Instruction* instruction) {
   RVCheriotBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a - b; });
 }
 
-void RiscVFMul(const Instruction *instruction) {
+void RiscVFMul(const Instruction* instruction) {
   RVCheriotBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a * b; });
 }
 
-void RiscVFDiv(const Instruction *instruction) {
+void RiscVFDiv(const Instruction* instruction) {
   RVCheriotBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a / b; });
 }
 
 // Square root uses the library square root.
-void RiscVFSqrt(const Instruction *instruction) {
+void RiscVFSqrt(const Instruction* instruction) {
   RVCheriotUnaryFloatNaNBoxOp<FPRegister::ValueType, FPRegister::ValueType,
                               float, float>(instruction, [](float a) -> float {
     float res = sqrt(a);
     if (std::isnan(res))
-      return *reinterpret_cast<const float *>(
-          &FPTypeInfo<float>::kCanonicalNaN);
+      return *reinterpret_cast<const float*>(&FPTypeInfo<float>::kCanonicalNaN);
     return res;
   });
 }
 
 // If either operand is NaN return the other.
-void RiscVFMin(const Instruction *instruction) {
+void RiscVFMin(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, float, float>(
       instruction, [instruction](float a, float b) -> float {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -195,7 +194,7 @@
           if (FPTypeInfo<float>::IsNaN(b)) {
             FPTypeInfo<float>::UIntType not_a_number =
                 FPTypeInfo<float>::kCanonicalNaN;
-            return *reinterpret_cast<float *>(&not_a_number);
+            return *reinterpret_cast<float*>(&not_a_number);
           }
           return b;
         }
@@ -207,11 +206,11 @@
 }
 
 // If either operand is NaN return the other.
-void RiscVFMax(const Instruction *instruction) {
+void RiscVFMax(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, float, float>(
       instruction, [instruction](float a, float b) -> float {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -219,7 +218,7 @@
           if (FPTypeInfo<float>::IsNaN(b)) {
             FPTypeInfo<float>::UIntType not_a_number =
                 FPTypeInfo<float>::kCanonicalNaN;
-            return *reinterpret_cast<float *>(&not_a_number);
+            return *reinterpret_cast<float*>(&not_a_number);
           }
           return b;
         }
@@ -236,12 +235,12 @@
 // Negated multiply-add -((a * b) + c)
 // Negated multiply-subtract -((a * b) - c)
 
-void RiscVFMadd(const Instruction *instruction) {
+void RiscVFMadd(const Instruction* instruction) {
   using T = float;
   RVCheriotTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -249,12 +248,12 @@
       });
 }
 
-void RiscVFMsub(const Instruction *instruction) {
+void RiscVFMsub(const Instruction* instruction) {
   using T = float;
   RVCheriotTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -262,12 +261,12 @@
       });
 }
 
-void RiscVFNmadd(const Instruction *instruction) {
+void RiscVFNmadd(const Instruction* instruction) {
   using T = float;
   RVCheriotTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -275,12 +274,12 @@
       });
 }
 
-void RiscVFNmsub(const Instruction *instruction) {
+void RiscVFNmsub(const Instruction* instruction) {
   using T = float;
   RVCheriotTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -289,14 +288,14 @@
 }
 
 // Set sign of the first operand to that of the second.
-void RiscVFSgnj(const Instruction *instruction) {
+void RiscVFSgnj(const Instruction* instruction) {
   RVCheriotBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction,
       [](FPUInt a, FPUInt b) { return (a & 0x7fff'ffff) | (b & 0x8000'0000); });
 }
 
 // Set the sign of the first operand to the opposite of the second.
-void RiscVFSgnjn(const Instruction *instruction) {
+void RiscVFSgnjn(const Instruction* instruction) {
   RVCheriotBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction, [](FPUInt a, FPUInt b) {
         return (a & 0x7fff'ffff) | (~b & 0x8000'0000);
@@ -305,7 +304,7 @@
 
 // Set the sign of the first operand to the xor of the signs of the two
 // operands.
-void RiscVFSgnjx(const Instruction *instruction) {
+void RiscVFSgnjx(const Instruction* instruction) {
   RVCheriotBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction, [](FPUInt a, FPUInt b) {
         return (a & 0x7fff'ffff) | ((a ^ b) & 0x8000'0000);
@@ -313,19 +312,19 @@
 }
 
 // Convert signed 32 bit integer to float.
-void RiscVFCvtSw(const Instruction *instruction) {
+void RiscVFCvtSw(const Instruction* instruction) {
   RVCheriotUnaryFloatNaNBoxOp<FPRegister::ValueType, uint32_t, float, int32_t>(
       instruction, [](int32_t a) -> float { return static_cast<float>(a); });
 }
 
 // Convert unsigned 32 bit integer to float.
-void RiscVFCvtSwu(const Instruction *instruction) {
+void RiscVFCvtSwu(const Instruction* instruction) {
   RVCheriotUnaryFloatNaNBoxOp<FPRegister::ValueType, uint32_t, float, uint32_t>(
       instruction, [](uint32_t a) -> float { return static_cast<float>(a); });
 }
 
 // Single precision move instruction from integer to fp register file.
-void RiscVFMvwx(const Instruction *instruction) {
+void RiscVFMvwx(const Instruction* instruction) {
   RVCheriotUnaryNaNBoxOp<FPRegister::ValueType, uint32_t, uint32_t, uint32_t>(
       instruction, [](uint32_t a) -> uint32_t { return a; });
 }
@@ -336,8 +335,8 @@
 using XUint = typename std::make_unsigned<XRegister::ValueType>::type;
 using XInt = typename std::make_signed<XRegister::ValueType>::type;
 
-void RiscVFSw(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void RiscVFSw(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   if (state->mstatus()->fs() == 0) return;
   RVCheriotStore<CheriotRegister, int32_t>(instruction);
 }
@@ -345,39 +344,39 @@
 // Single precision conversion instructions.
 
 // Convert float to signed 32 bit integer.
-void RiscVFCvtWs(const Instruction *instruction) {
+void RiscVFCvtWs(const Instruction* instruction) {
   internal::RVFCvtWs<XInt>(instruction);
 }
 
 // Convert float to unsigned 32 bit integer.
-void RiscVFCvtWus(const Instruction *instruction) {
+void RiscVFCvtWus(const Instruction* instruction) {
   internal::RVFCvtWus<XInt>(instruction);
 }
 
 // Single precision move instruction to integer register file, with
 // sign-extension.
-void RiscVFMvxw(const Instruction *instruction) {
+void RiscVFMvxw(const Instruction* instruction) {
   RVCheriotUnaryOp<XRegister, int32_t, int32_t>(instruction,
                                                 [](int32_t a) { return a; });
 }
 
 // Single precision compare equal.
-void RiscVFCmpeq(const Instruction *instruction) {
+void RiscVFCmpeq(const Instruction* instruction) {
   internal::RVFCmpeq<XRegister>(instruction);
 }
 
 // Single precicion compare less than.
-void RiscVFCmplt(const Instruction *instruction) {
+void RiscVFCmplt(const Instruction* instruction) {
   internal::RVFCmplt<XRegister>(instruction);
 }
 
 // Single precision compare less than or equal.
-void RiscVFCmple(const Instruction *instruction) {
+void RiscVFCmple(const Instruction* instruction) {
   internal::RVFCmple<XRegister>(instruction);
 }
 
 // Single precision fp class instruction.
-void RiscVFClass(const Instruction *instruction) {
+void RiscVFClass(const Instruction* instruction) {
   RVCheriotUnaryOp<XRegister, uint32_t, float>(
       instruction,
       [](float a) -> uint32_t { return static_cast<uint32_t>(ClassifyFP(a)); });

diff --git a/cheriot/riscv_cheriot_f_instructions.h b/cheriot/riscv_cheriot_f_instructions.h
index b7a680f..3338227 100644
--- a/cheriot/riscv_cheriot_f_instructions.h
+++ b/cheriot/riscv_cheriot_f_instructions.h

@@ -31,62 +31,62 @@
 // Single precision arithmetic instructions each take 3 source operands and
 // 1 destination register operand. Source 0 and 1 are the data sources to the
 // operation, source 2 is the rounding mode specifier in the instruction.
-void RiscVFAdd(const Instruction *instruction);
-void RiscVFSub(const Instruction *instruction);
-void RiscVFMul(const Instruction *instruction);
-void RiscVFDiv(const Instruction *instruction);
+void RiscVFAdd(const Instruction* instruction);
+void RiscVFSub(const Instruction* instruction);
+void RiscVFMul(const Instruction* instruction);
+void RiscVFDiv(const Instruction* instruction);
 // Single precision load child instruction takes a single destination operand.
-void RiscVIFlwChild(const Instruction *instruction);
+void RiscVIFlwChild(const Instruction* instruction);
 // Single precision square root takes 2 source operands, the source register
 // and the rounding mode, and 1 destination register operand.
-void RiscVFSqrt(const Instruction *instruction);
+void RiscVFSqrt(const Instruction* instruction);
 // The single precision Min and Max instructions each take 2 source register
 // operands and 1 destination register operand.
-void RiscVFMin(const Instruction *instruction);
-void RiscVFMax(const Instruction *instruction);
+void RiscVFMin(const Instruction* instruction);
+void RiscVFMax(const Instruction* instruction);
 // The following four multiply-accumulate instruction each take 3 source
 // register operands (0, 1, 2) and the rounding mode (3), and one destination
 // register operand.
-void RiscVFMadd(const Instruction *instruction);
-void RiscVFMsub(const Instruction *instruction);
-void RiscVFNmadd(const Instruction *instruction);
-void RiscVFNmsub(const Instruction *instruction);
+void RiscVFMadd(const Instruction* instruction);
+void RiscVFMsub(const Instruction* instruction);
+void RiscVFNmadd(const Instruction* instruction);
+void RiscVFNmsub(const Instruction* instruction);
 // The single precision sign manipulation instructions take 2 source register
 // operands and a single destination register operand.
-void RiscVFSgnj(const Instruction *instruction);
-void RiscVFSgnjn(const Instruction *instruction);
-void RiscVFSgnjx(const Instruction *instruction);
+void RiscVFSgnj(const Instruction* instruction);
+void RiscVFSgnjn(const Instruction* instruction);
+void RiscVFSgnjx(const Instruction* instruction);
 // The single precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVFCvtSw(const Instruction *instruction);
-void RiscVFCvtSwu(const Instruction *instruction);
-void RiscVFCvtSl(const Instruction *instruction);
-void RiscVFCvtSlu(const Instruction *instruction);
+void RiscVFCvtSw(const Instruction* instruction);
+void RiscVFCvtSwu(const Instruction* instruction);
+void RiscVFCvtSl(const Instruction* instruction);
+void RiscVFCvtSlu(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
-void RiscVFMvwx(const Instruction *instruction);
+void RiscVFMvwx(const Instruction* instruction);
 
 namespace RV32 {
 
 // Store float instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVFSw(const Instruction *instruction);
+void RiscVFSw(const Instruction* instruction);
 // Single precision load child instruction takes a single destination operand.
 // The single precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVFCvtWs(const Instruction *instruction);
-void RiscVFCvtWus(const Instruction *instruction);
+void RiscVFCvtWs(const Instruction* instruction);
+void RiscVFCvtWus(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
 // destination register operand.
-void RiscVFMvxw(const Instruction *instruction);
+void RiscVFMvxw(const Instruction* instruction);
 // The single precision compare instructions take 2 source register operands
 // and a single destination register operand.
-void RiscVFCmpeq(const Instruction *instruction);
-void RiscVFCmplt(const Instruction *instruction);
-void RiscVFCmple(const Instruction *instruction);
+void RiscVFCmpeq(const Instruction* instruction);
+void RiscVFCmplt(const Instruction* instruction);
+void RiscVFCmple(const Instruction* instruction);
 // The single precision class instruction takes a single source register operand
 // and a single destination register operand.
-void RiscVFClass(const Instruction *instruction);
+void RiscVFClass(const Instruction* instruction);
 
 }  // namespace RV32
 

diff --git a/cheriot/riscv_cheriot_i_instructions.cc b/cheriot/riscv_cheriot_i_instructions.cc
index 3baf3bf..e663619 100644
--- a/cheriot/riscv_cheriot_i_instructions.cc
+++ b/cheriot/riscv_cheriot_i_instructions.cc

@@ -32,8 +32,8 @@
 
 using EC = ::mpact::sim::riscv::ExceptionCode;
 
-void RiscVIllegalInstruction(const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
+void RiscVIllegalInstruction(const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
   // Get instruction word, as it needs to be used as trap value.
   uint64_t address = inst->address();
   auto db = state->db_factory()->Allocate<uint32_t>(1);
@@ -61,59 +61,59 @@
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 using IntReg = typename std::make_signed<UIntReg>::type;
 
-void RiscVIAdd(const Instruction *instruction) {
+void RiscVIAdd(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a + b; });
 }
 
-void RiscVISub(const Instruction *instruction) {
+void RiscVISub(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a - b; });
 }
 
-void RiscVISlt(const Instruction *instruction) {
+void RiscVISlt(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVISltu(const Instruction *instruction) {
+void RiscVISltu(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIAnd(const Instruction *instruction) {
+void RiscVIAnd(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a & b; });
 }
 
-void RiscVIOr(const Instruction *instruction) {
+void RiscVIOr(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | b; });
 }
 
-void RiscVIXor(const Instruction *instruction) {
+void RiscVIXor(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a ^ b; });
 }
 
-void RiscVISll(const Instruction *instruction) {
+void RiscVISll(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a << (b & 0x1f); });
 }
 
-void RiscVISrl(const Instruction *instruction) {
+void RiscVISrl(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >> (b & 0x1f); });
 }
 
-void RiscVISra(const Instruction *instruction) {
+void RiscVISra(const Instruction* instruction) {
   RVCheriotBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >> (b & 0x1f); });
 }
 
 // Load upper immediate. It is assumed that the decoder already shifted the
 // immediate. Operates on 32 bit quantities, not XLEN bits.
-void RiscVILui(const Instruction *instruction) {
+void RiscVILui(const Instruction* instruction) {
   RVCheriotUnaryOp<RegisterType, uint32_t, uint32_t>(
       instruction, [](uint32_t lhs) { return lhs & ~0xfff; });
 }
@@ -121,129 +121,129 @@
 // RiscVIJal and RiscVIJalr are superseded by the capability versions CJal and
 // CJalr.
 
-void RiscVINop(const Instruction *instruction) {}
+void RiscVINop(const Instruction* instruction) {}
 
 // Register width integer types.
 using UIntReg =
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 using IntReg = typename std::make_signed<UIntReg>::type;
 
-void RiscVIBeq(const Instruction *instruction) {
+void RiscVIBeq(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a == b; });
 }
 
-void RiscVIBne(const Instruction *instruction) {
+void RiscVIBne(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a != b; });
 }
 
-void RiscVIBlt(const Instruction *instruction) {
+void RiscVIBlt(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVIBltu(const Instruction *instruction) {
+void RiscVIBltu(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIBge(const Instruction *instruction) {
+void RiscVIBge(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >= b; });
 }
 
-void RiscVIBgeu(const Instruction *instruction) {
+void RiscVIBgeu(const Instruction* instruction) {
   RVCheriotBranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >= b; });
 }
 
-void RiscVILd(const Instruction *instruction) {
+void RiscVILd(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVILw(const Instruction *instruction) {
+void RiscVILw(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILwChild(const Instruction *instruction) {
+void RiscVILwChild(const Instruction* instruction) {
   RVCheriotLoadChild<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILh(const Instruction *instruction) {
+void RiscVILh(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhChild(const Instruction *instruction) {
+void RiscVILhChild(const Instruction* instruction) {
   RVCheriotLoadChild<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhu(const Instruction *instruction) {
+void RiscVILhu(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILhuChild(const Instruction *instruction) {
+void RiscVILhuChild(const Instruction* instruction) {
   RVCheriotLoadChild<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILb(const Instruction *instruction) {
+void RiscVILb(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbChild(const Instruction *instruction) {
+void RiscVILbChild(const Instruction* instruction) {
   RVCheriotLoadChild<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbu(const Instruction *instruction) {
+void RiscVILbu(const Instruction* instruction) {
   RVCheriotLoad<RegisterType, uint8_t>(instruction);
 }
 
-void RiscVILbuChild(const Instruction *instruction) {
+void RiscVILbuChild(const Instruction* instruction) {
   RVCheriotLoadChild<RegisterType, uint8_t>(instruction);
 }
 
-void RiscVISd(const Instruction *instruction) {
+void RiscVISd(const Instruction* instruction) {
   RVCheriotStore<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVISw(const Instruction *instruction) {
+void RiscVISw(const Instruction* instruction) {
   RVCheriotStore<RegisterType, uint32_t>(instruction);
 }
 
-void RiscVISh(const Instruction *instruction) {
+void RiscVISh(const Instruction* instruction) {
   RVCheriotStore<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVISb(const Instruction *instruction) {
+void RiscVISb(const Instruction* instruction) {
   RVCheriotStore<RegisterType, uint8_t>(instruction);
 }
 
-void RiscVIFence(const Instruction *instruction) {
+void RiscVIFence(const Instruction* instruction) {
   uint32_t bits = instruction->Source(0)->AsUint32(0);
   int fm = (bits >> 8) & 0xf;
   int predecessor = (bits >> 4) & 0xf;
   int successor = bits & 0xf;
-  auto *state = static_cast<CheriotState *>(instruction->state());
+  auto* state = static_cast<CheriotState*>(instruction->state());
   state->Fence(instruction, fm, predecessor, successor);
 }
 
-void RiscVIEcall(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void RiscVIEcall(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   state->ECall(instruction);
 }
 
-void RiscVIEbreak(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void RiscVIEbreak(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   state->EBreak(instruction);
 }
 
-void RiscVWFI(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void RiscVWFI(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   state->WFI(instruction);
 }
 
-void RiscVIUnimplemented(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void RiscVIUnimplemented(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   // Get instruction word, as it needs to be used as trap value.
   uint64_t address = instruction->address();
   auto db = state->db_factory()->Allocate<uint32_t>(1);

diff --git a/cheriot/riscv_cheriot_i_instructions.h b/cheriot/riscv_cheriot_i_instructions.h
index d24a61e..f82dc38 100644
--- a/cheriot/riscv_cheriot_i_instructions.h
+++ b/cheriot/riscv_cheriot_i_instructions.h

@@ -33,38 +33,38 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVIllegalInstruction(const Instruction *inst);
+void RiscVIllegalInstruction(const Instruction* inst);
 
 // No operands necessary for Nop. For now, all hint instructions should be
 // decoded as Nop.
-void RiscVINop(const Instruction *instruction);
+void RiscVINop(const Instruction* instruction);
 
 // For the following, source operand 0 refers to the register specified in rs1,
 // and source operand 1 refers to either the register specified in rs2, or the
 // immediate. Destination operand 0 refers to the register specified in rd.
-void RiscVIAdd(const Instruction *instruction);
-void RiscVISub(const Instruction *instruction);
-void RiscVISlt(const Instruction *instruction);
-void RiscVISltu(const Instruction *instruction);
-void RiscVIAnd(const Instruction *instruction);
-void RiscVIOr(const Instruction *instruction);
-void RiscVIXor(const Instruction *instruction);
-void RiscVISll(const Instruction *instruction);
-void RiscVISrl(const Instruction *instruction);
-void RiscVISra(const Instruction *instruction);
+void RiscVIAdd(const Instruction* instruction);
+void RiscVISub(const Instruction* instruction);
+void RiscVISlt(const Instruction* instruction);
+void RiscVISltu(const Instruction* instruction);
+void RiscVIAnd(const Instruction* instruction);
+void RiscVIOr(const Instruction* instruction);
+void RiscVIXor(const Instruction* instruction);
+void RiscVISll(const Instruction* instruction);
+void RiscVISrl(const Instruction* instruction);
+void RiscVISra(const Instruction* instruction);
 // For the following semantic function, source operand 0 refers to the
 // immediate value, and destination 0 the register specified in rd. Note, the
 // value of the immediate shall be properly shifted.
-void RiscVILui(const Instruction *instruction);
+void RiscVILui(const Instruction* instruction);
 // Source operand 0 contains the immediate value. Destination operand 0 refers
 // to the pc destination operand, wheras destination operand 1 refers to the
 // link register specified in rd.
-void RiscVIBeq(const Instruction *instruction);
-void RiscVIBne(const Instruction *instruction);
-void RiscVIBlt(const Instruction *instruction);
-void RiscVIBltu(const Instruction *instruction);
-void RiscVIBge(const Instruction *instruction);
-void RiscVIBgeu(const Instruction *instruction);
+void RiscVIBeq(const Instruction* instruction);
+void RiscVIBne(const Instruction* instruction);
+void RiscVIBlt(const Instruction* instruction);
+void RiscVIBltu(const Instruction* instruction);
+void RiscVIBge(const Instruction* instruction);
+void RiscVIBgeu(const Instruction* instruction);
 // Each of the load instructions are modeled by a pair of semantic instruction
 // functions. The "main" function computes the effective address and initiates
 // the load, the "child" function processes the load result and writes it back
@@ -73,40 +73,40 @@
 // source operand 1 the offset. Destination operand 0 is the register specified
 // by rd. The "child" semantic function will get a copy of the destination
 // operand.
-void RiscVILd(const Instruction *instruction);
-void RiscVILw(const Instruction *instruction);
-void RiscVILwChild(const Instruction *instruction);
-void RiscVILh(const Instruction *instruction);
-void RiscVILhChild(const Instruction *instruction);
-void RiscVILhu(const Instruction *instruction);
-void RiscVILhuChild(const Instruction *instruction);
-void RiscVILb(const Instruction *instruction);
-void RiscVILbChild(const Instruction *instruction);
-void RiscVILbu(const Instruction *instruction);
-void RiscVILbuChild(const Instruction *instruction);
+void RiscVILd(const Instruction* instruction);
+void RiscVILw(const Instruction* instruction);
+void RiscVILwChild(const Instruction* instruction);
+void RiscVILh(const Instruction* instruction);
+void RiscVILhChild(const Instruction* instruction);
+void RiscVILhu(const Instruction* instruction);
+void RiscVILhuChild(const Instruction* instruction);
+void RiscVILb(const Instruction* instruction);
+void RiscVILbChild(const Instruction* instruction);
+void RiscVILbu(const Instruction* instruction);
+void RiscVILbuChild(const Instruction* instruction);
 // For each store instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVISd(const Instruction *instruction);
-void RiscVISw(const Instruction *instruction);
-void RiscVISh(const Instruction *instruction);
-void RiscVISb(const Instruction *instruction);
+void RiscVISd(const Instruction* instruction);
+void RiscVISw(const Instruction* instruction);
+void RiscVISh(const Instruction* instruction);
+void RiscVISb(const Instruction* instruction);
 
 // Unimplemented instruction. This is executed when either the unimp or the
 // c.unimp instructions are issued. The instruction takes an unknown instruction
 // exception, but does not print a log message.
 // The instruction does not take any operands.
-void RiscVIUnimplemented(const Instruction *instruction);
+void RiscVIUnimplemented(const Instruction* instruction);
 // The Fence instruction takes a single source operand (index 0) which consists
 // of an immediate value containing the right justified concatenation of the FM,
 // predecessor, and successor bit fields of the instruction.
-void RiscVIFence(const Instruction *instruction);
+void RiscVIFence(const Instruction* instruction);
 // Ecall and EBreak take no source or destination operands.
-void RiscVIEcall(const Instruction *instruction);
-void RiscVIEbreak(const Instruction *instruction);
+void RiscVIEcall(const Instruction* instruction);
+void RiscVIEbreak(const Instruction* instruction);
 // Trap doesn't implement any specific instruction, but can be called as an
 // instruction, for instance for unknown instructions.
-void RiscVITrap(bool is_interrupt, uint32_t cause, Instruction *instruction);
+void RiscVITrap(bool is_interrupt, uint32_t cause, Instruction* instruction);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_instruction_helpers.h b/cheriot/riscv_cheriot_instruction_helpers.h
index 28fd75a..cd7bffc 100644
--- a/cheriot/riscv_cheriot_instruction_helpers.h
+++ b/cheriot/riscv_cheriot_instruction_helpers.h

@@ -54,17 +54,17 @@
 using PB = ::mpact::sim::cheriot::CheriotRegister::PermissionBits;
 
 // Get the destination capability register.
-static inline CapReg *GetCapDest(const Instruction *instruction, int i) {
-  return static_cast<CapReg *>(
-      std::any_cast<RegisterBase *>(instruction->Destination(i)->GetObject()));
+static inline CapReg* GetCapDest(const Instruction* instruction, int i) {
+  return static_cast<CapReg*>(
+      std::any_cast<RegisterBase*>(instruction->Destination(i)->GetObject()));
 }
 
 // Writing an integer result requires invalidating the capability and setting
 // it to null.
 template <typename Result>
-static inline void WriteCapIntResult(const Instruction *instruction, int i,
+static inline void WriteCapIntResult(const Instruction* instruction, int i,
                                      Result value) {
-  auto *cap_reg = GetCapDest(instruction, i);
+  auto* cap_reg = GetCapDest(instruction, i);
   cap_reg->data_buffer()->Set<Result>(0, value);
   cap_reg->Invalidate();
   cap_reg->set_is_null();
@@ -103,7 +103,7 @@
 // Generic helper function for floating op instructions that do not require
 // NaN boxing since they produce non fp-values, but set fflags.
 template <typename Result, typename From, typename To>
-inline void RVCheriotConvertFloatWithFflagsOp(const Instruction *instruction) {
+inline void RVCheriotConvertFloatWithFflagsOp(const Instruction* instruction) {
   constexpr To kMax = std::numeric_limits<To>::max();
   constexpr To kMin = std::numeric_limits<To>::min();
 
@@ -113,7 +113,7 @@
   uint32_t rm = generic::GetInstructionSource<uint32_t>(instruction, 1);
   // Dynamic rounding mode will get rounding mode from the global state.
   if (rm == *FPRoundingMode::kDynamic) {
-    auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+    auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
     if (!rv_fp->rounding_mode_valid()) {
       LOG(ERROR) << "Invalid rounding mode";
       return;
@@ -135,7 +135,7 @@
     auto constexpr kSigSize = FPTypeInfo<From>::kSigSize;
     auto constexpr kSigMask = FPTypeInfo<From>::kSigMask;
     auto constexpr kBitSize = FPTypeInfo<From>::kBitSize;
-    FromUint lhs_u = *reinterpret_cast<FromUint *>(&lhs);
+    FromUint lhs_u = *reinterpret_cast<FromUint*>(&lhs);
     const bool sign = (lhs_u & (1ULL << (kBitSize - 1))) != 0;
     FromUint exp = kExpMask & lhs_u;
     int exp_value = exp >> kSigSize;
@@ -294,7 +294,7 @@
   Result dest_value = static_cast<Result>(signed_value);
   WriteCapIntResult(instruction, 0, dest_value);
   if (flags) {
-    auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+    auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
     flag_db->Set<uint32_t>(0, flags);
     flag_db->Submit();
   }
@@ -303,7 +303,7 @@
 // Helper function to read a NaN boxed source value, converting it to NaN if
 // it isn't formatted properly.
 template <typename RegValue, typename Argument>
-inline Argument GetNaNBoxedSource(const Instruction *instruction, int arg) {
+inline Argument GetNaNBoxedSource(const Instruction* instruction, int arg) {
   if (sizeof(RegValue) <= sizeof(Argument)) {
     return generic::GetInstructionSource<Argument>(instruction, arg);
   } else {
@@ -313,7 +313,7 @@
     UInt uval = static_cast<UInt>(val);
     UInt mask = std::numeric_limits<UInt>::max() << (sizeof(Argument) * 8);
     if (((mask & uval) != mask)) {
-      return *reinterpret_cast<const Argument *>(
+      return *reinterpret_cast<const Argument*>(
           &FPTypeInfo<Argument>::kCanonicalNaN);
     }
     return generic::GetInstructionSource<Argument>(instruction, arg);
@@ -321,13 +321,13 @@
 }
 
 template <typename Register, typename Result, typename Argument>
-inline void RiscVBinaryOp(const Instruction *instruction,
+inline void RiscVBinaryOp(const Instruction* instruction,
                           std::function<Result(Argument, Argument)> operation) {
   using RegValue = typename Register::ValueType;
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   Argument rhs = generic::GetInstructionSource<Argument>(instruction, 1);
   Result dest_value = operation(lhs, rhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
@@ -338,7 +338,7 @@
 template <typename Register, typename Result, typename Argument1,
           typename Argument2>
 inline void RVCheriotBinaryOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument1, Argument2)> operation) {
   Argument1 lhs = generic::GetInstructionSource<Argument1>(instruction, 0);
   Argument2 rhs = generic::GetInstructionSource<Argument2>(instruction, 1);
@@ -348,7 +348,7 @@
 
 template <typename Register, typename Result, typename Argument>
 inline void RVCheriotBinaryOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument)> operation) {
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   Argument rhs = generic::GetInstructionSource<Argument>(instruction, 1);
@@ -357,7 +357,7 @@
 }
 
 template <typename Register, typename Result>
-inline void RVCheriotBinaryOp(const Instruction *instruction,
+inline void RVCheriotBinaryOp(const Instruction* instruction,
                               std::function<Result(Result, Result)> operation) {
   Result lhs = generic::GetInstructionSource<Result>(instruction, 0);
   Result rhs = generic::GetInstructionSource<Result>(instruction, 1);
@@ -367,7 +367,7 @@
 
 // Generic helper function for unary instructions.
 template <typename Register, typename Result, typename Argument>
-inline void RVCheriotUnaryOp(const Instruction *instruction,
+inline void RVCheriotUnaryOp(const Instruction* instruction,
                              std::function<Result(Argument)> operation) {
   auto lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   Result dest_value = operation(lhs);
@@ -377,7 +377,7 @@
 // Helper function for conditional branches.
 template <typename RegisterType, typename ValueType>
 static inline void RVCheriotBranchConditional(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<bool(ValueType, ValueType)> cond) {
   using UIntType =
       typename std::make_unsigned<typename RegisterType::ValueType>::type;
@@ -386,8 +386,8 @@
   if (cond(a, b)) {
     UIntType offset = generic::GetInstructionSource<UIntType>(instruction, 2);
     UIntType target = offset + instruction->address();
-    auto *state = static_cast<CheriotState *>(instruction->state());
-    auto *pcc = state->pcc();
+    auto* state = static_cast<CheriotState*>(instruction->state());
+    auto* pcc = state->pcc();
     if (!pcc->HasPermission(PB::kPermitExecute)) {
       state->HandleCheriRegException(
           instruction, pcc->address(),
@@ -401,18 +401,18 @@
 
 // Generic helper function for load instructions.
 template <typename Register, typename ValueType>
-inline void RVCheriotLoad(const Instruction *instruction) {
+inline void RVCheriotLoad(const Instruction* instruction) {
   using RegVal = typename Register::ValueType;
   using URegVal = typename std::make_unsigned<RegVal>::type;
   // Bet the capability.
-  auto *cap_reg = static_cast<CheriotRegister *>(
-      static_cast<generic::RegisterSourceOperand<RegVal> *>(
+  auto* cap_reg = static_cast<CheriotRegister*>(
+      static_cast<generic::RegisterSourceOperand<RegVal>*>(
           instruction->Source(0))
           ->GetRegister());
   URegVal base = cap_reg->address();
   RegVal offset = generic::GetInstructionSource<RegVal>(instruction, 1);
   URegVal address = base + offset;
-  auto *state = static_cast<CheriotState *>(instruction->state());
+  auto* state = static_cast<CheriotState*>(instruction->state());
   // Check for tag unset.
   if (!cap_reg->tag()) {
     state->HandleCheriRegException(instruction, instruction->address(),
@@ -439,10 +439,10 @@
                                    cap_reg);
     return;
   }
-  auto *value_db =
+  auto* value_db =
       instruction->state()->db_factory()->Allocate(sizeof(ValueType));
   value_db->set_latency(0);
-  auto *context = new riscv::LoadContext(value_db);
+  auto* context = new riscv::LoadContext(value_db);
   state->LoadMemory(instruction, address, value_db, instruction->child(),
                     context);
   context->DecRef();
@@ -450,12 +450,12 @@
 
 // Generic helper function for load instructions' "child instruction".
 template <typename Register, typename ValueType>
-inline void RVCheriotLoadChild(const Instruction *instruction) {
+inline void RVCheriotLoadChild(const Instruction* instruction) {
   using RegVal = typename Register::ValueType;
   using URegVal = typename std::make_unsigned<RegVal>::type;
   using SRegVal = typename std::make_signed<URegVal>::type;
-  riscv::LoadContext *context =
-      static_cast<riscv::LoadContext *>(instruction->context());
+  riscv::LoadContext* context =
+      static_cast<riscv::LoadContext*>(instruction->context());
   if (std::is_signed<ValueType>::value) {
     SRegVal value = static_cast<SRegVal>(context->value_db->Get<ValueType>(0));
     WriteCapIntResult(instruction, 0, value);
@@ -467,20 +467,20 @@
 
 // Generic helper function for store instructions.
 template <typename RegisterType, typename ValueType>
-inline void RVCheriotStore(const Instruction *instruction) {
+inline void RVCheriotStore(const Instruction* instruction) {
   using URegVal =
       typename std::make_unsigned<typename RegisterType::ValueType>::type;
   using SRegVal = typename std::make_signed<URegVal>::type;
   ValueType value = generic::GetInstructionSource<ValueType>(instruction, 2);
-  auto *cap_reg = static_cast<CheriotRegister *>(
+  auto* cap_reg = static_cast<CheriotRegister*>(
       static_cast<
-          generic::RegisterSourceOperand<typename RegisterType::ValueType> *>(
+          generic::RegisterSourceOperand<typename RegisterType::ValueType>*>(
           instruction->Source(0))
           ->GetRegister());
   URegVal base = cap_reg->address();
   SRegVal offset = generic::GetInstructionSource<SRegVal>(instruction, 1);
   URegVal address = base + offset;
-  auto *state = static_cast<CheriotState *>(instruction->state());
+  auto* state = static_cast<CheriotState*>(instruction->state());
   // Check for tag unset.
   if (!cap_reg->tag()) {
     state->HandleCheriRegException(instruction, instruction->address(),
@@ -507,7 +507,7 @@
                                    cap_reg);
     return;
   }
-  auto *db = state->db_factory()->Allocate(sizeof(ValueType));
+  auto* db = state->db_factory()->Allocate(sizeof(ValueType));
   db->Set<ValueType>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
@@ -518,12 +518,12 @@
 // not really executing an fp operation that requires rounding.
 template <typename RegValue, typename Result, typename Argument>
 inline void RVCheriotBinaryNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<RegValue, Argument>(instruction, 0);
   Argument rhs = GetNaNBoxedSource<RegValue, Argument>(instruction, 1);
   Result dest_value = operation(lhs, rhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -532,7 +532,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<RegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(RegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -545,11 +545,11 @@
 // Generic helper function for unary instructions with NaN boxing.
 template <typename DstRegValue, typename SrcRegValue, typename Result,
           typename Argument>
-inline void RVCheriotUnaryNaNBoxOp(const Instruction *instruction,
+inline void RVCheriotUnaryNaNBoxOp(const Instruction* instruction,
                                    std::function<Result(Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<SrcRegValue, Argument>(instruction, 0);
   Result dest_value = operation(lhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -558,7 +558,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<DstRegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(DstRegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -574,14 +574,14 @@
 template <typename DstRegValue, typename SrcRegValue, typename Result,
           typename Argument>
 inline void RVCheriotUnaryFloatNaNBoxOp(
-    const Instruction *instruction, std::function<Result(Argument)> operation) {
+    const Instruction* instruction, std::function<Result(Argument)> operation) {
   using ResUint = typename FPTypeInfo<Result>::UIntType;
   Argument lhs = GetNaNBoxedSource<SrcRegValue, Argument>(instruction, 0);
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
   // If the rounding mode is dynamic, read it from the current state.
-  auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
       LOG(ERROR) << "Invalid rounding mode";
@@ -595,21 +595,21 @@
     dest_value = operation(lhs);
   }
   if (std::isnan(dest_value) && std::signbit(dest_value)) {
-    ResUint res_value = *reinterpret_cast<ResUint *>(&dest_value);
+    ResUint res_value = *reinterpret_cast<ResUint*>(&dest_value);
     res_value &= FPTypeInfo<Result>::kInfMask;
-    dest_value = *reinterpret_cast<Result *>(&res_value);
+    dest_value = *reinterpret_cast<Result*>(&res_value);
   }
-  auto *dest = instruction->Destination(0);
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* dest = instruction->Destination(0);
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   // Check to see if we need to NaN box the result.
   if (sizeof(DstRegValue) > sizeof(Result)) {
     // If the floating point Value is narrower than the register, the upper
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<DstRegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(DstRegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -622,13 +622,13 @@
 // Generic helper function for floating op instructions that do not require
 // NaN boxing since they produce non fp-values.
 template <typename Result, typename Argument>
-inline void RVCheriotUnaryFloatOp(const Instruction *instruction,
+inline void RVCheriotUnaryFloatOp(const Instruction* instruction,
                                   std::function<Result(Argument)> operation) {
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-  auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -642,11 +642,11 @@
     ScopedFPStatus set_fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(lhs);
   }
-  auto *dest = instruction->Destination(0);
+  auto* dest = instruction->Destination(0);
   using UInt = typename FPTypeInfo<Result>::UIntType;
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<UInt> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<UInt>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
 }
 
@@ -654,13 +654,13 @@
 // NaN boxing since they produce non fp-values, but set fflags.
 template <typename Result, typename Argument>
 inline void RVCheriotUnaryFloatWithFflagsOp(
-    const Instruction *instruction,
-    std::function<Result(Argument, uint32_t &)> operation) {
+    const Instruction* instruction,
+    std::function<Result(Argument, uint32_t&)> operation) {
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-  auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -675,13 +675,13 @@
     ScopedFPStatus set_fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(lhs, flag);
   }
-  auto *dest = instruction->Destination(0);
+  auto* dest = instruction->Destination(0);
   using UInt = typename FPTypeInfo<Result>::UIntType;
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<UInt> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<UInt>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
-  auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, flag);
   flag_db->Submit();
 }
@@ -690,7 +690,7 @@
 // difference is that it handles rounding mode.
 template <typename Register, typename Result, typename Argument>
 inline void RVCheriotBinaryFloatNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<Register, Argument>(instruction, 0);
   Argument rhs = GetNaNBoxedSource<Register, Argument>(instruction, 1);
@@ -700,7 +700,7 @@
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 2);
 
-  auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -715,10 +715,10 @@
     dest_value = operation(lhs, rhs);
   }
   if (std::isnan(dest_value)) {
-    *reinterpret_cast<typename FPTypeInfo<Result>::UIntType *>(&dest_value) =
+    *reinterpret_cast<typename FPTypeInfo<Result>::UIntType*>(&dest_value) =
         FPTypeInfo<Result>::kCanonicalNaN;
   }
-  auto *reg = static_cast<generic::RegisterDestinationOperand<Register> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<Register>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -727,7 +727,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<Register>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(Register) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -740,7 +740,7 @@
 // Generic helper function for ternary floating point instructions.
 template <typename Register, typename Result, typename Argument>
 inline void RVCheriotTernaryFloatNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument, Argument)> operation) {
   Argument rs1 = generic::GetInstructionSource<Argument>(instruction, 0);
   Argument rs2 = generic::GetInstructionSource<Argument>(instruction, 1);
@@ -748,7 +748,7 @@
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 3);
 
-  auto *rv_fp = static_cast<CheriotState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<CheriotState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -762,7 +762,7 @@
     ScopedFPStatus fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(rs1, rs2, rs3);
   }
-  auto *reg = static_cast<generic::RegisterDestinationOperand<Register> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<Register>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -771,7 +771,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<Register>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(Register) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -785,7 +785,7 @@
 template <typename T>
 typename FPTypeInfo<T>::UIntType ClassifyFP(T val) {
   using UIntType = typename FPTypeInfo<T>::UIntType;
-  auto int_value = *reinterpret_cast<UIntType *>(&val);
+  auto int_value = *reinterpret_cast<UIntType*>(&val);
   UIntType sign = int_value >> (FPTypeInfo<T>::kBitSize - 1);
   UIntType exp_mask = (1 << FPTypeInfo<T>::kExpSize) - 1;
   UIntType exp = (int_value >> FPTypeInfo<T>::kSigSize) & exp_mask;

diff --git a/cheriot/riscv_cheriot_instructions.cc b/cheriot/riscv_cheriot_instructions.cc
index 5d4c3ef..aa5f10e 100644
--- a/cheriot/riscv_cheriot_instructions.cc
+++ b/cheriot/riscv_cheriot_instructions.cc

@@ -46,21 +46,21 @@
 using ::mpact::sim::generic::RegisterBase;
 
 // Helpers to get capability register source and destination registers.
-static inline CapReg *GetCapSource(const Instruction *instruction, int i) {
-  return static_cast<CapReg *>(
-      std::any_cast<RegisterBase *>(instruction->Source(i)->GetObject()));
+static inline CapReg* GetCapSource(const Instruction* instruction, int i) {
+  return static_cast<CapReg*>(
+      std::any_cast<RegisterBase*>(instruction->Source(i)->GetObject()));
 }
 
-static inline CapReg *GetCapDest(const Instruction *instruction, int i) {
-  return static_cast<CapReg *>(
-      std::any_cast<RegisterBase *>(instruction->Destination(i)->GetObject()));
+static inline CapReg* GetCapDest(const Instruction* instruction, int i) {
+  return static_cast<CapReg*>(
+      std::any_cast<RegisterBase*>(instruction->Destination(i)->GetObject()));
 }
 // Writing an integer result requires invalidating the capability and setting
 // it to null.
 template <typename Result>
-static inline void WriteCapIntResult(const Instruction *instruction, int i,
+static inline void WriteCapIntResult(const Instruction* instruction, int i,
                                      Result value) {
-  auto *cap_reg = GetCapDest(instruction, i);
+  auto* cap_reg = GetCapDest(instruction, i);
   cap_reg->data_buffer()->Set<Result>(0, value);
   cap_reg->Invalidate();
   cap_reg->set_is_null();
@@ -78,10 +78,10 @@
 
 // Instruction semantic function bodies.
 
-void CheriotAuicap(const Instruction *instruction) {
-  auto *cap_src = GetCapSource(instruction, 0);
+void CheriotAuicap(const Instruction* instruction) {
+  auto* cap_src = GetCapSource(instruction, 0);
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cap_dest = GetCapDest(instruction, 0);
+  auto* cap_dest = GetCapDest(instruction, 0);
   cap_dest->CopyFrom(*cap_src);
   uint32_t address = cap_src->address() + offset;
   cap_dest->data_buffer()->Set<uint32_t>(0, address);
@@ -91,61 +91,61 @@
   if (!cap_dest->IsRepresentable()) cap_dest->Invalidate();
 }
 
-void CheriotCAndPerm(const Instruction *instruction) {
-  auto *cap_src = GetCapSource(instruction, 0);
+void CheriotCAndPerm(const Instruction* instruction) {
+  auto* cap_src = GetCapSource(instruction, 0);
   auto perms = cap_src->permissions();
   auto perms_to_keep = generic::GetInstructionSource<uint32_t>(instruction, 1);
   auto new_perms = perms & perms_to_keep;
-  auto *cap_dest = GetCapDest(instruction, 0);
+  auto* cap_dest = GetCapDest(instruction, 0);
   bool valid = !cap_src->IsSealed();
   cap_dest->CopyFrom(*cap_src);
   cap_dest->ClearPermissions(perms ^ new_perms);
   if (!valid) cap_dest->Invalidate();
 }
 
-void CheriotCClearTag(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cd = GetCapDest(instruction, 0);
+void CheriotCClearTag(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   if (cd != cs1) cd->CopyFrom(*cs1);
   cd->Invalidate();
 }
 
-void CheriotCGetAddr(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetAddr(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   WriteCapIntResult<uint32_t>(instruction, 0, cs1->address());
 }
 
-void CheriotCGetBase(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetBase(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto [base, unused] = cs1->ComputeBounds();
   WriteCapIntResult(instruction, 0, base);
 }
 
-void CheriotCGetHigh(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetHigh(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   WriteCapIntResult<uint32_t>(instruction, 0, cs1->Compress());
 }
 
-void CheriotCGetLen(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetLen(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto [base, top] = cs1->ComputeBounds();
   uint64_t length = top - base;
   if (length == 0x1'0000'0000ULL) length = 0xffff'ffff;
   WriteCapIntResult<uint32_t>(instruction, 0, length);
 }
 
-void CheriotCGetPerm(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetPerm(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   WriteCapIntResult<uint32_t>(instruction, 0, cs1->permissions());
 }
 
-void CheriotCGetTag(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetTag(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   WriteCapIntResult<uint32_t>(instruction, 0, cs1->tag());
 }
 
-void CheriotCGetTop(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetTop(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto [unused, top] = cs1->ComputeBounds();
   // auto top = cs1->top();
   if (top == 0x1'0000'0000ULL) {
@@ -154,8 +154,8 @@
   WriteCapIntResult<uint32_t>(instruction, 0, top);
 }
 
-void CheriotCGetType(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCGetType(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   uint32_t object_type = cs1->object_type();
   object_type &= 0b0111;
   if ((object_type != 0) && (!cs1->HasPermission(CapReg::kPermitExecute))) {
@@ -164,10 +164,10 @@
   WriteCapIntResult<uint32_t>(instruction, 0, object_type);
 }
 
-void CheriotCIncAddr(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCIncAddr(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto inc = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   uint32_t new_addr = cs1->address() + inc;
   bool valid = true;
   if (cs1->IsSealed()) valid = false;
@@ -177,9 +177,9 @@
 }
 
 // Helper function to check for exceptions for Jal and J.
-static bool CheriotCJChecks(const Instruction *instruction, uint64_t new_pc,
-                            const CheriotRegister *pcc) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+static bool CheriotCJChecks(const Instruction* instruction, uint64_t new_pc,
+                            const CheriotRegister* pcc) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   if (!state->has_compact() && (new_pc & 0b10)) {
     state->Trap(/*is_interrupt*/ false, new_pc,
                 *riscv::ExceptionCode::kInstructionAddressMisaligned,
@@ -189,14 +189,14 @@
   return true;
 }
 
-void CheriotCJal(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCJal(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 0);
   uint64_t new_pc = offset + instruction->address();
-  auto *pcc = state->pcc();
+  auto* pcc = state->pcc();
   if (!CheriotCJChecks(instruction, new_pc, pcc)) return;
   // Update link register.
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   cd->CopyFrom(*pcc);
   cd->set_address(instruction->address() + instruction->size());
   bool interrupt_enable = state->mstatus()->mie();
@@ -211,14 +211,14 @@
   state->set_branch(true);
 }
 
-void CheriotCJalCra(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCJalCra(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 0);
   uint64_t new_pc = offset + instruction->address();
-  auto *pcc = state->pcc();
+  auto* pcc = state->pcc();
   if (!CheriotCJChecks(instruction, new_pc, pcc)) return;
   // Update link register.
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   cd->CopyFrom(*pcc);
   cd->set_address(instruction->address() + instruction->size());
   bool interrupt_enable = state->mstatus()->mie();
@@ -230,11 +230,11 @@
   state->set_branch(true);
 }
 
-void CheriotCJ(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCJ(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 0);
   uint64_t new_pc = offset + instruction->address();
-  auto *pcc = state->pcc();
+  auto* pcc = state->pcc();
   if (!CheriotCJChecks(instruction, new_pc, pcc)) return;
   // Update pcc.
   pcc->set_address(new_pc);
@@ -242,10 +242,10 @@
 }
 
 // Helper function to check for exceptions for Jr and Jalr.
-static bool CheriotCJrCheck(const Instruction *instruction, uint64_t new_pc,
-                            uint32_t offset, const CheriotRegister *cs1,
+static bool CheriotCJrCheck(const Instruction* instruction, uint64_t new_pc,
+                            uint32_t offset, const CheriotRegister* cs1,
                             bool has_dest, bool uses_ra) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+  auto* state = static_cast<CheriotState*>(instruction->state());
   if (!cs1->tag()) {
     state->HandleCheriRegException(instruction, instruction->address(),
                                    EC::kCapExTagViolation, cs1);
@@ -280,18 +280,18 @@
   return true;
 }
 
-static inline void CheriotCJalrHelper(const Instruction *instruction,
+static inline void CheriotCJalrHelper(const Instruction* instruction,
                                       bool has_dest, bool uses_ra) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
-  auto *cs1 = GetCapSource(instruction, 0);
+  auto* state = static_cast<CheriotState*>(instruction->state());
+  auto* cs1 = GetCapSource(instruction, 0);
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *pcc = state->pcc();
+  auto* pcc = state->pcc();
   auto new_pc = offset + cs1->address();
   new_pc &= ~0b1ULL;
   if (!CheriotCJrCheck(instruction, new_pc, offset, cs1, has_dest, uses_ra)) {
     return;
   }
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   if (has_dest) {
     // Update link register.
     state->temp_reg()->CopyFrom(*pcc);
@@ -325,38 +325,38 @@
   pcc->set_address(new_pc);
   state->set_branch(true);
   if (has_dest) {
-    auto *cd = GetCapDest(instruction, 0);
+    auto* cd = GetCapDest(instruction, 0);
     cd->CopyFrom(*state->temp_reg());
   }
 }
 
-void CheriotCJalr(const Instruction *instruction) {
+void CheriotCJalr(const Instruction* instruction) {
   CheriotCJalrHelper(instruction, /*has_dest=*/true, /*uses_ra=*/false);
 }
 
-void CheriotCJalrCra(const Instruction *instruction) {
+void CheriotCJalrCra(const Instruction* instruction) {
   CheriotCJalrHelper(instruction, /*has_dest=*/true, /*uses_ra=*/true);
 }
 
-void CheriotCJrCra(const Instruction *instruction) {
+void CheriotCJrCra(const Instruction* instruction) {
   CheriotCJalrHelper(instruction, /*has_dest=*/false, /*uses_ra=*/true);
 }
 
-void CheriotCJr(const Instruction *instruction) {
+void CheriotCJr(const Instruction* instruction) {
   CheriotCJalrHelper(instruction, /*has_dest=*/false, /*uses_ra=*/false);
 }
 
-void CheriotCJalrZero(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCJalrZero(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
+  auto* cs1 = GetCapSource(instruction, 0);
   state->HandleCheriRegException(instruction, instruction->address(),
                                  EC::kCapExTagViolation, cs1);
 }
 
-void CheriotCLc(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCLc(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   auto offset = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cs1 = GetCapSource(instruction, 0);
+  auto* cs1 = GetCapSource(instruction, 0);
   uint32_t address = cs1->address() + offset;
   if (!cs1->tag()) {
     state->HandleCheriRegException(instruction, instruction->address(),
@@ -384,21 +384,20 @@
                 instruction->address(), instruction);
     return;
   }
-  auto *db = state->db_factory()->Allocate(CapReg::kCapabilitySizeInBytes);
+  auto* db = state->db_factory()->Allocate(CapReg::kCapabilitySizeInBytes);
   db->set_latency(0);
-  auto *tag_db = state->db_factory()->Allocate(1);
-  auto *context = new CapabilityLoadContext32(db, tag_db, cs1->permissions(),
+  auto* tag_db = state->db_factory()->Allocate(1);
+  auto* context = new CapabilityLoadContext32(db, tag_db, cs1->permissions(),
                                               /*clear_tag=*/false);
   state->LoadCapability(instruction, address, db, tag_db, instruction->child(),
                         context);
   context->DecRef();
 }
 
-void CheriotCLcChild(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
-  auto *context =
-      static_cast<CapabilityLoadContext32 *>(instruction->context());
-  auto *cd = GetCapDest(instruction, 0);
+void CheriotCLcChild(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
+  auto* context = static_cast<CapabilityLoadContext32*>(instruction->context());
+  auto* cd = GetCapDest(instruction, 0);
   cd->Expand(context->db->Get<uint32_t>(0), context->db->Get<uint32_t>(1),
              context->tag_db->Get<uint8_t>(0));
   // If the source capability did not have load/store capability, invalidate.
@@ -425,9 +424,9 @@
   }
 }
 
-void CheriotCMove(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cd = GetCapDest(instruction, 0);
+void CheriotCMove(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   cd->CopyFrom(*cs1);
 }
 
@@ -439,13 +438,13 @@
   return absl::bit_width(alignment) - 1;
 }
 
-void CheriotCRepresentableAlignmentMask(const Instruction *instruction) {
+void CheriotCRepresentableAlignmentMask(const Instruction* instruction) {
   auto rs1 = generic::GetInstructionSource<uint32_t>(instruction, 0);
   auto exp = GetExponent(rs1);
   WriteCapIntResult<uint32_t>(instruction, 0, 0xffff'ffffU << exp);
 }
 
-void CheriotCRoundRepresentableLength(const Instruction *instruction) {
+void CheriotCRoundRepresentableLength(const Instruction* instruction) {
   auto rs1 = generic::GetInstructionSource<uint32_t>(instruction, 0);
   auto exp = GetExponent(rs1);
   uint32_t mask = (1 << exp) - 1;
@@ -453,10 +452,10 @@
   WriteCapIntResult(instruction, 0, length);
 }
 
-void CheriotCSc(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 2);
+void CheriotCSc(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 2);
   uint32_t imm = generic::GetInstructionSource<uint32_t>(instruction, 1);
   uint32_t address = cs1->address() + imm;
   uint8_t tag = cs2->tag();
@@ -496,8 +495,8 @@
                 instruction->address(), instruction);
     return;
   }
-  auto *db = state->db_factory()->Allocate(CapReg::kCapabilitySizeInBytes);
-  auto *tag_db = state->db_factory()->Allocate(1);
+  auto* db = state->db_factory()->Allocate(CapReg::kCapabilitySizeInBytes);
+  auto* tag_db = state->db_factory()->Allocate(1);
   db->Set<uint32_t>(0, cs2->address());
   db->Set<uint32_t>(1, cs2->Compress());
   tag_db->Set<uint8_t>(0, tag);
@@ -506,10 +505,10 @@
   tag_db->DecRef();
 }
 
-void CheriotCSeal(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+void CheriotCSeal(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 1);
+  auto* cd = GetCapDest(instruction, 0);
   bool valid = true;
   // If cs1 is sealed, invalidate cd.
   if (cs1->IsSealed()) valid = false;
@@ -541,10 +540,10 @@
   if (!permitted || !valid) cd->Invalidate();
 }
 
-void CheriotCSetAddr(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCSetAddr(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto rs2 = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   auto valid = true;
   if (cs1->IsSealed()) valid = false;
   cd->CopyFrom(*cs1);
@@ -552,10 +551,10 @@
   if (!cd->IsRepresentable() || !valid) cd->Invalidate();
 }
 
-void CheriotCSetBounds(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCSetBounds(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto rs2 = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   auto cs1_address = cs1->address();
   bool valid = true;
   // If cs1 is sealed, then invalidate the capability.
@@ -571,10 +570,10 @@
   if (!valid) cd->Invalidate();
 }
 
-void CheriotCSetBoundsExact(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCSetBoundsExact(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto rs2 = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   bool valid = true;
   auto cs1_address = cs1->address();
   // If cs1 is sealed, then invalidate the capability.
@@ -590,26 +589,26 @@
   if (!exact || !valid) cd->Invalidate();
 }
 
-void CheriotCSetEqualExact(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 1);
+void CheriotCSetEqualExact(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 1);
   uint32_t equal =
       (cs1->tag() == cs2->tag()) && (cs1->Compress() == cs2->Compress());
   WriteCapIntResult(instruction, 0, equal);
 }
 
-void CheriotCSetHigh(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
+void CheriotCSetHigh(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
   auto rs2 = generic::GetInstructionSource<uint32_t>(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   cd->Expand(cs1->address(), rs2, false);
 }
 
-void CheriotCSpecialR(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCSpecialR(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   // Decode will ensure that register scr is valid.
-  auto *scr = GetCapSource(instruction, 0);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* scr = GetCapSource(instruction, 0);
+  auto* cd = GetCapDest(instruction, 0);
   if (!state->pcc()->HasPermission(CapReg::kPermitAccessSystemRegisters)) {
     state->HandleCheriRegException(
         instruction, instruction->address(),
@@ -619,19 +618,19 @@
   cd->CopyFrom(*scr);
 }
 
-void CheriotCSpecialRW(const Instruction *instruction) {
-  auto *state = static_cast<CheriotState *>(instruction->state());
+void CheriotCSpecialRW(const Instruction* instruction) {
+  auto* state = static_cast<CheriotState*>(instruction->state());
   // Decode will ensure that register scr is valid.
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *scr = GetCapSource(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* scr = GetCapSource(instruction, 1);
+  auto* cd = GetCapDest(instruction, 0);
   if (!state->pcc()->HasPermission(CapReg::kPermitAccessSystemRegisters)) {
     state->HandleCheriRegException(
         instruction, instruction->address(),
         EC::kCapExPermitAccessSystemRegistersViolation, state->pcc());
     return;
   }
-  auto *temp_reg = state->temp_reg();
+  auto* temp_reg = state->temp_reg();
   temp_reg->CopyFrom(*cs1);
   cd->CopyFrom(*scr);
   // If it's the mepcc register, make sure to clear any lsb.
@@ -655,15 +654,15 @@
   scr->CopyFrom(*state->temp_reg());
 }
 
-void CheriotCSub(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 1);
+void CheriotCSub(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 1);
   WriteCapIntResult(instruction, 0, cs1->address() - cs2->address());
 }
 
-void CheriotCTestSubset(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 1);
+void CheriotCTestSubset(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 1);
   auto [cs1_base, cs1_top] = cs1->ComputeBounds();
   auto [cs2_base, cs2_top] = cs2->ComputeBounds();
   // Verify that cs2 is a subset of cs1.
@@ -676,10 +675,10 @@
   WriteCapIntResult(instruction, 0, static_cast<uint32_t>(result));
 }
 
-void CheriotCUnseal(const Instruction *instruction) {
-  auto *cs1 = GetCapSource(instruction, 0);
-  auto *cs2 = GetCapSource(instruction, 1);
-  auto *cd = GetCapDest(instruction, 0);
+void CheriotCUnseal(const Instruction* instruction) {
+  auto* cs1 = GetCapSource(instruction, 0);
+  auto* cs2 = GetCapSource(instruction, 1);
+  auto* cd = GetCapDest(instruction, 0);
   bool valid = true;
   if (!cs2->tag() || !cs1->IsSealed() || cs2->IsSealed() ||
       (cs2->address() != cs1->object_type()) ||

diff --git a/cheriot/riscv_cheriot_instructions.h b/cheriot/riscv_cheriot_instructions.h
index 8988908..cdd3b66 100644
--- a/cheriot/riscv_cheriot_instructions.h
+++ b/cheriot/riscv_cheriot_instructions.h

@@ -33,123 +33,123 @@
 // This takes 2 source operands and one destination operand. Source 0 is the
 // source capability, source 1 is a pre-scaled immediate. Destination 0 is the
 // target capability.
-void CheriotAuicap(const Instruction *instruction);
+void CheriotAuicap(const Instruction* instruction);
 // This takes 2 sources and 1 destination operand. Source 0 is the source
 // capability, source 1 is an integer register value. Destination 0 is the
 // target capability.
-void CheriotCAndPerm(const Instruction *instruction);
+void CheriotCAndPerm(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is the target capability.
-void CheriotCClearTag(const Instruction *instruction);
+void CheriotCClearTag(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetAddr(const Instruction *instruction);
+void CheriotCGetAddr(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetBase(const Instruction *instruction);
+void CheriotCGetBase(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetHigh(const Instruction *instruction);
+void CheriotCGetHigh(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetLen(const Instruction *instruction);
+void CheriotCGetLen(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetPerm(const Instruction *instruction);
+void CheriotCGetPerm(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetTag(const Instruction *instruction);
+void CheriotCGetTag(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetTop(const Instruction *instruction);
+void CheriotCGetTop(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is an integer register.
-void CheriotCGetType(const Instruction *instruction);
+void CheriotCGetType(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability and source 1 is the integer increment amount. Destination
 // 0 is the target capability.
-void CheriotCIncAddr(const Instruction *instruction);
+void CheriotCIncAddr(const Instruction* instruction);
 // This instruction takes 1 source (an offset), and one destination (the link
 // capability). The pcc is implied.
-void CheriotCJal(const Instruction *instruction);
-void CheriotCJalCra(const Instruction *instruction);
+void CheriotCJal(const Instruction* instruction);
+void CheriotCJalCra(const Instruction* instruction);
 // This instruction takes 1 source (an offset). The pcc is implied.
-void CheriotCJ(const Instruction *instruction);
+void CheriotCJ(const Instruction* instruction);
 // This instruction takes 2 sources and one destination operand. Source 0 is the
 // source capability, source 1 is the offset. Destination 0 is the link
 // capability. The pcc is implied.
-void CheriotCJalr(const Instruction *instruction);
+void CheriotCJalr(const Instruction* instruction);
 // This instruction takes 2 sources. Source 0 is the source capability, source 1
 // is the offset. The pcc is implied.
-void CheriotCJr(const Instruction *instruction);
+void CheriotCJr(const Instruction* instruction);
 // This instruction takes 2 sources and one destination operand. Source 0 is the
 // source capability, source 1 is the offset. Destination 0 is the link
 // capability. The pcc is implied.
-void CheriotCJalrCra(const Instruction *instruction);
+void CheriotCJalrCra(const Instruction* instruction);
 // This instruction takes 2 sources. Source 0 is the source capability, source 1
 // is the offset. The pcc is implied.
-void CheriotCJrCra(const Instruction *instruction);
+void CheriotCJrCra(const Instruction* instruction);
 // This instruction takes no sources, no destinations.
-void CheriotCJalrZero(const Instruction *instruction);
+void CheriotCJalrZero(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // address source capability, source 1 is the integer offset. Destination 0 is
 // the target capability.
-void CheriotCLc(const Instruction *instruction);
+void CheriotCLc(const Instruction* instruction);
 // Child instruction function for CheriotCLc.
-void CheriotCLcChild(const Instruction *instruction);
+void CheriotCLcChild(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is the source
 // capability. Destination 0 is the target capability.
-void CheriotCMove(const Instruction *instruction);
+void CheriotCMove(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is an integer value
 // (address of a capability). Destination 0 is an integer register.
-void CheriotCRepresentableAlignmentMask(const Instruction *instruction);
+void CheriotCRepresentableAlignmentMask(const Instruction* instruction);
 // This takes 1 source and 1 destination operand. Source 0 is an integer value
 // (address of a capability). Destination 0 is an integer register.
-void CheriotCRoundRepresentableLength(const Instruction *instruction);
+void CheriotCRoundRepresentableLength(const Instruction* instruction);
 // This takes 3 source operands. Source 0 is the address source capability,
 // source 1 is the integer offset, and source 2 is the source capability that
 // is stored to memory.
-void CheriotCSc(const Instruction *instruction);
+void CheriotCSc(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is the sealing authority capability. Destination
 // 0 is the target capability.
-void CheriotCSeal(const Instruction *instruction);
+void CheriotCSeal(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is an integer value. Destination 0 is the
 // target capability.
-void CheriotCSetAddr(const Instruction *instruction);
+void CheriotCSetAddr(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is an integer value. Destination 0 is the
 // target capability.
-void CheriotCSetBounds(const Instruction *instruction);
+void CheriotCSetBounds(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is an integer value. Destination 0 is the
 // target capability.
-void CheriotCSetBoundsExact(const Instruction *instruction);
+void CheriotCSetBoundsExact(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Sources 0 and 1
 // are capabilities. Destination 0 is an integer register.
-void CheriotCSetEqualExact(const Instruction *instruction);
+void CheriotCSetEqualExact(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is an integer value. Destination 0 is the
 // target capability.
-void CheriotCSetHigh(const Instruction *instruction);
+void CheriotCSetHigh(const Instruction* instruction);
 // This takes one source and one destination operand. Source 0 is the source
 // special capability CSR. Destination 0 is the target capability.
-void CheriotCSpecialR(const Instruction *instruction);
+void CheriotCSpecialR(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is the special capability CSR. Destination 0
 // is the target capability.
-void CheriotCSpecialRW(const Instruction *instruction);
+void CheriotCSpecialRW(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Sources 0 and 1
 // are capabilities. Destination 0 is an integer register.
-void CheriotCSub(const Instruction *instruction);
+void CheriotCSub(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Sources 0 and 1
 // are capabilities. Destination 0 is an integer register.
-void CheriotCTestSubset(const Instruction *instruction);
+void CheriotCTestSubset(const Instruction* instruction);
 // This takes 2 source operands and 1 destination operand. Source 0 is the
 // source capability, source 1 is the unsealing authority capability.
 // Destination 0 is the target capability.
-void CheriotCUnseal(const Instruction *instruction);
+void CheriotCUnseal(const Instruction* instruction);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_m_instructions.cc b/cheriot/riscv_cheriot_m_instructions.cc
index 50c462c..ca41004 100644
--- a/cheriot/riscv_cheriot_m_instructions.cc
+++ b/cheriot/riscv_cheriot_m_instructions.cc

@@ -33,7 +33,7 @@
 using IntReg = typename std::make_signed<RegType::ValueType>::type;
 using WideIntReg = typename WideType<IntReg>::type;
 
-void MMul(Instruction *instruction) {
+void MMul(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, UintReg, WideIntReg>(
       instruction, [](WideIntReg a_wide, WideIntReg b_wide) {
         WideIntReg c_wide = a_wide * b_wide;
@@ -42,7 +42,7 @@
       });
 }
 
-void MMulh(Instruction *instruction) {
+void MMulh(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, IntReg>(instruction,
                                      [](WideIntReg a_wide, WideIntReg b_wide) {
                                        WideIntReg c_wide = a_wide * b_wide;
@@ -50,7 +50,7 @@
                                      });
 }
 
-void MMulhu(Instruction *instruction) {
+void MMulhu(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, UintReg>(
       instruction, [](WideUintReg a_wide, WideUintReg b_wide) {
         WideUintReg c_wide = a_wide * b_wide;
@@ -58,7 +58,7 @@
       });
 }
 
-void MMulhsu(Instruction *instruction) {
+void MMulhsu(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, UintReg, WideIntReg, WideUintReg>(
       instruction, [](WideIntReg a_wide, WideUintReg b_wide) {
         WideIntReg c_wide = a_wide * b_wide;
@@ -66,7 +66,7 @@
       });
 }
 
-void MDiv(Instruction *instruction) {
+void MDiv(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, IntReg>(
       instruction, [](IntReg a, IntReg b) -> IntReg {
         if (b == 0) return -1;
@@ -77,7 +77,7 @@
       });
 }
 
-void MDivu(Instruction *instruction) {
+void MDivu(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, UintReg>(
       instruction, [](UintReg a, UintReg b) -> UintReg {
         if (b == 0) return std::numeric_limits<UintReg>::max();
@@ -85,7 +85,7 @@
       });
 }
 
-void MRem(Instruction *instruction) {
+void MRem(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, IntReg>(
       instruction, [](IntReg a, IntReg b) -> IntReg {
         if (b == 0) return a;
@@ -96,7 +96,7 @@
       });
 }
 
-void MRemu(Instruction *instruction) {
+void MRemu(Instruction* instruction) {
   RVCheriotBinaryOp<RegType, UintReg>(instruction, [](UintReg a, UintReg b) {
     if (b == 0) return a;
     return a % b;

diff --git a/cheriot/riscv_cheriot_m_instructions.h b/cheriot/riscv_cheriot_m_instructions.h
index 6ddccca..0fbbc2f 100644
--- a/cheriot/riscv_cheriot_m_instructions.h
+++ b/cheriot/riscv_cheriot_m_instructions.h

@@ -28,14 +28,14 @@
 // Each instruction takes rs1 as source operand 0, rs2 as source operand 1,
 // and rd as destination operand 0.
 
-void MMul(Instruction *instruction);
-void MMulh(Instruction *instruction);
-void MMulhu(Instruction *instruction);
-void MMulhsu(Instruction *instruction);
-void MDiv(Instruction *instruction);
-void MDivu(Instruction *instruction);
-void MRem(Instruction *instruction);
-void MRemu(Instruction *instruction);
+void MMul(Instruction* instruction);
+void MMulh(Instruction* instruction);
+void MMulhu(Instruction* instruction);
+void MMulhsu(Instruction* instruction);
+void MDiv(Instruction* instruction);
+void MDivu(Instruction* instruction);
+void MRem(Instruction* instruction);
+void MRemu(Instruction* instruction);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_priv_instructions.cc b/cheriot/riscv_cheriot_priv_instructions.cc
index ee2b29b..9f75450 100644
--- a/cheriot/riscv_cheriot_priv_instructions.cc
+++ b/cheriot/riscv_cheriot_priv_instructions.cc

@@ -26,11 +26,11 @@
 
 using UIntReg = uint32_t;
 
-void RiscVPrivMRet(const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
+void RiscVPrivMRet(const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
   state->pcc()->CopyFrom(*state->mepcc());
   state->set_branch(true);
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   // Set mstatus:mie to the value of mstatus:mpie.
   mstatus->set_mie(mstatus->mpie());
   // Set mstatus:mpie to 1.
@@ -40,9 +40,9 @@
   state->SignalReturnFromInterrupt();
 }
 
-void RiscVPrivWfi(const Instruction *inst) {
+void RiscVPrivWfi(const Instruction* inst) {
   // WFI is treated as a no-op, unless the user sets a callback.
-  auto *state = static_cast<CheriotState *>(inst->state());
+  auto* state = static_cast<CheriotState*>(inst->state());
   state->WFI(inst);
 }
 

diff --git a/cheriot/riscv_cheriot_priv_instructions.h b/cheriot/riscv_cheriot_priv_instructions.h
index c013c1c..9f78aec 100644
--- a/cheriot/riscv_cheriot_priv_instructions.h
+++ b/cheriot/riscv_cheriot_priv_instructions.h

@@ -28,13 +28,13 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVPrivMRet(const Instruction *inst);
+void RiscVPrivMRet(const Instruction* inst);
 
-void RiscVPrivWfi(const Instruction *inst);
-void RiscVPrivSFenceVmaZZ(const Instruction *inst);
-void RiscVPrivSFenceVmaZN(const Instruction *inst);
-void RiscVPrivSFenceVmaNZ(const Instruction *inst);
-void RiscVPrivSFenceVmaNN(const Instruction *inst);
+void RiscVPrivWfi(const Instruction* inst);
+void RiscVPrivSFenceVmaZZ(const Instruction* inst);
+void RiscVPrivSFenceVmaZN(const Instruction* inst);
+void RiscVPrivSFenceVmaNZ(const Instruction* inst);
+void RiscVPrivSFenceVmaNN(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_rvv_encoding.cc b/cheriot/riscv_cheriot_rvv_encoding.cc
index b1b3f3c..80cf314 100644
--- a/cheriot/riscv_cheriot_rvv_encoding.cc
+++ b/cheriot/riscv_cheriot_rvv_encoding.cc

@@ -35,7 +35,7 @@
 
 using Extractors = ::mpact::sim::cheriot::encoding_rvv::Extractors;
 
-RiscVCheriotRVVEncoding::RiscVCheriotRVVEncoding(CheriotState *state)
+RiscVCheriotRVVEncoding::RiscVCheriotRVVEncoding(CheriotState* state)
     : RiscVCheriotEncodingCommon(state) {
   source_op_getters_.emplace(*SourceOpEnum::kNone, []() { return nullptr; });
   dest_op_getters_.emplace(*DestOpEnum::kNone,
@@ -78,7 +78,7 @@
   format_ = format;
 }
 
-DestinationOperandInterface *RiscVCheriotRVVEncoding::GetDestination(
+DestinationOperandInterface* RiscVCheriotRVVEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -92,7 +92,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscVCheriotRVVEncoding::GetSource(
+SourceOperandInterface* RiscVCheriotRVVEncoding::GetSource(
     SlotEnum, int, OpcodeEnum opcode, SourceOpEnum source_op, int source_no) {
   int index = static_cast<int>(source_op);
   auto iter = source_op_getters_.find(index);

diff --git a/cheriot/riscv_cheriot_rvv_encoding.h b/cheriot/riscv_cheriot_rvv_encoding.h
index 1aa0907..9f5652b 100644
--- a/cheriot/riscv_cheriot_rvv_encoding.h
+++ b/cheriot/riscv_cheriot_rvv_encoding.h

@@ -43,11 +43,11 @@
                                 public RiscVCheriotRVVEncodingBase {
  public:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
-  explicit RiscVCheriotRVVEncoding(CheriotState *state);
+  explicit RiscVCheriotRVVEncoding(CheriotState* state);
 
   // Parses an instruction and determines the opcode.
   void ParseInstruction(uint32_t inst_word);
@@ -62,19 +62,19 @@
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
   // Currently no resources modeled for RiscV CHERIoT.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override {
     return nullptr;
@@ -82,12 +82,12 @@
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -97,8 +97,8 @@
     return 0;
   }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
 
  private:
   SourceOpGetterMap source_op_getters_;

diff --git a/cheriot/riscv_cheriot_rvv_fp_encoding.cc b/cheriot/riscv_cheriot_rvv_fp_encoding.cc
index c7f3930..3523a3b 100644
--- a/cheriot/riscv_cheriot_rvv_fp_encoding.cc
+++ b/cheriot/riscv_cheriot_rvv_fp_encoding.cc

@@ -37,7 +37,7 @@
 
 using Extractors = ::mpact::sim::cheriot::encoding_rvv_fp::Extractors;
 
-RiscVCheriotRVVFPEncoding::RiscVCheriotRVVFPEncoding(CheriotState *state)
+RiscVCheriotRVVFPEncoding::RiscVCheriotRVVFPEncoding(CheriotState* state)
     : RiscVCheriotEncodingCommon(state) {
   source_op_getters_.emplace(*SourceOpEnum::kNone, []() { return nullptr; });
   dest_op_getters_.emplace(*DestOpEnum::kNone,
@@ -87,7 +87,7 @@
   format_ = format;
 }
 
-DestinationOperandInterface *RiscVCheriotRVVFPEncoding::GetDestination(
+DestinationOperandInterface* RiscVCheriotRVVFPEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -101,7 +101,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscVCheriotRVVFPEncoding::GetSource(
+SourceOperandInterface* RiscVCheriotRVVFPEncoding::GetSource(
     SlotEnum, int, OpcodeEnum opcode, SourceOpEnum source_op, int source_no) {
   int index = static_cast<int>(source_op);
   auto iter = source_op_getters_.find(index);

diff --git a/cheriot/riscv_cheriot_rvv_fp_encoding.h b/cheriot/riscv_cheriot_rvv_fp_encoding.h
index 7f52735..34f740f 100644
--- a/cheriot/riscv_cheriot_rvv_fp_encoding.h
+++ b/cheriot/riscv_cheriot_rvv_fp_encoding.h

@@ -42,7 +42,7 @@
 class RiscVCheriotRVVFPEncoding : public RiscVCheriotEncodingCommon,
                                   public RiscVCheriotRVVFpEncodingBase {
  public:
-  explicit RiscVCheriotRVVFPEncoding(CheriotState *state);
+  explicit RiscVCheriotRVVFPEncoding(CheriotState* state);
 
   // Parses an instruction and determines the opcode.
   void ParseInstruction(uint32_t inst_word);
@@ -57,19 +57,19 @@
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
   // Currently no resources modeled for RiscV CHERIoT.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override {
     return nullptr;
@@ -77,12 +77,12 @@
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -94,9 +94,9 @@
 
  private:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 
   SourceOpGetterMap source_op_getters_;
   DestOpGetterMap dest_op_getters_;

diff --git a/cheriot/riscv_cheriot_vector_fp_compare_instructions.cc b/cheriot/riscv_cheriot_vector_fp_compare_instructions.cc
index 2747d7b..234a367 100644
--- a/cheriot/riscv_cheriot_vector_fp_compare_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_fp_compare_instructions.cc

@@ -24,8 +24,8 @@
 namespace cheriot {
 
 // Vector floating point compare equal.
-void Vmfeq(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmfeq(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -44,8 +44,8 @@
 }
 
 // Vector floating point compare less than or equal.
-void Vmfle(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmfle(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -64,8 +64,8 @@
 }
 
 // Vector floating compare less than.
-void Vmflt(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmflt(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -84,8 +84,8 @@
 }
 
 // Vector floating point compare not equal.
-void Vmfne(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmfne(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -104,8 +104,8 @@
 }
 
 // Vector floating point compare greater than.
-void Vmfgt(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmfgt(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -124,8 +124,8 @@
 }
 
 // Vector floating point compare greater than or equal.
-void Vmfge(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmfge(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:

diff --git a/cheriot/riscv_cheriot_vector_fp_compare_instructions.h b/cheriot/riscv_cheriot_vector_fp_compare_instructions.h
index 9b5f83e..e398b96 100644
--- a/cheriot/riscv_cheriot_vector_fp_compare_instructions.h
+++ b/cheriot/riscv_cheriot_vector_fp_compare_instructions.h

@@ -31,12 +31,12 @@
 // Vmfge only take the scalar register), source operand 2 is the vector mask
 // register. Destination operand 0 is a vector register treated as the
 // destination mask register.
-void Vmfeq(const Instruction *inst);
-void Vmfle(const Instruction *inst);
-void Vmflt(const Instruction *inst);
-void Vmfne(const Instruction *inst);
-void Vmfgt(const Instruction *inst);
-void Vmfge(const Instruction *inst);
+void Vmfeq(const Instruction* inst);
+void Vmfle(const Instruction* inst);
+void Vmflt(const Instruction* inst);
+void Vmfne(const Instruction* inst);
+void Vmfgt(const Instruction* inst);
+void Vmfge(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_fp_instructions.cc b/cheriot/riscv_cheriot_vector_fp_instructions.cc
index e4d92fa..87d6c48 100644
--- a/cheriot/riscv_cheriot_vector_fp_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_fp_instructions.cc

@@ -26,7 +26,6 @@
 #include "riscv//riscv_fp_host.h"
 #include "riscv//riscv_fp_info.h"
 #include "riscv//riscv_fp_state.h"
-#include "riscv//riscv_vector_state.h"
 
 namespace mpact {
 namespace sim {
@@ -37,9 +36,9 @@
 using ::mpact::sim::riscv::ScopedFPStatus;
 
 // Floating point add.
-void Vfadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -64,9 +63,9 @@
 }
 
 // Floating point subtract.
-void Vfsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -91,9 +90,9 @@
 }
 
 // Reverse floating point subtract (rs1 - vs2).
-void Vfrsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfrsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -118,9 +117,9 @@
 }
 
 // Widening floating point add.
-void Vfwadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -144,9 +143,9 @@
 }
 
 // Widening floating point subtract.
-void Vfwsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -170,9 +169,9 @@
 }
 
 // Widening floating point add with wide operand (vs2).
-void Vfwaddw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwaddw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -195,9 +194,9 @@
 }
 
 // Widening floating point subtract with wide operand (vs2).
-void Vfwsubw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwsubw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -220,9 +219,9 @@
 }
 
 // Floating point multiply.
-void Vfmul(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmul(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -247,9 +246,9 @@
 }
 
 // Floating point division vs2/vs1;
-void Vfdiv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfdiv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -274,9 +273,9 @@
 }
 
 // Floating point reverse division vs1/vs2.
-void Vfrdiv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfrdiv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -301,9 +300,9 @@
 }
 
 // Widening floating point multiply.
-void Vfwmul(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwmul(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -327,9 +326,9 @@
 }
 
 // Floating point multiply and add vs2.
-void Vfmadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -356,9 +355,9 @@
 }
 
 // Negated floating point multiply and add vs2.
-void Vfnmadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfnmadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -385,9 +384,9 @@
 }
 
 // Floating point multiply and subtract vs2.
-void Vfmsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -414,9 +413,9 @@
 }
 
 // Negated floating point multiply and subtract vs2.
-void Vfnmsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfnmsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -443,9 +442,9 @@
 }
 
 // Floating point multiply and accumulate vd.
-void Vfmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -472,9 +471,9 @@
 }
 
 // Negated floating point multiply and accumulate vd.
-void Vfnmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfnmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -501,9 +500,9 @@
 }
 
 // Floating point multiply and subtract vd.
-void Vfmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -530,9 +529,9 @@
 }
 
 // Negated floating point multiply and subtract vd.
-void Vfnmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfnmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -559,9 +558,9 @@
 }
 
 // Widening floating point multiply and accumulate vd.
-void Vfwmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -585,9 +584,9 @@
 }
 
 // Widening negated floating point multiply and accumulate vd.
-void Vfwnmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwnmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -611,9 +610,9 @@
 }
 
 // Widening floating point multiply and subtract vd.
-void Vfwmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -637,9 +636,9 @@
 }
 
 // Widening negated floating point multiply and subtract vd.
-void Vfwnmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwnmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -663,8 +662,8 @@
 }
 
 // Change the sign of vs2 to the sign of vs1.
-void Vfsgnj(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfsgnj(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -686,8 +685,8 @@
 }
 
 // Change the sign of vs2 to the negation of the sign of vs1.
-void Vfsgnjn(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfsgnjn(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -709,8 +708,8 @@
 }
 
 // Change the sign of vs2 to the xor of the sign of the two operands.
-void Vfsgnjx(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfsgnjx(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -743,7 +742,7 @@
   }
   if (FPTypeInfo<T>::IsNaN(vs2) && FPTypeInfo<T>::IsNaN(vs1)) {
     auto c_nan = FPTypeInfo<T>::kCanonicalNaN;
-    return std::make_tuple(*reinterpret_cast<T *>(&c_nan), flag);
+    return std::make_tuple(*reinterpret_cast<T*>(&c_nan), flag);
   }
   // If either operand is a NaN return the other.
   if (FPTypeInfo<T>::IsNaN(vs2)) return std::tie(vs1, flag);
@@ -758,8 +757,8 @@
 }
 
 // Vector floating point min.
-void Vfmin(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmin(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -788,8 +787,8 @@
 }
 
 // Vector floating point max.
-void Vfmax(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmax(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -818,8 +817,8 @@
 }
 
 // Vector fp merge.
-void Vfmerge(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmerge(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:

diff --git a/cheriot/riscv_cheriot_vector_fp_instructions.h b/cheriot/riscv_cheriot_vector_fp_instructions.h
index 46d56b5..3ed636c 100644
--- a/cheriot/riscv_cheriot_vector_fp_instructions.h
+++ b/cheriot/riscv_cheriot_vector_fp_instructions.h

@@ -31,52 +31,52 @@
 // register group, source 1 is either a vector register group or a scalar
 // register, and source 2 is the mask register. Destination 0 is a vector
 // register group.
-void Vfadd(const Instruction *inst);
-void Vfsub(const Instruction *inst);
-void Vfrsub(const Instruction *inst);
-void Vfwadd(const Instruction *inst);
-void Vfwsub(const Instruction *inst);
-void Vfwaddw(const Instruction *inst);
-void Vfwsubw(const Instruction *inst);
-void Vfmul(const Instruction *inst);
-void Vfdiv(const Instruction *inst);
-void Vfrdiv(const Instruction *inst);
-void Vfwmul(const Instruction *inst);
+void Vfadd(const Instruction* inst);
+void Vfsub(const Instruction* inst);
+void Vfrsub(const Instruction* inst);
+void Vfwadd(const Instruction* inst);
+void Vfwsub(const Instruction* inst);
+void Vfwaddw(const Instruction* inst);
+void Vfwsubw(const Instruction* inst);
+void Vfmul(const Instruction* inst);
+void Vfdiv(const Instruction* inst);
+void Vfrdiv(const Instruction* inst);
+void Vfwmul(const Instruction* inst);
 
 // Vector floating point multiply and add/subtract instructions. Each of these
 // instructions take four source operands and one destination operand. Source 0
 // is a vector register group, source 1 is either a vector register group or a
 // scalar register, source 2 is a vector register group, and source 3 is the
 // mask register. Destination 0 is a vector register group.
-void Vfmadd(const Instruction *inst);
-void Vfnmadd(const Instruction *inst);
-void Vfmsub(const Instruction *inst);
-void Vfnmsub(const Instruction *inst);
-void Vfmacc(const Instruction *inst);
-void Vfnmacc(const Instruction *inst);
-void Vfmsac(const Instruction *inst);
-void Vfnmsac(const Instruction *inst);
-void Vfwmacc(const Instruction *inst);
-void Vfwnmacc(const Instruction *inst);
-void Vfwmsac(const Instruction *inst);
-void Vfwnmsac(const Instruction *inst);
+void Vfmadd(const Instruction* inst);
+void Vfnmadd(const Instruction* inst);
+void Vfmsub(const Instruction* inst);
+void Vfnmsub(const Instruction* inst);
+void Vfmacc(const Instruction* inst);
+void Vfnmacc(const Instruction* inst);
+void Vfmsac(const Instruction* inst);
+void Vfnmsac(const Instruction* inst);
+void Vfwmacc(const Instruction* inst);
+void Vfwnmacc(const Instruction* inst);
+void Vfwmsac(const Instruction* inst);
+void Vfwnmsac(const Instruction* inst);
 
 // Vector floating point sign modification instructions. Each of these
 // instructions take three source operands and one destination operand. Source 0
 // is a vector register group, source 1 is either a vector register group or a
 // scalar register, and source 2 is the mask register. Destination 0 is a vector
 // register group.
-void Vfsgnj(const Instruction *inst);
-void Vfsgnjn(const Instruction *inst);
-void Vfsgnjx(const Instruction *inst);
+void Vfsgnj(const Instruction* inst);
+void Vfsgnjn(const Instruction* inst);
+void Vfsgnjx(const Instruction* inst);
 
 // Vector selection instructions. Each of these instructions take three source
 // operands and one destination operand. Source 0 is a vector register group,
 // source 1 is either a vector register group or a scalar register, and source 2
 // is the mask register. Destination 0 is a vector register group.
-void Vfmin(const Instruction *inst);
-void Vfmax(const Instruction *inst);
-void Vfmerge(const Instruction *inst);
+void Vfmin(const Instruction* inst);
+void Vfmax(const Instruction* inst);
+void Vfmerge(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_fp_reduction_instructions.cc b/cheriot/riscv_cheriot_vector_fp_reduction_instructions.cc
index cf72616..09dad44 100644
--- a/cheriot/riscv_cheriot_vector_fp_reduction_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_fp_reduction_instructions.cc

@@ -22,7 +22,6 @@
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv//riscv_fp_host.h"
 #include "riscv//riscv_fp_state.h"
-#include "riscv//riscv_vector_state.h"
 
 namespace mpact {
 namespace sim {
@@ -36,9 +35,9 @@
 // separate entry in the destination vector.
 
 // Sum reduction.
-void Vfredosum(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfredosum(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -64,9 +63,9 @@
   }
 }
 
-void Vfwredosum(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwredosum(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -96,7 +95,7 @@
   if (FPTypeInfo<T>::IsSNaN(vs1) || FPTypeInfo<T>::IsSNaN(vs2) ||
       (FPTypeInfo<T>::IsNaN(vs2) && FPTypeInfo<T>::IsNaN(vs1))) {
     typename FPTypeInfo<T>::UIntType c_nan = FPTypeInfo<T>::kCanonicalNaN;
-    return *reinterpret_cast<T *>(&c_nan);
+    return *reinterpret_cast<T*>(&c_nan);
   }
   // If either operand is a NaN return the other.
   if (FPTypeInfo<T>::IsNaN(vs2)) return vs1;
@@ -106,9 +105,9 @@
 }
 
 // FP min reduction.
-void Vfredmin(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfredmin(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -142,9 +141,9 @@
 }
 
 // FP max reduction.
-void Vfredmax(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfredmax(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();

diff --git a/cheriot/riscv_cheriot_vector_fp_reduction_instructions.h b/cheriot/riscv_cheriot_vector_fp_reduction_instructions.h
index bfb4b6c..ab64e79 100644
--- a/cheriot/riscv_cheriot_vector_fp_reduction_instructions.h
+++ b/cheriot/riscv_cheriot_vector_fp_reduction_instructions.h

@@ -30,10 +30,10 @@
 // destination operand. Source 0 is a vector register group, source 1 is a
 // vector register, and source 2 is the vector mask register. Destination
 // operand 0 is a vector register group.
-void Vfredosum(const Instruction *inst);
-void Vfwredosum(const Instruction *inst);
-void Vfredmin(const Instruction *inst);
-void Vfredmax(const Instruction *inst);
+void Vfredosum(const Instruction* inst);
+void Vfwredosum(const Instruction* inst);
+void Vfredmin(const Instruction* inst);
+void Vfredmax(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_fp_unary_instructions.cc b/cheriot/riscv_cheriot_vector_fp_unary_instructions.cc
index 06db4e3..c855394 100644
--- a/cheriot/riscv_cheriot_vector_fp_unary_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_fp_unary_instructions.cc

@@ -28,7 +28,6 @@
 #include "riscv//riscv_fp_host.h"
 #include "riscv//riscv_fp_info.h"
 #include "riscv//riscv_fp_state.h"
-#include "riscv//riscv_vector_state.h"
 
 namespace mpact {
 namespace sim {
@@ -64,15 +63,15 @@
     4,   3,   3,   2,   2,   1,   1,   0};
 
 // Move float from scalar fp register to vector register(all elements).
-void Vfmvvf(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmvvf(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   const int vl = rv_vector->vector_length();
   if (rv_vector->vstart() > 0) return;
   if (vl == 0) return;
 
   const int sew = rv_vector->selected_element_width();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   switch (sew) {
     case 4:
@@ -98,13 +97,13 @@
 }
 
 // Move float from vector to scalar fp register(first element).
-void Vfmvsf(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmvsf(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart() > 0) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   switch (sew) {
     case 4:
@@ -126,8 +125,8 @@
 }
 
 // Move scalar floating point value to element 0 of vector register.
-void Vfmvfs(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfmvfs(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto dest_op = inst->Destination(0);
   auto dest_db = dest_op->AllocateDataBuffer();
@@ -160,9 +159,9 @@
 }
 
 // Convert floating point to unsigned integer.
-void Vfcvtxufv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfcvtxufv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -188,9 +187,9 @@
 }
 
 // Convert floating point to signed integer.
-void Vfcvtxfv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfcvtxfv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -216,9 +215,9 @@
 }
 
 // Convert unsigned integer to floating point.
-void Vfcvtfxuv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfcvtfxuv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -243,9 +242,9 @@
 }
 
 // Convert signed integer to floating point.
-void Vfcvtfxv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfcvtfxv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -270,9 +269,9 @@
 }
 
 // Convert floating point to unsigned integer with truncation.
-void Vfcvtrtzxufv(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfcvtrtzxufv(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -293,9 +292,9 @@
 }
 
 // Convert floating point to signed integer with truncation.
-void Vfcvtrtzxfv(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfcvtrtzxfv(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -316,9 +315,9 @@
 }
 
 // Widening conversion of floating point to unsigned integer.
-void Vfwcvtxufv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwcvtxufv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -339,9 +338,9 @@
 }
 
 // Widening conversion of floating point to signed integer.
-void Vfwcvtxfv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwcvtxfv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -362,8 +361,8 @@
 }
 
 // Wideing conversion of floating point to floating point.
-void Vfwcvtffv(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwcvtffv(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -378,9 +377,9 @@
 }
 
 // Widening conversion of unsigned integer to floating point.
-void Vfwcvtfxuv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwcvtfxuv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -405,9 +404,9 @@
 }
 
 // Widening conversion of signed integer to floating point.
-void Vfwcvtfxv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfwcvtfxv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -432,9 +431,9 @@
 }
 
 // Widening conversion of floating point to unsigned integer with truncation.
-void Vfwcvtrtzxufv(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfwcvtrtzxufv(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -450,9 +449,9 @@
 }
 
 // Widening conversion of floating point to signed integer with truncation.
-void Vfwcvtrtzxfv(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfwcvtrtzxfv(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -468,9 +467,9 @@
 }
 
 // Narrowing conversion of floating point to unsigned integer.
-void Vfncvtxufw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtxufw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -496,9 +495,9 @@
 }
 
 // Narrowing conversion of floating point to signed integer.
-void Vfncvtxfw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtxfw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -524,9 +523,9 @@
 }
 
 // Narrowing conversion of floating point to floating point.
-void Vfncvtffw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtffw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -547,9 +546,9 @@
 }
 
 // Narrowing conversion of floating point to floating point rounding to odd.
-void Vfncvtrodffw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtrodffw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -569,16 +568,16 @@
             }
             using UIntD = typename FPTypeInfo<double>::UIntType;
             using UIntF = typename FPTypeInfo<float>::UIntType;
-            UIntD uval = *reinterpret_cast<UIntD *>(&vs2);
+            UIntD uval = *reinterpret_cast<UIntD*>(&vs2);
             int sig_diff =
                 FPTypeInfo<double>::kSigSize - FPTypeInfo<float>::kSigSize;
             UIntD mask = (1ULL << sig_diff) - 1;
             UIntF bit = (mask & uval) != 0;
             auto res = static_cast<float>(vs2);
             if (FPTypeInfo<float>::IsInf(res)) return res;
-            UIntF ures = *reinterpret_cast<UIntF *>(&res);
+            UIntF ures = *reinterpret_cast<UIntF*>(&res);
             ures |= bit;
-            return *reinterpret_cast<float *>(&ures);
+            return *reinterpret_cast<float*>(&ures);
           });
     default:
       LOG(ERROR) << "Vfwcvt.rod.f.fw: Illegal sew (" << sew << ")";
@@ -588,9 +587,9 @@
 }
 
 // Narrowing conversion of unsigned integer to floating point.
-void Vfncvtfxuw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtfxuw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -611,9 +610,9 @@
 }
 
 // Narrowing conversion of signed integeer to floating point.
-void Vfncvtfxw(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfncvtfxw(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -634,9 +633,9 @@
 }
 
 // Narrowing conversion of floating point to unsigned integer with truncation.
-void Vfncvtrtzxufw(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfncvtrtzxufw(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -657,9 +656,9 @@
 }
 
 // Narrowing conversion of floating point to signed integer with truncation.
-void Vfncvtrtzxfw(const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfncvtrtzxfw(const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -686,7 +685,7 @@
   T res;
   if (FPTypeInfo<T>::IsNaN(vs2) || vs2 < 0.0) {
     auto value = FPTypeInfo<T>::kCanonicalNaN;
-    res = *reinterpret_cast<T *>(&value);
+    res = *reinterpret_cast<T*>(&value);
     flags = *FPExceptions::kInvalidOp;
     return std::tie(res, flags);
   }
@@ -696,9 +695,9 @@
 }
 
 // Square root.
-void Vfsqrtv(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfsqrtv(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -731,7 +730,7 @@
         return;
     }
   }
-  auto *fflags = rv_fp->fflags();
+  auto* fflags = rv_fp->fflags();
   fflags->Write(flags | fflags->AsUint32());
 }
 
@@ -740,7 +739,7 @@
 template <typename T>
 inline T RecipSqrt7(T value) {
   using Uint = typename FPTypeInfo<T>::UIntType;
-  Uint uint_value = *reinterpret_cast<Uint *>(&value);
+  Uint uint_value = *reinterpret_cast<Uint*>(&value);
   // The input value is positive. Negative values are already handled.
   int norm_exponent =
       (uint_value & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
@@ -763,7 +762,7 @@
                       << (FPTypeInfo<T>::kSigSize - 7);
   Uint new_exponent = (3 * FPTypeInfo<T>::kExpBias - 1 - norm_exponent) / 2;
   Uint new_value = (new_exponent << FPTypeInfo<T>::kSigSize) | new_mantissa;
-  T new_fp_value = *reinterpret_cast<T *>(&new_value);
+  T new_fp_value = *reinterpret_cast<T*>(&new_value);
   return new_fp_value;
 }
 
@@ -807,9 +806,9 @@
 }
 
 // Approximation of reciprocal square root to 7 bits mantissa.
-void Vfrsqrt7v(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfrsqrt7v(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -837,7 +836,7 @@
 inline T Recip7(T value, FPRoundingMode rm) {
   using Uint = typename FPTypeInfo<T>::UIntType;
   using Int = typename FPTypeInfo<T>::IntType;
-  Uint uint_value = *reinterpret_cast<Uint *>(&value);
+  Uint uint_value = *reinterpret_cast<Uint*>(&value);
   Int norm_exponent =
       (uint_value & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
   Uint norm_mantissa = uint_value & FPTypeInfo<T>::kSigMask;
@@ -891,7 +890,7 @@
     new_mantissa &= 0b111'1111;
   }
   Uint new_value = (new_exponent << FPTypeInfo<T>::kSigSize) | new_mantissa;
-  T new_fp_value = *reinterpret_cast<T *>(&new_value);
+  T new_fp_value = *reinterpret_cast<T*>(&new_value);
   return value < 0.0 ? -new_fp_value : new_fp_value;
 }
 
@@ -919,9 +918,9 @@
 }
 
 // Approximate reciprocal to 7 bits of mantissa.
-void Vfrec7v(const Instruction *inst) {
-  auto *rv_fp = static_cast<CheriotState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfrec7v(const Instruction* inst) {
+  auto* rv_fp = static_cast<CheriotState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   ScopedFPStatus set_fpstatus(rv_fp->host_fp_interface());
   auto rm = rv_fp->GetRoundingMode();
@@ -942,8 +941,8 @@
 }
 
 // Classify floating point value.
-void Vfclassv(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfclassv(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:

diff --git a/cheriot/riscv_cheriot_vector_fp_unary_instructions.h b/cheriot/riscv_cheriot_vector_fp_unary_instructions.h
index ad607d3..31d2c9f 100644
--- a/cheriot/riscv_cheriot_vector_fp_unary_instructions.h
+++ b/cheriot/riscv_cheriot_vector_fp_unary_instructions.h

@@ -27,11 +27,11 @@
 using Instruction = ::mpact::sim::generic::Instruction;
 
 // Move a single floating point value from vector[0] to vector[vl-1].
-void Vfmvvf(const Instruction *inst);
+void Vfmvvf(const Instruction* inst);
 // Move a single floating point value from vector[0] to scalar fp register.
-void Vfmvsf(const Instruction *inst);
+void Vfmvsf(const Instruction* inst);
 // Move single floating point value from scalar fp register to vector[0].
-void Vfmvfs(const Instruction *inst);
+void Vfmvfs(const Instruction* inst);
 
 // Each of the following semantic functions take 2 source operands and 1
 // destination operand. Source operand 0 is a vector register group, source
@@ -44,17 +44,17 @@
 // rounding mode.
 
 // FP to unsigned integer.
-void Vfcvtxufv(const Instruction *inst);
+void Vfcvtxufv(const Instruction* inst);
 // FP to signed integer.
-void Vfcvtxfv(const Instruction *inst);
+void Vfcvtxfv(const Instruction* inst);
 // Unsigned integer to FP.
-void Vfcvtfxuv(const Instruction *inst);
+void Vfcvtfxuv(const Instruction* inst);
 // Signed integer to FP.
-void Vfcvtfxv(const Instruction *inst);
+void Vfcvtfxv(const Instruction* inst);
 // FP to unsigned integer using round to zero.
-void Vfcvtrtzxufv(const Instruction *inst);
+void Vfcvtrtzxufv(const Instruction* inst);
 // FP to signed integer using round to zero.
-void Vfcvtrtzxfv(const Instruction *inst);
+void Vfcvtrtzxfv(const Instruction* inst);
 
 // Vector element widening conversion instructions. These convert values from/to
 // signed/unsigned integer and floating point, where the resulting value is 2x
@@ -62,19 +62,19 @@
 // zero), whereas the others use the dynamically set rounding mode.
 
 // FP to wider unsigned integer.
-void Vfwcvtxufv(const Instruction *inst);
+void Vfwcvtxufv(const Instruction* inst);
 // FP to wider signed integer.
-void Vfwcvtxfv(const Instruction *inst);
+void Vfwcvtxfv(const Instruction* inst);
 // FP to next wider FP.
-void Vfwcvtffv(const Instruction *inst);
+void Vfwcvtffv(const Instruction* inst);
 // Unsigned integer to wider FP.
-void Vfwcvtfxuv(const Instruction *inst);
+void Vfwcvtfxuv(const Instruction* inst);
 // Signed integer to wider FP.
-void Vfwcvtfxv(const Instruction *inst);
+void Vfwcvtfxv(const Instruction* inst);
 // FP to wider unsigned integer using round to zero.
-void Vfwcvtrtzxufv(const Instruction *inst);
+void Vfwcvtrtzxufv(const Instruction* inst);
 // FP to wider signed integer using round to zero.
-void Vfwcvtrtzxfv(const Instruction *inst);
+void Vfwcvtrtzxfv(const Instruction* inst);
 
 // Vector element widening conversion instructions. These convert values from/to
 // signed/unsigned integer and floating point, where the resulting value is 1/2x
@@ -83,30 +83,30 @@
 // dynamically set rounding mode.
 
 // FP to narrower unsigned integer.
-void Vfncvtxufw(const Instruction *inst);
+void Vfncvtxufw(const Instruction* inst);
 // FP to narrower signed integer.
-void Vfncvtxfw(const Instruction *inst);
+void Vfncvtxfw(const Instruction* inst);
 // FP to next narrower FP.
-void Vfncvtffw(const Instruction *inst);
+void Vfncvtffw(const Instruction* inst);
 // FP to next narrower FP with round to odd.
-void Vfncvtrodffw(const Instruction *inst);
+void Vfncvtrodffw(const Instruction* inst);
 // Unsigned integer to narrower FP.
-void Vfncvtfxuw(const Instruction *inst);
+void Vfncvtfxuw(const Instruction* inst);
 // Signed integer to narrower FP.
-void Vfncvtfxw(const Instruction *inst);
+void Vfncvtfxw(const Instruction* inst);
 // FP to narrower unsigned integer using round to zero.
-void Vfncvtrtzxufw(const Instruction *inst);
+void Vfncvtrtzxufw(const Instruction* inst);
 // FP to narrower signed integer using round to zero.
-void Vfncvtrtzxfw(const Instruction *inst);
+void Vfncvtrtzxfw(const Instruction* inst);
 
 // Vector element square root instruction.
-void Vfsqrtv(const Instruction *inst);
+void Vfsqrtv(const Instruction* inst);
 // Vector element approximate reciprocal square root instruction.
-void Vfrsqrt7v(const Instruction *inst);
+void Vfrsqrt7v(const Instruction* inst);
 // Vector element approximate reciprocal instruction.
-void Vfrec7v(const Instruction *inst);
+void Vfrec7v(const Instruction* inst);
 // Vector element floating point value classify instruction.
-void Vfclassv(const Instruction *inst);
+void Vfclassv(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_instruction_helpers.h b/cheriot/riscv_cheriot_vector_instruction_helpers.h
index b7640e0..e5a325e 100644
--- a/cheriot/riscv_cheriot_vector_instruction_helpers.h
+++ b/cheriot/riscv_cheriot_vector_instruction_helpers.h

@@ -53,23 +53,23 @@
 // Note that this function will modify masked bits no matter what the mask
 // value is.
 template <typename Vs2, typename Vs1>
-void RiscVSetMaskBinaryVectorMaskOp(CheriotVectorState *rv_vector,
-                                    const Instruction *inst,
+void RiscVSetMaskBinaryVectorMaskOp(CheriotVectorState* rv_vector,
+                                    const Instruction* inst,
                                     std::function<bool(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Get the vector start element index and compute where to start
   // the operation.
   const int num_elements = rv_vector->vector_length();
   const int vector_index = rv_vector->vstart();
   // Allocate data buffer for the new register data.
-  auto *dest_db = dest_op->CopyDataBuffer();
+  auto* dest_db = dest_op->CopyDataBuffer();
   auto dest_span = dest_db->Get<uint8_t>();
   // Determine if it's vector-vector or vector-scalar.
   const bool vector_scalar = inst->Source(1)->shape()[0] == 1;
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   bool vm_unmasked_bit = false;
   if (inst->SourcesSize() > 3) {
     vm_unmasked_bit = GetInstructionSource<bool>(inst, 3);
@@ -99,23 +99,23 @@
 // mask and uses the mask value in the instruction, such as carry generation
 // from add with carry.
 template <typename Vs2, typename Vs1>
-void RiscVMaskBinaryVectorMaskOp(CheriotVectorState *rv_vector,
-                                 const Instruction *inst,
+void RiscVMaskBinaryVectorMaskOp(CheriotVectorState* rv_vector,
+                                 const Instruction* inst,
                                  std::function<bool(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Get the vector start element index and compute where to start
   // the operation.
   int num_elements = rv_vector->vector_length();
   int vector_index = rv_vector->vstart();
   // Allocate data buffer for the new register data.
-  auto *dest_db = dest_op->CopyDataBuffer();
+  auto* dest_db = dest_op->CopyDataBuffer();
   auto dest_span = dest_db->Get<uint8_t>();
   // Determine if it's vector-vector or vector-scalar.
   bool vector_scalar = inst->Source(1)->shape()[0] == 1;
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   bool vm_unmasked_bit = false;
   if (inst->SourcesSize() > 3) {
     vm_unmasked_bit = GetInstructionSource<bool>(inst, 3);
@@ -148,8 +148,8 @@
 // This helper function handles the case of vector mask
 // operations.
 template <typename Vs2, typename Vs1>
-void RiscVBinaryVectorMaskOp(CheriotVectorState *rv_vector,
-                             const Instruction *inst,
+void RiscVBinaryVectorMaskOp(CheriotVectorState* rv_vector,
+                             const Instruction* inst,
                              std::function<bool(Vs2, Vs1)> op) {
   RiscVMaskBinaryVectorMaskOp<Vs2, Vs1>(
       rv_vector, inst, [op](Vs2 vs2, Vs1 vs1, bool mask_value) -> bool {
@@ -164,16 +164,16 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd>
-void RiscVMaskNullaryVectorOp(CheriotVectorState *rv_vector,
-                              const Instruction *inst,
+void RiscVMaskNullaryVectorOp(CheriotVectorState* rv_vector,
+                              const Instruction* inst,
                               std::function<Vd(bool)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -185,13 +185,13 @@
   // There 2 types of instruction with different number of source operands.
   // 1. inst vd, vs2, vmask (viota instruction)
   // 2. inst vd, vmask (vid instruction)
-  RV32VectorSourceOperand *vs2_op = nullptr;
-  RV32VectorSourceOperand *mask_op = nullptr;
+  RV32VectorSourceOperand* vs2_op = nullptr;
+  RV32VectorSourceOperand* mask_op = nullptr;
   if (inst->SourcesSize() > 1) {
-    vs2_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
-    mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+    vs2_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
+    mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   } else {
-    mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+    mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   }
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
@@ -203,7 +203,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -240,7 +240,7 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd, typename Vs2>
-void RiscVUnaryVectorOp(CheriotVectorState *rv_vector, const Instruction *inst,
+void RiscVUnaryVectorOp(CheriotVectorState* rv_vector, const Instruction* inst,
                         std::function<Vd(Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -261,8 +261,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -272,7 +272,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -283,7 +283,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -312,7 +312,7 @@
 // narrowing operations.
 template <typename Vd, typename Vs2>
 void RiscVUnaryVectorOpWithFflags(
-    CheriotVectorState *rv_vector, const Instruction *inst,
+    CheriotVectorState* rv_vector, const Instruction* inst,
     std::function<std::tuple<Vd, uint32_t>(Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -333,8 +333,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -344,7 +344,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -356,7 +356,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -379,7 +379,7 @@
     dest_db->Submit();
     item_index = 0;
   }
-  auto *flag_db = inst->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = inst->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, fflags);
   flag_db->Submit();
   rv_vector->clear_vstart();
@@ -390,7 +390,7 @@
 // narrowing operations.
 template <typename Vd, typename Vs2, typename Vs1>
 void RiscVMaskBinaryVectorOp(
-    CheriotVectorState *rv_vector, const Instruction *inst,
+    CheriotVectorState* rv_vector, const Instruction* inst,
     std::function<std::optional<Vd>(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -412,8 +412,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -423,7 +423,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -437,7 +437,7 @@
   for (int reg = start_reg;
        !exception && (reg < max_regs) && (vector_index < num_elements); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -476,7 +476,7 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVBinaryVectorOp(CheriotVectorState *rv_vector, const Instruction *inst,
+void RiscVBinaryVectorOp(CheriotVectorState* rv_vector, const Instruction* inst,
                          std::function<Vd(Vs2, Vs1)> op) {
   RiscVMaskBinaryVectorOp<Vd, Vs2, Vs1>(
       rv_vector, inst,
@@ -490,7 +490,7 @@
 
 template <typename Vd, typename Vs2, typename Vs1>
 void RiscVBinaryVectorOpWithFflags(
-    CheriotVectorState *rv_vector, const Instruction *inst,
+    CheriotVectorState* rv_vector, const Instruction* inst,
     std::function<std::tuple<Vd, uint32_t>(Vs2, Vs1)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -512,8 +512,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -523,7 +523,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -538,7 +538,7 @@
   for (int reg = start_reg;
        !exception && (reg < max_regs) && (vector_index < num_elements); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -568,7 +568,7 @@
     dest_db->Submit();
     item_index = 0;
   }
-  auto *flag_db = inst->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = inst->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, fflags);
   flag_db->Submit();
   rv_vector->clear_vstart();
@@ -578,8 +578,8 @@
 // implements all the checking necessary for both widening and narrowing
 // operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVTernaryVectorOp(CheriotVectorState *rv_vector,
-                          const Instruction *inst,
+void RiscVTernaryVectorOp(CheriotVectorState* rv_vector,
+                          const Instruction* inst,
                           std::function<Vd(Vs2, Vs1, Vd)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -601,8 +601,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -612,7 +612,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -625,7 +625,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -656,8 +656,8 @@
 // masking) from Vs2 and apply the reduction operation to produce a single
 // element that is written to Vd[0].
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVBinaryReductionVectorOp(CheriotVectorState *rv_vector,
-                                  const Instruction *inst,
+void RiscVBinaryReductionVectorOp(CheriotVectorState* rv_vector,
+                                  const Instruction* inst,
                                   std::function<Vd(Vd, Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   if (rv_vector->vstart()) {
@@ -681,7 +681,7 @@
   }
   int num_elements = rv_vector->vector_length();
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   Vd accumulator =
       static_cast<Vd>(generic::GetInstructionSource<Vs1>(inst, 1, 0));
@@ -694,8 +694,8 @@
           op(accumulator, generic::GetInstructionSource<Vs2>(inst, 0, i));
     }
   }
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   dest_db->Set<Vd>(0, accumulator);
   dest_db->Submit();
@@ -735,7 +735,7 @@
 }
 
 template <typename T>
-T RoundOff(CheriotVectorState *rv_vector, T value, int size) {
+T RoundOff(CheriotVectorState* rv_vector, T value, int size) {
   auto rm = rv_vector->vxrm();
   auto ret = (value >> size) + GetRoundingBit<T>(rm, value, size + 1);
   return ret;

diff --git a/cheriot/riscv_cheriot_vector_memory_instructions.cc b/cheriot/riscv_cheriot_vector_memory_instructions.cc
index f56bab5..7d86a43 100644
--- a/cheriot/riscv_cheriot_vector_memory_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_memory_instructions.cc

@@ -42,14 +42,14 @@
 using CapReg = CheriotRegister;
 
 // Helper to get capability register source and destination registers.
-static inline CapReg *GetCapSource(const Instruction *instruction, int i) {
-  return static_cast<CapReg *>(
-      std::any_cast<RegisterBase *>(instruction->Source(i)->GetObject()));
+static inline CapReg* GetCapSource(const Instruction* instruction, int i) {
+  return static_cast<CapReg*>(
+      std::any_cast<RegisterBase*>(instruction->Source(i)->GetObject()));
 }
 
-static inline bool CheckCapForMemoryAccess(const Instruction *instruction,
-                                           CapReg *cap_reg,
-                                           CheriotState *state) {
+static inline bool CheckCapForMemoryAccess(const Instruction* instruction,
+                                           CapReg* cap_reg,
+                                           CheriotState* state) {
   // Check for tag unset.
   if (!cap_reg->tag()) {
     state->HandleCheriRegException(instruction, instruction->address(),
@@ -72,9 +72,9 @@
   return true;
 }
 
-static inline bool CheckCapBounds(const Instruction *instruction,
+static inline bool CheckCapBounds(const Instruction* instruction,
                                   uint64_t address, int el_width,
-                                  CapReg *cap_reg, CheriotState *state) {
+                                  CapReg* cap_reg, CheriotState* state) {
   // Check for bounds.
   if (!cap_reg->IsInBounds(address, el_width)) {
     state->HandleCheriRegException(instruction, instruction->address(),
@@ -89,9 +89,9 @@
 // writes the loaded data into the registers.
 template <typename T>
 absl::Status WriteBackLoadData(int vector_register_byte_length,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
   // Get values from context.
-  auto *context = static_cast<VectorLoadContext *>(inst->context());
+  auto* context = static_cast<VectorLoadContext*>(inst->context());
   auto masks = context->mask_db->Get<bool>();
   auto values = context->value_db->Get<T>();
   int vector_start = context->vstart;
@@ -102,8 +102,8 @@
   int max_regs =
       (vector_length + elements_per_vector - 1) / elements_per_vector;
   // Verify that the dest_op has enough registers. Else signal error.
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (dest_op->size() < max_regs) {
     // TODO: signal error.
     return absl::InternalError("Not enough registers in destination operand");
@@ -123,7 +123,7 @@
   // Iterate over the number of registers to write.
   for (int reg = start_reg; (reg < max_regs) && (value_count > 0); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<T>();
     // Write data into register subject to masking.
     int count = std::min(elements_per_vector - item_index, value_count);
@@ -144,11 +144,11 @@
 // writes the loaded data into the registers.
 template <typename T>
 absl::Status WriteBackSegmentLoadData(int vector_register_byte_length,
-                                      const Instruction *inst) {
+                                      const Instruction* inst) {
   // The number of fields in each segment.
   int num_fields = GetInstructionSource<uint32_t>(inst, 0) + 1;
   // Get values from context.
-  auto *context = static_cast<VectorLoadContext *>(inst->context());
+  auto* context = static_cast<VectorLoadContext*>(inst->context());
   auto masks = context->mask_db->Get<bool>();
   auto values = context->value_db->Get<T>();
   int start_segment = context->vstart;
@@ -164,8 +164,8 @@
   // Total number of registers written.
   int total_regs = num_fields * num_regs;
   // Verify that the dest_op has enough registers. Else signal error.
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (dest_op->size() < total_regs) {
     return absl::InternalError("Not enough registers in destination operand");
   }
@@ -184,7 +184,7 @@
     int offset = start_segment % max_elements_per_vector;
     int remaining_data = num_segments;
     for (int reg = start_reg; reg < start_reg + num_regs; reg++) {
-      auto *dest_db = dest_op->CopyDataBuffer(reg);
+      auto* dest_db = dest_op->CopyDataBuffer(reg);
       auto span = dest_db->Get<T>();
       int max_entry =
           std::min(remaining_data + offset, max_elements_per_vector);
@@ -205,9 +205,9 @@
 // This models the vsetvl set of instructions. The immediate versus register
 // versions are all modeled by the same function. Flags are bound during decode
 // to the two first parameters to specify if rd or rs1 are x0.
-void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   uint32_t vtype = GetInstructionSource<uint32_t>(inst, 1) & 0b1'1'111'111;
   // Get previous vtype.
   uint32_t prev_vtype = rv_vector->vtype();
@@ -259,9 +259,9 @@
 // Source(1): stride size bytes.
 // Source(2): vector mask register, vector constant {1..} if not masked.
 // Destination(0): vector destination register.
-void VlStrided(int element_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VlStrided(int element_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
@@ -280,18 +280,18 @@
   int num_elements_loaded = num_elements - start;
 
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
 
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate(num_elements_loaded * element_width);
+  auto* value_db = db_factory->Allocate(num_elements_loaded * element_width);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Allocate a byte mask data buffer for the load.
-  auto *mask_db = db_factory->Allocate<bool>(num_elements_loaded);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements_loaded);
 
   // Get the spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
@@ -317,7 +317,7 @@
   }
 
   // Set up the context, and submit the load.
-  auto *context = new VectorLoadContext(value_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(value_db, mask_db, element_width, start,
                                         rv_vector->vector_length());
   value_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width, value_db,
@@ -332,9 +332,9 @@
 
 // Source(0): base address.
 // Destination(0): vector destination register (for the child instruction).
-void Vlm(const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void Vlm(const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
@@ -342,12 +342,12 @@
   // Compute the number of bytes to be loaded.
   int num_bytes = rv_vector->vector_register_byte_length() - start;
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_bytes);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_bytes);
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate<uint8_t>(num_bytes);
+  auto* value_db = db_factory->Allocate<uint8_t>(num_bytes);
   // Allocate a byte mask data buffer.
-  auto *mask_db = db_factory->Allocate<bool>(num_bytes);
+  auto* mask_db = db_factory->Allocate<bool>(num_bytes);
   // Get the spans for addresses and masks.
   auto masks = mask_db->Get<bool>();
   auto addresses = address_db->Get<uint64_t>();
@@ -363,10 +363,10 @@
     }
   }
   // Set up the context, and submit the load.
-  auto *context =
+  auto* context =
       new VectorLoadContext(value_db, mask_db, sizeof(uint8_t), start,
                             rv_vector->vector_register_byte_length());
-  auto *rv32_state = static_cast<CheriotState *>(inst->state());
+  auto* rv32_state = static_cast<CheriotState*>(inst->state());
   value_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, sizeof(uint8_t), value_db,
                          inst->child(), context);
@@ -387,16 +387,16 @@
 // Source(1) index vector.
 // Source(2) masks.
 // Destination(0): vector destination register (for the child instruction).
-void VlIndexed(int index_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VlIndexed(int index_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
   int element_width = rv_vector->selected_element_width();
   int lmul = rv_vector->vector_length_multiplier();
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   int index_emul = index_width * lmul / element_width;
   // Validate that emul has a legal value.
   if ((index_emul > 64) || (index_emul == 0)) {
@@ -413,19 +413,19 @@
   int num_bytes_loaded = num_elements_loaded * element_width;
 
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
   auto addresses = address_db->Get<uint64_t>();
 
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate(num_bytes_loaded);
+  auto* value_db = db_factory->Allocate(num_bytes_loaded);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Allocate a byte mask data buffer for the load.
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   auto masks = mask_db->Get<bool>();
 
   // Convert the bit masks to byte masks and compute the element addresses.
@@ -467,7 +467,7 @@
   }
 
   // Set up context and submit load.
-  auto *context = new VectorLoadContext(value_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(value_db, mask_db, element_width, start,
                                         rv_vector->vector_length());
   value_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width, value_db,
@@ -485,19 +485,19 @@
 // Source(0): base address.
 // Destination(0): vector destination register (for the child instruction).
 void VlRegister(int num_regs, int element_width_bytes,
-                const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+                const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
   int num_elements =
       rv_vector->vector_register_byte_length() * num_regs / element_width_bytes;
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width_bytes);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width_bytes);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -521,7 +521,7 @@
   }
 
   // Set up context and submit load.
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width_bytes,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width_bytes,
                                         0, num_elements);
   data_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width_bytes, data_db,
@@ -542,14 +542,14 @@
 // Source(1): mask
 // Source(2): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegment(int element_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VlSegment(int element_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 2) + 1;
   // Effective vector length multiplier.
@@ -566,10 +566,10 @@
   int segment_stride = num_fields * element_width;
   int num_elements = num_fields * num_segments;
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -593,7 +593,7 @@
       }
     }
   }
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
   data_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
@@ -611,15 +611,15 @@
 // Source(2): mask
 // Source(3): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegmentStrided(int element_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VlSegmentStrided(int element_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
   int64_t segment_stride = GetInstructionSource<int64_t>(inst, 1);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   // Effective vector length multiplier.
@@ -635,10 +635,10 @@
   int num_segments = rv_vector->vector_length();
   int num_elements = num_fields * num_segments;
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -662,7 +662,7 @@
     }
   }
   // Allocate the context and submit the load.
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
   data_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
@@ -681,15 +681,15 @@
 // Source(2): mask
 // Source(3): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegmentIndexed(int index_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VlSegmentIndexed(int index_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   int start = rv_vector->vstart();
   auto cap_reg = GetCapSource(inst, 0);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   int element_width = rv_vector->selected_element_width();
@@ -716,10 +716,10 @@
   int num_elements = num_fields * num_segments;
 
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the spans for the addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -765,7 +765,7 @@
       }
     }
   }
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
   data_db->set_latency(0);
   state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
@@ -779,11 +779,11 @@
 // Child instruction used for non-segment vector loads. This function really
 // only is used to select a type specific version of the helper function to
 // write back the load data.
-void VlChild(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void VlChild(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   absl::Status status;
   int byte_length = rv_vector->vector_register_byte_length();
-  switch (static_cast<VectorLoadContext *>(inst->context())->element_width) {
+  switch (static_cast<VectorLoadContext*>(inst->context())->element_width) {
     case 1:
       status = WriteBackLoadData<uint8_t>(byte_length, inst);
       break;
@@ -809,11 +809,11 @@
 // Child instruction used for segmen vector loads. This function really only is
 // used to select a type specific version of the helper function to write back
 // the load data.
-void VlSegmentChild(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void VlSegmentChild(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   absl::Status status;
   int byte_length = rv_vector->vector_register_byte_length();
-  switch (static_cast<VectorLoadContext *>(inst->context())->element_width) {
+  switch (static_cast<VectorLoadContext*>(inst->context())->element_width) {
     case 1:
       status = WriteBackSegmentLoadData<uint8_t>(byte_length, inst);
       break;
@@ -839,23 +839,23 @@
 // Templated helper function for vector stores.
 template <typename T>
 void StoreVectorStrided(int vector_length, int vstart, int emul,
-                        const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
+                        const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
   int64_t stride = GetInstructionSource<int64_t>(inst, 2);
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Compute total number of elements to be stored.
   int num_elements = vector_length;
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
   auto addresses = address_db->Get<uint64_t>();
-  auto *store_data_db = db_factory->Allocate(num_elements * sizeof(T));
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* store_data_db = db_factory->Allocate(num_elements * sizeof(T));
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
 
   // Get the spans for addresses and masks.
   auto store_data = store_data_db->Get<T>();
@@ -890,8 +890,8 @@
 // Source(1): base address.
 // Source(2): stride.
 // Source(3): vector mask register, vector constant {1..} if not masked.
-void VsStrided(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void VsStrided(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int emul = element_width * rv_vector->vector_length_multiplier() /
              rv_vector->selected_element_width();
   // Validate that emul has a legal value.
@@ -925,9 +925,9 @@
 // Store vector mask. Single vector register store.
 // Source(0): store data
 // Source(1): base address
-void Vsm(const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void Vsm(const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
@@ -937,10 +937,10 @@
   int num_bytes = rv_vector->vector_register_byte_length();
   int num_bytes_stored = num_bytes - start;
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_bytes_stored);
-  auto *store_data_db = db_factory->Allocate(num_bytes_stored);
-  auto *mask_db = db_factory->Allocate<uint8_t>(num_bytes_stored);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_bytes_stored);
+  auto* store_data_db = db_factory->Allocate(num_bytes_stored);
+  auto* mask_db = db_factory->Allocate<uint8_t>(num_bytes_stored);
   // Get the spans for addresses, masks, and store data.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -975,9 +975,9 @@
 // Source(1): base address.
 // Source(2): offset vector.
 // Source(3): mask.
-void VsIndexed(int index_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VsIndexed(int index_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
@@ -994,16 +994,16 @@
     return;
   }
 
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
 
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *value_db = db_factory->Allocate(num_elements * element_width);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* value_db = db_factory->Allocate(num_elements * element_width);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Get the spans for addresses, masks, and data.
@@ -1074,19 +1074,19 @@
   rv_vector->clear_vstart();
 }
 
-void VsRegister(int num_regs, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VsRegister(int num_regs, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base = cap_reg->address();
   int num_elements =
       rv_vector->vector_register_byte_length() * num_regs / sizeof(uint64_t);
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the address, mask, and data spans.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1111,14 +1111,14 @@
 
 // Vector store segment (unit stride). This stores the segments contiguously
 // in memory in a sequential manner.
-void VsSegment(int element_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VsSegment(int element_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base_address = cap_reg->address();
   int start = rv_vector->vstart();
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   // Effective vector length multiplier.
@@ -1138,10 +1138,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, emul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1150,7 +1150,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   uint64_t address = base_address;
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
@@ -1181,7 +1181,7 @@
         return;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);
@@ -1211,15 +1211,15 @@
 
 // Vector strided segment store. This stores each segment contiguously at
 // locations separated by the segment stride.
-void VsSegmentStrided(int element_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VsSegmentStrided(int element_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base_address = cap_reg->address();
   int start = rv_vector->vstart();
   int64_t segment_stride = GetInstructionSource<int64_t>(inst, 2);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 4) + 1;
   // Effective vector length multiplier.
@@ -1239,10 +1239,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, emul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1251,7 +1251,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   uint64_t segment_address = base_address;
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
@@ -1283,7 +1283,7 @@
         return;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);
@@ -1315,14 +1315,14 @@
 // Vector indexed segment store. This instruction stores each segment
 // contiguously at an address formed by adding the index value for that
 // segment (from the index vector source operand) to the base address.
-void VsSegmentIndexed(int index_width, const Instruction *inst) {
-  auto *state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = state->rv_vector();
+void VsSegmentIndexed(int index_width, const Instruction* inst) {
+  auto* state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = state->rv_vector();
   auto cap_reg = GetCapSource(inst, 1);
   if (!CheckCapForMemoryAccess(inst, cap_reg, state)) return;
   uint64_t base_address = cap_reg->address();
   int start = rv_vector->vstart();
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 4) + 1;
   int element_width = rv_vector->selected_element_width();
@@ -1351,10 +1351,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, lmul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1363,7 +1363,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
     // Masks are applied on a segment basis.
@@ -1413,7 +1413,7 @@
         return;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);

diff --git a/cheriot/riscv_cheriot_vector_memory_instructions.h b/cheriot/riscv_cheriot_vector_memory_instructions.h
index ab3cb41..441ab3c 100644
--- a/cheriot/riscv_cheriot_vector_memory_instructions.h
+++ b/cheriot/riscv_cheriot_vector_memory_instructions.h

@@ -31,7 +31,7 @@
 // The instruction takes 2 instruction source scalar operands: source operand 0
 // is the requested vector length, source operand 1 is the requested vector
 // configuration value. The destination operand is a scalar.
-void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction *inst);
+void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction* inst);
 
 // Vector load semantic functions.
 // Load with unit stride as element width. The instruction takes 2 source and 1
@@ -39,47 +39,47 @@
 // operand 1 is the vector mask (either a vector register, or a constant).
 // Destination operand 0 is assigned to the child instruction and is a vector
 // register (group).
-void VlUnitStrided(int element_width, const Instruction *inst);
+void VlUnitStrided(int element_width, const Instruction* inst);
 // Load with constant stride, the parameter specifies the width of the vector
 // elements. This instruction takes 3 source and 1 destination operands. Source
 // operand 0 is a scalar base address, source operand 1 is a scalar stride,
 // source operand 2 is the vector mask (either a vector register, or a
 // constant). Destination operand 0 is assigned to the child instruction and
 // is a vector register (group).
-void VlStrided(int element_width, const Instruction *inst);
+void VlStrided(int element_width, const Instruction* inst);
 // Load vector mask. This instruction takes 1 source and 1 destination operand.
 // The source operand is a scalar base address, the destination operand is the
 // vector register to write the mask to.
-void Vlm(const Instruction *inst);
+void Vlm(const Instruction* inst);
 // Indexed vector load (ordered and unordered). This instruction takes 3 source
 // and 1 destination operands. Source operand 0 is a scalar base address, source
 // operand 1 is a vector register (group) of indices, source operand 2 is the
 // vector mask. Destination operand 0 is assigned to the child instruction and
 // is a vector register (group).
-void VlIndexed(int index_width, const Instruction *inst);
+void VlIndexed(int index_width, const Instruction* inst);
 // Load vector register(s). Takes a parameter specifying how many registers to
 // load. This instruction takes 1 source and 1 destination operand. Source
 // operand 0 is a scalar base address. Destination operand 0 is assigned to the
 // child instruction and is a vector register (group).
-void VlRegister(int num_regs, int element_width_bytes, const Instruction *inst);
+void VlRegister(int num_regs, int element_width_bytes, const Instruction* inst);
 // Child instruction semantic functions for non-segment loads responsible for
 // writing load data back to the target register(s). It takes a single
 // destination operand. Destination operand 0 is a vector register (group).
-void VlChild(const Instruction *inst);
+void VlChild(const Instruction* inst);
 // Load segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 3 source operands and 1 destination
 // operand. Source operand 0 is a scalar base address, source operand 1 is
 // the vector mask, and source operand 2 is the number of fields - 1.
 // Destination operand 0 is assigned to the child instruction and is a vector
 // register (group).
-void VlSegment(int element_width, const Instruction *inst);
+void VlSegment(int element_width, const Instruction* inst);
 // Load segment strided. The function takes one parameter that specifies
 // the element width. The instruction takes 4 source operands and 1 destination
 // operand. Source operand 0 is a scalar base address, source operand 1 is a
 // scalar stride, source operand 2 is the vector mask, and source operand 3 is
 // the number of fields - 1. Destination operand 0 is assigned to the child
 // instruction and is a vector register (group).
-void VlSegmentStrided(int element_width, const Instruction *inst);
+void VlSegmentStrided(int element_width, const Instruction* inst);
 // Load segment indexed. The function takes one parameter that specifies
 // the index element width. The instruction takes 4 source operands and 1
 // destination operand. Source operand 0 is a scalar base address, source
@@ -87,11 +87,11 @@
 // vector mask, and source operand 3 is the number of fields - 1. Destination
 // operand 0 is assigned to the child instruction and is a vector register
 // (group).
-void VlSegmentIndexed(int index_width, const Instruction *inst);
+void VlSegmentIndexed(int index_width, const Instruction* inst);
 // Child instruction semantic functions for segment loads responsible for
 // writing load data back to the target register(s). It takes a single
 // destination operand. Destination operand 0 is a vector register (group).
-void VlSegmentChild(int element_width, const Instruction *inst);
+void VlSegmentChild(int element_width, const Instruction* inst);
 
 // Vector store semantic functions.
 
@@ -99,39 +99,39 @@
 // width. The instruction takes 4 source parameters. Source 0 is the store data
 // vector register (group), source 1 is the scalar base address, source 2 is the
 // stride, and source 3 is the vector mask.
-void VsStrided(int element_width, const Instruction *inst);
+void VsStrided(int element_width, const Instruction* inst);
 // Store vector mask. This instruction takes 2 source operands. Source 0 is the
 // vector mask register to be stored, the second is the scalar base address.
-void Vsm(const Instruction *inst);
+void Vsm(const Instruction* inst);
 // Store indexed. The function takes one parameter that specifies the element
 // width. The instruction takes 4 source parameters. Source 0 is the store data
 // vector register (group), source 1 is a vector (group) of indices, source 2 is
 // the stride, and source 3 is the vector mask.
-void VsIndexed(int index_width, const Instruction *inst);
+void VsIndexed(int index_width, const Instruction* inst);
 // Store vector register (group). This function takes one parameter that
 // specifies the number of registers to store. The instruction takes 2 source
 // operands. Source 0 is the source vector register (group), the second is the
 // scalar base address.
-void VsRegister(int num_regs, const Instruction *inst);
+void VsRegister(int num_regs, const Instruction* inst);
 // Store segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 4 source operands. Source operand 0
 // is the store data, source operand 1 is the scalar base address, source
 // operand 2 is the vector mask, and source operand 3 is the number of fields
 // - 1.
-void VsSegment(int element_width, const Instruction *inst);
+void VsSegment(int element_width, const Instruction* inst);
 // Store segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 5 source operands. Source operand 0
 // is the store data, source operand 1 is the scalar base address, source
 // operand 2 is the segment stride, source operand 3 is the vector mask, and
 // source operand 4 is the number of fields
 // - 1.
-void VsSegmentStrided(int element_width, const Instruction *inst);
+void VsSegmentStrided(int element_width, const Instruction* inst);
 // Load segment indexed. The function takes one parameter that specifies
 // the index element width. The instruction takes 5 source operands. Source
 // operand 0 is the store data, source operand 1 is a scalar base address,
 // source operand 2 is a vector register (group) of indices, source operand 3 is
 // the vector mask, and source operand 4 is the number of fields - 1.
-void VsSegmentIndexed(int index_width, const Instruction *inst);
+void VsSegmentIndexed(int index_width, const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_opi_instructions.cc b/cheriot/riscv_cheriot_vector_opi_instructions.cc
index e2fa037..d6ee4a6 100644
--- a/cheriot/riscv_cheriot_vector_opi_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_opi_instructions.cc

@@ -44,8 +44,8 @@
 // Vector arithmetic operations.
 
 // Vector add.
-void Vadd(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vadd(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -72,8 +72,8 @@
 }
 
 // Vector subtract.
-void Vsub(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsub(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -100,8 +100,8 @@
 }
 
 // Vector reverse subtract.
-void Vrsub(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vrsub(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -130,8 +130,8 @@
 // Vector logical operations.
 
 // Vector and.
-void Vand(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vand(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -158,8 +158,8 @@
 }
 
 // Vector or.
-void Vor(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vor(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -186,8 +186,8 @@
 }
 
 // Vector xor.
-void Vxor(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vxor(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -216,8 +216,8 @@
 // Vector shift operations.
 
 // Vector shift left logical.
-void Vsll(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsll(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -248,8 +248,8 @@
 }
 
 // Vector shift right logical.
-void Vsrl(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsrl(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -280,8 +280,8 @@
 }
 
 // Vector shift right arithmetic.
-void Vsra(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsra(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -315,8 +315,8 @@
 
 // Vector narrowing shift right logical. Source op 0 is shifted right
 // by source op 1 and the result is 1/2 the size of source op 0.
-void Vnsrl(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnsrl(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -349,8 +349,8 @@
 
 // Vector narrowing shift right arithmetic. Source op 0 is shifted right
 // by source op 1 and the result is 1/2 the size of source op 0.
-void Vnsra(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnsra(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // If the vector length multiplier (x8) is greater than 32, that means that
   // the source values (sew * 2) would exceed the available register group.
@@ -385,8 +385,8 @@
 }
 
 // Vector unsigned min.
-void Vminu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vminu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -417,8 +417,8 @@
 }
 
 // Vector signed min.
-void Vmin(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmin(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -448,8 +448,8 @@
 }
 
 // Vector unsigned max.
-void Vmaxu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmaxu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -480,8 +480,8 @@
 }
 
 // Vector signed max.
-void Vmax(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmax(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -511,8 +511,8 @@
 }
 
 // Set equal.
-void Vmseq(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmseq(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -541,8 +541,8 @@
 // Vector compare instructions.
 
 // Set not equal.
-void Vmsne(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsne(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -569,8 +569,8 @@
 }
 
 // Set less than unsigned.
-void Vmsltu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsltu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -597,8 +597,8 @@
 }
 
 // Set less than.
-void Vmslt(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmslt(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -625,8 +625,8 @@
 }
 
 // Set less than or equal unsigned.
-void Vmsleu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsleu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -653,8 +653,8 @@
 }
 
 // Set less than or equal.
-void Vmsle(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsle(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -681,8 +681,8 @@
 }
 
 // Set greater than unsigned.
-void Vmsgtu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsgtu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -709,8 +709,8 @@
 }
 
 // Set greater than.
-void Vmsgt(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsgt(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -737,8 +737,8 @@
 }
 
 // Saturated unsigned addition.
-void Vsaddu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsaddu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -792,7 +792,7 @@
 // Uses unsigned arithmetic for the addition to avoid signed overflow, which,
 // when compiled with --config=asan, will trigger an exception.
 template <typename T>
-inline T VsaddHelper(T vs2, T vs1, CheriotVectorState *rv_vector) {
+inline T VsaddHelper(T vs2, T vs1, CheriotVectorState* rv_vector) {
   using UT = typename std::make_unsigned<T>::type;
   UT uvs2 = static_cast<UT>(vs2);
   UT uvs1 = static_cast<UT>(vs1);
@@ -806,8 +806,8 @@
 }
 
 // Saturated signed addition.
-void Vsadd(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsadd(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -838,8 +838,8 @@
 }
 
 // Saturated unsigned subtract.
-void Vssubu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vssubu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -890,7 +890,7 @@
 }
 
 template <typename T>
-T VssubHelper(T vs2, T vs1, CheriotVectorState *rv_vector) {
+T VssubHelper(T vs2, T vs1, CheriotVectorState* rv_vector) {
   using UT = typename std::make_unsigned<T>::type;
   UT uvs2 = static_cast<UT>(vs2);
   UT uvs1 = static_cast<UT>(vs1);
@@ -904,8 +904,8 @@
 }
 
 // Saturated signed subtract.
-void Vssub(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vssub(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -936,8 +936,8 @@
 }
 
 // Add/Subtract with carry, carry generation.
-void Vadc(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vadc(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -971,8 +971,8 @@
 }
 
 // Add with carry - carry generation.
-void Vmadc(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmadc(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1024,8 +1024,8 @@
 }
 
 // Subtract with borrow.
-void Vsbc(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsbc(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1059,8 +1059,8 @@
 }
 
 // Subtract with borrow - borrow generation.
-void Vmsbc(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsbc(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1096,8 +1096,8 @@
 }
 
 // Vector merge.
-void Vmerge(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmerge(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1131,13 +1131,13 @@
 }
 
 // Vector move register(s).
-void Vmvr(int num_regs, Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmvr(int num_regs, Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vector_exception()) return;
 
-  auto *src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (src_op->size() < num_regs) {
     LOG(ERROR) << "Vmvr: source operand has fewer registers than requested";
     rv_vector->set_vector_exception();
@@ -1154,8 +1154,8 @@
   int vstart = rv_vector->vstart();
   int start_reg = vstart / num_elements_per_vector;
   for (int i = start_reg; i < num_regs; i++) {
-    auto *src_db = src_op->GetRegister(i)->data_buffer();
-    auto *dest_db = dest_op->AllocateDataBuffer(i);
+    auto* src_db = src_op->GetRegister(i)->data_buffer();
+    auto* dest_db = dest_op->AllocateDataBuffer(i);
     std::memcpy(dest_db->raw_ptr(), src_db->raw_ptr(),
                 dest_db->size<uint8_t>());
     dest_db->Submit();
@@ -1165,7 +1165,7 @@
 
 // Templated helper function for shift right with rounding.
 template <typename T>
-T VssrHelper(CheriotVectorState *rv_vector, T vs2, T vs1) {
+T VssrHelper(CheriotVectorState* rv_vector, T vs2, T vs1) {
   using UT = typename MakeUnsigned<T>::type;
   int rm = rv_vector->vxrm();
   int max_shift = (sizeof(T) << 3) - 1;
@@ -1183,8 +1183,8 @@
 }
 
 // Logical shift right with rounding.
-void Vssrl(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vssrl(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1215,8 +1215,8 @@
 }
 
 // Arithmetic shift right with rounding.
-void Vssra(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vssra(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1248,7 +1248,7 @@
 
 // Templated helper function for shift right with rounding and saturation.
 template <typename DT, typename WT, typename T>
-T VnclipHelper(CheriotVectorState *rv_vector, WT vs2, T vs1) {
+T VnclipHelper(CheriotVectorState* rv_vector, WT vs2, T vs1) {
   using WUT = typename std::make_unsigned<WT>::type;
   int rm = rv_vector->vxrm();
   int max_shift = (sizeof(WT) << 3) - 1;
@@ -1276,8 +1276,8 @@
 
 // Arithmetic shift right and narrowing from 2*sew to sew with rounding and
 // signed saturation.
-void Vnclip(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnclip(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int lmul8 = rv_vector->vector_length_multiplier();
   // This is a narrowing operation and sew is that of the narrow data type.
   // Thus if lmul > 32, then emul for the wider data type is illegal.
@@ -1314,8 +1314,8 @@
 
 // Logical shift right and narrowing from 2*sew to sew with rounding and
 // unsigned saturation.
-void Vnclipu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnclipu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int lmul8 = rv_vector->vector_length_multiplier();
   // This is a narrowing operation and sew is that of the narrow data type.
   // Thus if lmul > 32, then emul for the wider data type is illegal.
@@ -1356,7 +1356,7 @@
 // Perform a signed multiply from T to wider int type. Shift that result
 // right by sizeof(T) * 8 - 1 and round. Saturate if needed to fit into T.
 template <typename T>
-T VsmulHelper(CheriotVectorState *rv_vector, T vs2, T vs1) {
+T VsmulHelper(CheriotVectorState* rv_vector, T vs2, T vs1) {
   using WT = typename WideType<T>::type;
   WT vd_w;
   WT vs2_w = static_cast<WT>(vs2);
@@ -1375,8 +1375,8 @@
 }
 
 // Vector fractional multiply with rounding and saturation.
-void Vsmul(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsmul(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:

diff --git a/cheriot/riscv_cheriot_vector_opi_instructions.h b/cheriot/riscv_cheriot_vector_opi_instructions.h
index 87ccbd9..f8bbe4e 100644
--- a/cheriot/riscv_cheriot_vector_opi_instructions.h
+++ b/cheriot/riscv_cheriot_vector_opi_instructions.h

@@ -34,200 +34,200 @@
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vadd(Instruction *inst);
+void Vadd(Instruction* inst);
 // Element wide vector subtract. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector) or rs1 (scalar). Source 2 is a vector
 // mask operand.
-void Vsub(Instruction *inst);
+void Vsub(Instruction* inst);
 // Element wide vector reverse subtract. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vrsub(Instruction *inst);
+void Vrsub(Instruction* inst);
 // Element wide bitwise and. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vand(Instruction *inst);
+void Vand(Instruction* inst);
 // Element wide bitwise or. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vor(Instruction *inst);
+void Vor(Instruction* inst);
 // Element wide bitwise xor. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vxor(Instruction *inst);
+void Vxor(Instruction* inst);
 // Element wide logical left shift. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsll(Instruction *inst);
+void Vsll(Instruction* inst);
 // Element wide logical right shift. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vsrl(Instruction *inst);
+void Vsrl(Instruction* inst);
 // Element wide arithmetic right shift. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vsra(Instruction *inst);
+void Vsra(Instruction* inst);
 // Element wide narrowing logical right shift. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnsrl(Instruction *inst);
+void Vnsrl(Instruction* inst);
 // Element wide narrowing arithmetic right shift. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnsra(Instruction *inst);
+void Vnsra(Instruction* inst);
 // Vector signed min (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmin(Instruction *inst);
+void Vmin(Instruction* inst);
 // Vector unsigned min (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vminu(Instruction *inst);
+void Vminu(Instruction* inst);
 // Vector signed max (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmax(Instruction *inst);
+void Vmax(Instruction* inst);
 // Vector unsigned max (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmaxu(Instruction *inst);
+void Vmaxu(Instruction* inst);
 // Vector mask set equal. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmseq(Instruction *inst);
+void Vmseq(Instruction* inst);
 // Vector mask set not equal.  This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsne(Instruction *inst);
+void Vmsne(Instruction* inst);
 // Vector mask set less than unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vmsltu(Instruction *inst);
+void Vmsltu(Instruction* inst);
 // Vector mask set less than signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector mask
 // operand.
-void Vmslt(Instruction *inst);
+void Vmslt(Instruction* inst);
 // Vector mask set less or equal unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector mask
 // operand.
-void Vmsleu(Instruction *inst);
+void Vmsleu(Instruction* inst);
 // Vector mask set less or equal signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vmsle(Instruction *inst);
+void Vmsle(Instruction* inst);
 // Vector mask set greater than unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsgtu(Instruction *inst);
+void Vmsgtu(Instruction* inst);
 // Vector mask set greater than signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsgt(Instruction *inst);
+void Vmsgt(Instruction* inst);
 // Vector saturating unsigned add. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsaddu(Instruction *inst);
+void Vsaddu(Instruction* inst);
 // Vector saturating signed add. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsadd(Instruction *inst);
+void Vsadd(Instruction* inst);
 // Vector saturating unsigned subtrract. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vssubu(Instruction *inst);
+void Vssubu(Instruction* inst);
 // Vector saturating subtract. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vssub(Instruction *inst);
+void Vssub(Instruction* inst);
 // Vector add with carry. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand that contains the carry in values.
-void Vadc(Instruction *inst);
+void Vadc(Instruction* inst);
 // Vector add with carry - carry generate. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand that contains the carry in values. The output of this
 // instruction is the carry outs of each element wise addition. It is stored in
 // the format of the vector flags.
-void Vmadc(Instruction *inst);
+void Vmadc(Instruction* inst);
 // Vector subtract with borrow. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand that contains the borrow values.
-void Vsbc(Instruction *inst);
+void Vsbc(Instruction* inst);
 // Vector subtract with borrow - borrow generate. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand that contains the borrow values. The output
 // of this instruction is the borrow outs of each element wise subtraction. It
 // is stored in the format of the vector flags.
-void Vmsbc(Instruction *inst);
+void Vmsbc(Instruction* inst);
 // Vector pairwise merge. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand. This semantic function also captures the functionality of vmv.vv,
 // vmv.vx, and vmv.vi, in which case vs2 is register group v0, and the mask
 // is all ones.
-void Vmerge(Instruction *inst);
+void Vmerge(Instruction* inst);
 // Vector register move. This instruction takes one source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. The num_regs
 // value is part of the opcode and should be bound to the semantic function at
 // decode.
-void Vmvr(int num_regs, Instruction *inst);
+void Vmvr(int num_regs, Instruction* inst);
 // Vector logical right shift with rounding. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vssrl(Instruction *inst);
+void Vssrl(Instruction* inst);
 // Vector arithmetic right shift with rounding. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vssra(Instruction *inst);
+void Vssra(Instruction* inst);
 // Vector logical right shift with rounding and (unsigned) saturation from SEW *
 // 2 to SEW wide elements. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnclipu(Instruction *inst);
+void Vnclipu(Instruction* inst);
 // Vector arithmetic right shift with rounding and (signed) saturation from SEW
 // * 2 to SEW wide elements. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnclip(Instruction *inst);
+void Vnclip(Instruction* inst);
 // Vector fractional multiply. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector
 // mask operand.
-void Vsmul(Instruction *inst);
+void Vsmul(Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_opm_instructions.cc b/cheriot/riscv_cheriot_vector_opm_instructions.cc
index 78617ef..ed00d80 100644
--- a/cheriot/riscv_cheriot_vector_opm_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_opm_instructions.cc

@@ -34,7 +34,7 @@
 
 // Helper function used to factor out some code from Vaadd* instructions.
 template <typename T>
-inline T VaaddHelper(CheriotVectorState *rv_vector, T vs2, T vs1) {
+inline T VaaddHelper(CheriotVectorState* rv_vector, T vs2, T vs1) {
   // Perform the addition using a wider type, then shift and round.
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
@@ -45,8 +45,8 @@
 
 // Average unsigned add. The two sources are added, then shifted right by one
 // and rounded.
-void Vaaddu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vaaddu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -78,8 +78,8 @@
 
 // Average signed add. The two sources are added, then shifted right by one and
 // rounded.
-void Vaadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vaadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -112,7 +112,7 @@
 // Helper function for Vasub* instructions. Subract using a wider type, then
 // round.
 template <typename T>
-inline T VasubHelper(CheriotVectorState *rv_vector, T vs2, T vs1) {
+inline T VasubHelper(CheriotVectorState* rv_vector, T vs2, T vs1) {
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
   WT vs1_w = static_cast<WT>(vs1);
@@ -121,8 +121,8 @@
 }
 
 // Averaging unsigned subtract - subtract then shift right by 1 and round.
-void Vasubu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vasubu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -153,8 +153,8 @@
 }
 
 // Averaging signed subtract. Subtract then shift right by 1 and round.
-void Vasub(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vasub(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -188,19 +188,19 @@
 // is used by the following bitwise mask manipulation instruction semantic
 // functions.
 static inline void BitwiseMaskBinaryOp(
-    CheriotVectorState *rv_vector, const Instruction *inst,
+    CheriotVectorState* rv_vector, const Instruction* inst,
     std::function<uint8_t(uint8_t, uint8_t)> op) {
   if (rv_vector->vector_exception()) return;
   int vstart = rv_vector->vstart();
   int vlen = rv_vector->vector_length();
   // Get spans for vector source and destination registers.
-  auto *vs2_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* vs2_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto vs2_span = vs2_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *vs1_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* vs1_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto vs1_span = vs1_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *vd_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *vd_db = vd_op->CopyDataBuffer();
+  auto* vd_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* vd_db = vd_op->CopyDataBuffer();
   auto vd_span = vd_db->Get<uint8_t>();
   // Compute start and end locations.
   int start_byte = vstart / 8;
@@ -226,51 +226,51 @@
 }
 
 // Bitwise vector mask instructions. The operation is clear by their name.
-void Vmandnot(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmandnot(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 & ~vs1;
   });
 }
 
-void Vmand(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmand(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 & vs1;
   });
 }
-void Vmor(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmor(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 | vs1;
   });
 }
-void Vmxor(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmxor(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 ^ vs1;
   });
 }
-void Vmornot(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmornot(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 | ~vs1;
   });
 }
-void Vmnand(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmnand(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 & vs1);
   });
 }
-void Vmnor(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmnor(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 | vs1);
   });
 }
-void Vmxnor(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmxnor(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 ^ vs1);
   });
@@ -278,8 +278,8 @@
 
 // Vector unsigned divide. Note, just like the scalar divide instruction, a
 // divide by zero does not cause an exception, instead it returns all 1s.
-void Vdivu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vdivu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -315,8 +315,8 @@
 
 // Signed divide. Divide by 0 returns all 1s. If -1 is divided by the largest
 // magnitude negative number, it returns that negative number.
-void Vdiv(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vdiv(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -363,8 +363,8 @@
 }
 
 // Unsigned remainder. If the denominator is 0, it returns the enumerator.
-void Vremu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vremu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -399,8 +399,8 @@
 }
 
 // Signed remainder. If the denominator is 0, it returns the enumerator.
-void Vrem(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vrem(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -447,8 +447,8 @@
 }
 
 // Multiply high, unsigned.
-void Vmulhu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmulhu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -480,8 +480,8 @@
 
 // Signed multiply. Note, that signed and unsigned multiply operations have the
 // same result for the low half of the product.
-void Vmul(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmul(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -533,8 +533,8 @@
 }
 
 // Multiply signed unsigned and return the high half.
-void Vmulhsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmulhsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -565,8 +565,8 @@
 }
 
 // Signed multiply, return high half.
-void Vmulh(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmulh(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -597,8 +597,8 @@
 }
 
 // Multiply-add.
-void Vmadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -636,8 +636,8 @@
 }
 
 // Negated multiply and add.
-void Vnmsub(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnmsub(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -674,8 +674,8 @@
 }
 
 // Multiply add overwriting the sum.
-void Vmacc(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmacc(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -712,8 +712,8 @@
 }
 
 // Negated multiply add, overwriting sum.
-void Vnmsac(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vnmsac(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -750,8 +750,8 @@
 }
 
 // Widening unsigned add.
-void Vwaddu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwaddu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -777,8 +777,8 @@
 }
 
 // Widening unsigned subtract.
-void Vwsubu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwsubu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -804,8 +804,8 @@
 }
 
 // Widening signed add.
-void Vwadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -844,8 +844,8 @@
 }
 
 // Widening signed subtract.
-void Vwsub(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwsub(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -883,8 +883,8 @@
 }
 
 // Widening unsigned add with wide source.
-void Vwadduw(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwadduw(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -917,8 +917,8 @@
 }
 
 // Widening unsigned subtract with wide source.
-void Vwsubuw(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwsubuw(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -951,8 +951,8 @@
 }
 
 // Widening signed add with wide source.
-void Vwaddw(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwaddw(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -985,8 +985,8 @@
 }
 
 // Widening signed subtract with wide source.
-void Vwsubw(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwsubw(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1029,8 +1029,8 @@
 }
 
 // Unsigned widening multiply.
-void Vwmulu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmulu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1076,8 +1076,8 @@
 }
 
 // Widening multiply signed-unsigned.
-void Vwmulsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmulsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1110,8 +1110,8 @@
 }
 
 // Widening signed multiply.
-void Vwmul(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmul(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1155,8 +1155,8 @@
 }
 
 // Unsigned widening multiply and add.
-void Vwmaccu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmaccu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1192,8 +1192,8 @@
 }
 
 // Widening signed multiply and add.
-void Vwmacc(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmacc(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1226,8 +1226,8 @@
 }
 
 // Widening unsigned-signed multiply and add.
-void Vwmaccus(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmaccus(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1262,8 +1262,8 @@
 }
 
 // Widening signed-unsigned multiply and add.
-void Vwmaccsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwmaccsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {

diff --git a/cheriot/riscv_cheriot_vector_opm_instructions.h b/cheriot/riscv_cheriot_vector_opm_instructions.h
index 9dbd61f..2b8fce4 100644
--- a/cheriot/riscv_cheriot_vector_opm_instructions.h
+++ b/cheriot/riscv_cheriot_vector_opm_instructions.h

@@ -27,151 +27,151 @@
 // Integer average unsigned add. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vaaddu(const Instruction *inst);
+void Vaaddu(const Instruction* inst);
 // Integer average signed add. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vaadd(const Instruction *inst);
+void Vaadd(const Instruction* inst);
 // Integer average unsigned subtract. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vasubu(const Instruction *inst);
+void Vasubu(const Instruction* inst);
 // Integer average signed subtract. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vasub(const Instruction *inst);
+void Vasub(const Instruction* inst);
 // The following instructions are vector mask logical operations. Each takes
 // two source operands, vs2 and vs1 vector registers, and one destination
 // operand, vd vector destination register.
-void Vmandnot(const Instruction *inst);
-void Vmand(const Instruction *inst);
-void Vmor(const Instruction *inst);
-void Vmxor(const Instruction *inst);
-void Vmornot(const Instruction *inst);
-void Vmnand(const Instruction *inst);
-void Vmnor(const Instruction *inst);
-void Vmxnor(const Instruction *inst);
+void Vmandnot(const Instruction* inst);
+void Vmand(const Instruction* inst);
+void Vmor(const Instruction* inst);
+void Vmxor(const Instruction* inst);
+void Vmornot(const Instruction* inst);
+void Vmnand(const Instruction* inst);
+void Vmnor(const Instruction* inst);
+void Vmxnor(const Instruction* inst);
 // Integer unsigned division. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vdivu(const Instruction *inst);
+void Vdivu(const Instruction* inst);
 // Integer signed division. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vdiv(const Instruction *inst);
+void Vdiv(const Instruction* inst);
 // Integer unsigned remainder. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vremu(const Instruction *inst);
+void Vremu(const Instruction* inst);
 // Integer signed remainder. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vrem(const Instruction *inst);
+void Vrem(const Instruction* inst);
 // Integer unsigned multiply high. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmulhu(const Instruction *inst);
+void Vmulhu(const Instruction* inst);
 // Integer signed multiply. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmul(const Instruction *inst);
+void Vmul(const Instruction* inst);
 // Integer signed-unsigned multiply high. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vmulhsu(const Instruction *inst);
+void Vmulhsu(const Instruction* inst);
 // Integer signed multiply high. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmulh(const Instruction *inst);
+void Vmulh(const Instruction* inst);
 // Integer multiply add (vs1 * vd) + vs2. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vmadd(const Instruction *inst);
+void Vmadd(const Instruction* inst);
 // Integer multiply subtract -(vs1 * vd) + vs2. This instruction takes 4
 // source operands and one destination operand. Source 0 is vs2, source 1 is vs1
 // (or rs1), source 2 is Vd as a source operand, and source 4 is vector mask.
 // The destination operand is the Vd register group.
-void Vnmsub(const Instruction *inst);
+void Vnmsub(const Instruction* inst);
 // Integer multiply add (vs1 * vs2) + vd. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vmacc(const Instruction *inst);
+void Vmacc(const Instruction* inst);
 // Integer multiply subtract -(vs1 * vs2) + vd. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vnmsac(const Instruction *inst);
+void Vnmsac(const Instruction* inst);
 // Integer widening unsigned addition. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwaddu(const Instruction *inst);
+void Vwaddu(const Instruction* inst);
 // Integer widening signed addition. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwadd(const Instruction *inst);
+void Vwadd(const Instruction* inst);
 // Integer widening unsigned subtraction. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwsubu(const Instruction *inst);
+void Vwsubu(const Instruction* inst);
 // Integer widening signed subtraction. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwsub(const Instruction *inst);
+void Vwsub(const Instruction* inst);
 // Integer widening unsigned addition with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwadduw(const Instruction *inst);
+void Vwadduw(const Instruction* inst);
 // Integer widening signed addition with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwaddw(const Instruction *inst);
+void Vwaddw(const Instruction* inst);
 // Integer widening unsigned subtraction with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwsubuw(const Instruction *inst);
+void Vwsubuw(const Instruction* inst);
 // Integer widening signed subtraction with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwsubw(const Instruction *inst);
+void Vwsubw(const Instruction* inst);
 // Integer widening unsigned multiplication. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwmulu(const Instruction *inst);
+void Vwmulu(const Instruction* inst);
 // Integer widening signed by unsigned multiplication. This instruction takes 3
 // source operands and one destination. Source 0 is vs2, source 1 is vs1 (or
 // rs1), and source 2 is vector mask. The destination operand is a vector
 // register group.
-void Vwmulsu(const Instruction *inst);
+void Vwmulsu(const Instruction* inst);
 // Integer widening signed multiplication. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwmul(const Instruction *inst);
+void Vwmul(const Instruction* inst);
 // Integer widening signed multiply and add (vs2 * vs1) + vd. This instruction
 // takes 4 source operands and one destination operand. Source 0 is vs2, source
 // 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source 4 is vector
 // mask. The destination operand is the Vd register group.
-void Vwmaccu(const Instruction *inst);
+void Vwmaccu(const Instruction* inst);
 // Integer widening unsigned multiply and add (vs2 * vs1) + vd. This instruction
 // takes 4 source operands and one destination operand. Source 0 is vs2, source
 // 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source 4 is vector
 // mask. The destination operand is the Vd register group.
-void Vwmacc(const Instruction *inst);
+void Vwmacc(const Instruction* inst);
 // Integer widening unsigned by signed multiply and add (vs2 * vs1) + vd. This
 // instruction takes 4 source operands and one destination operand. Source 0 is
 // vs2, source 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source
 // 4 is vector mask. The destination operand is the Vd register group.
-void Vwmaccus(const Instruction *inst);
+void Vwmaccus(const Instruction* inst);
 // Integer widening signed by unsigned multiply and add (vs2 * vs1) + vd. This
 // instruction takes 4 source operands and one destination operand. Source 0 is
 // vs2, source 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source
 // 4 is vector mask. The destination operand is the Vd register group.
-void Vwmaccsu(const Instruction *inst);
+void Vwmaccsu(const Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_permute_instructions.cc b/cheriot/riscv_cheriot_vector_permute_instructions.cc
index b5bad6e..1752087 100644
--- a/cheriot/riscv_cheriot_vector_permute_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_permute_instructions.cc

@@ -36,7 +36,7 @@
 
 // This helper function handles the vector gather operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void VrgatherHelper(CheriotVectorState *rv_vector, Instruction *inst) {
+void VrgatherHelper(CheriotVectorState* rv_vector, Instruction* inst) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
@@ -50,8 +50,8 @@
   }
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -61,7 +61,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -70,13 +70,13 @@
   int item_index = vector_index % elements_per_vector;
   // Determine if it's vector-vector or vector-scalar.
   bool vector_scalar = inst->Source(1)->shape()[0] == 1;
-  auto src0_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src0_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   int max_index = src0_op->size() * elements_per_vector;
   // Iterate over the number of registers to write.
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -111,8 +111,8 @@
 }
 
 // Vector register gather.
-void Vrgather(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vrgather(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -131,8 +131,8 @@
 }
 
 // Vector register gather with 16 bit indices.
-void Vrgatherei16(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vrgatherei16(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -152,7 +152,7 @@
 
 // This helper function handles the vector slide up/down instructions.
 template <typename Vd>
-void VSlideHelper(CheriotVectorState *rv_vector, Instruction *inst,
+void VSlideHelper(CheriotVectorState* rv_vector, Instruction* inst,
                   int offset) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -160,8 +160,8 @@
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -171,7 +171,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -182,7 +182,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -210,9 +210,9 @@
   rv_vector->clear_vstart();
 }
 
-void Vslideup(Instruction *inst) {
+void Vslideup(Instruction* inst) {
   using ValueType = CheriotRegister::ValueType;
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto offset = generic::GetInstructionSource<ValueType>(inst, 1, 0);
   int int_offset = static_cast<int>(offset);
@@ -234,9 +234,9 @@
   }
 }
 
-void Vslidedown(Instruction *inst) {
+void Vslidedown(Instruction* inst) {
   using ValueType = CheriotRegister::ValueType;
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto offset = generic::GetInstructionSource<ValueType>(inst, 1, 0);
   // Slide down amount is negative.
@@ -259,7 +259,7 @@
 
 // This helper function handles the vector slide up/down 1 instructions.
 template <typename Vd>
-void VSlide1Helper(CheriotVectorState *rv_vector, Instruction *inst,
+void VSlide1Helper(CheriotVectorState* rv_vector, Instruction* inst,
                    int offset) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -267,8 +267,8 @@
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -278,7 +278,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -290,7 +290,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -318,8 +318,8 @@
   rv_vector->clear_vstart();
 }
 
-void Vslide1up(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vslide1up(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -337,8 +337,8 @@
   }
 }
 
-void Vslide1down(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vslide1down(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -356,8 +356,8 @@
   }
 }
 
-void Vfslide1up(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfslide1up(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -371,8 +371,8 @@
   }
 }
 
-void Vfslide1down(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfslide1down(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -387,15 +387,15 @@
 }
 
 template <typename Vd>
-void VCompressHelper(CheriotVectorState *rv_vector, Instruction *inst) {
+void VCompressHelper(CheriotVectorState* rv_vector, Instruction* inst) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -405,7 +405,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -413,7 +413,7 @@
   int dest_index = 0;
   int prev_reg = -1;
   absl::Span<Vd> dest_span;
-  generic::DataBuffer *dest_db = nullptr;
+  generic::DataBuffer* dest_db = nullptr;
   // Iterate over the input elements.
   for (int i = vector_index; i < num_elements; i++) {
     // Get mask value.
@@ -441,8 +441,8 @@
   rv_vector->clear_vstart();
 }
 
-void Vcompress(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vcompress(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:

diff --git a/cheriot/riscv_cheriot_vector_permute_instructions.h b/cheriot/riscv_cheriot_vector_permute_instructions.h
index 9ccc612..2b70726 100644
--- a/cheriot/riscv_cheriot_vector_permute_instructions.h
+++ b/cheriot/riscv_cheriot_vector_permute_instructions.h

@@ -27,60 +27,60 @@
 // operands and one destination operand. Source 0 is the vector from which
 // elements are gathered, source 1 is the index vector, and source 2 is the
 // vector mask register. The destination operand is the target vector register.
-void Vrgather(Instruction *inst);
+void Vrgather(Instruction* inst);
 // Vector register gather instruction with 16 bit indices. This instruction
 // takes three source operands and one destination operand. Source 0 is the
 // vector from which elements are gathered, source 1 is the index vector, and
 // source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vrgatherei16(Instruction *inst);
+void Vrgatherei16(Instruction* inst);
 // Vector slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up. Source 1 is a scalar register or
 // immediate that specifies the number of 'entries' by which source 0 values
 // are slid up. Source 2 is the vector mask register. The destination operand
 // is the target vector register.
-void Vslideup(Instruction *inst);
+void Vslideup(Instruction* inst);
 // Vector slide down instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' down. Source 1 is a scalar register or
 // immediate that specifies the number of 'entries' by which source 0 values
 // are slid down. Source 2 is the vector mask register. The destination operand
 // is the target vector register.
-void Vslidedown(Instruction *inst);
+void Vslidedown(Instruction* inst);
 // Vector slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up by 1. Source 1 is a scalar register or
 // immediate that specifies the value written into the 'empty' slot. Source 2 is
 // the vector mask register. The destination operand is the target vector
 // register.
-void Vslide1up(Instruction *inst);
+void Vslide1up(Instruction* inst);
 // Vector slide down instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' down. Source 1 is a scalar register or
 // immediate that specifies the value written into the 'empty' slot. Source 2 is
 // the vector mask register. The destination operand is the target vector
 // register.
-void Vslide1down(Instruction *inst);
+void Vslide1down(Instruction* inst);
 // Vector fp slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up by 1. Source 1 is a floating point
 // register or immediate that specifies the value written into the 'empty' slot.
 // Source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vfslide1up(Instruction *inst);
+void Vfslide1up(Instruction* inst);
 // Vector fp slide down instruction. This instruction takes three source
 // operands and one destination operand. Source 0 is the vector source register
 // that contains the values that are 'slid' down. Source 1 is a floating point
 // register or immediate that specifies the value written into the 'empty' slot.
 // Source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vfslide1down(Instruction *inst);
+void Vfslide1down(Instruction* inst);
 // Vector compress instruction. This instruction takes two source operands and
 // one destination operand. Source 0 is the source value vector register. Source
 // 1 is a mask register, with specifies which elements of source 0 should be
 // selected and packed into the destination register.
-void Vcompress(Instruction *inst);
+void Vcompress(Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_reduction_instructions.cc b/cheriot/riscv_cheriot_vector_reduction_instructions.cc
index 8be7f68..83bb507 100644
--- a/cheriot/riscv_cheriot_vector_reduction_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_reduction_instructions.cc

@@ -29,8 +29,8 @@
 using ::mpact::sim::generic::Instruction;
 
 // Sum reduction.
-void Vredsum(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredsum(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -60,8 +60,8 @@
 }
 
 // And reduction.
-void Vredand(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredand(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -91,8 +91,8 @@
 }
 
 // Or reduction.
-void Vredor(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredor(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -122,8 +122,8 @@
 }
 
 // Xor reduction.
-void Vredxor(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredxor(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -153,8 +153,8 @@
 }
 
 // Unsigned min reduction.
-void Vredminu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredminu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -188,8 +188,8 @@
 }
 
 // Signed min reduction.
-void Vredmin(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredmin(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -222,8 +222,8 @@
 }
 
 // Unsigned max reduction.
-void Vredmaxu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredmaxu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -257,8 +257,8 @@
 }
 
 // Signed max reduction.
-void Vredmax(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vredmax(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -291,8 +291,8 @@
 }
 
 // Unsigned widening (SEW->SEW * 2) reduction.
-void Vwredsumu(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwredsumu(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -321,8 +321,8 @@
 }
 
 // Signed widening (SEW->SEW * 2) reduction.
-void Vwredsum(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vwredsum(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:

diff --git a/cheriot/riscv_cheriot_vector_reduction_instructions.h b/cheriot/riscv_cheriot_vector_reduction_instructions.h
index 58c93ae..eb5653e 100644
--- a/cheriot/riscv_cheriot_vector_reduction_instructions.h
+++ b/cheriot/riscv_cheriot_vector_reduction_instructions.h

@@ -31,25 +31,25 @@
 // result is written to the 0 element of destination operand vd.
 
 // Vector sum reduction.
-void Vredsum(Instruction *inst);
+void Vredsum(Instruction* inst);
 // Vector and reduction.
-void Vredand(Instruction *inst);
+void Vredand(Instruction* inst);
 // Vector or reduction.
-void Vredor(Instruction *inst);
+void Vredor(Instruction* inst);
 // Vector xor reduction.
-void Vredxor(Instruction *inst);
+void Vredxor(Instruction* inst);
 // Vector unsigned min reduction.
-void Vredminu(Instruction *inst);
+void Vredminu(Instruction* inst);
 // Vector signed min reduction.
-void Vredmin(Instruction *inst);
+void Vredmin(Instruction* inst);
 // Vector unsigned max reduction.
-void Vredmaxu(Instruction *inst);
+void Vredmaxu(Instruction* inst);
 // Vector signed max reduction.
-void Vredmax(Instruction *inst);
+void Vredmax(Instruction* inst);
 // Vector unsigned widening sum reduction. The result is 2 * SEW.
-void Vwredsumu(Instruction *inst);
+void Vwredsumu(Instruction* inst);
 // vector signed widening sum reduction. The result is 2 * SEW.
-void Vwredsum(Instruction *inst);
+void Vwredsum(Instruction* inst);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/riscv_cheriot_vector_unary_instructions.cc b/cheriot/riscv_cheriot_vector_unary_instructions.cc
index becf09a..00cf02e 100644
--- a/cheriot/riscv_cheriot_vector_unary_instructions.cc
+++ b/cheriot/riscv_cheriot_vector_unary_instructions.cc

@@ -37,8 +37,8 @@
                                           int64_t>::type;
 
 // Move scalar to vector register.
-void VmvToScalar(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void VmvToScalar(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
@@ -68,12 +68,12 @@
   WriteCapIntResult<SignedXregType>(inst, 0, value);
 }
 
-void VmvFromScalar(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void VmvFromScalar(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
-  auto *dest_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* dest_db = inst->Destination(0)->AllocateDataBuffer();
   std::memset(dest_db->raw_ptr(), 0, dest_db->size<uint8_t>());
   switch (sew) {
     case 1:
@@ -98,17 +98,17 @@
 
 // Population count of vector mask register. The value is written to a scalar
 // register.
-void Vcpop(Instruction *inst) {
-  auto *rv_state = static_cast<CheriotState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vcpop(Instruction* inst) {
+  auto* rv_state = static_cast<CheriotState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   uint64_t count = 0;
   for (int i = 0; i < vlen; i++) {
@@ -123,15 +123,15 @@
 
 // Find first set of vector mask register. The value is written to a scalar
 // register.
-void Vfirst(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vfirst(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Initialize the element index to -1.
   uint64_t element_index = -1LL;
@@ -150,8 +150,8 @@
 }
 
 // Vector integer sign and zero extension instructions.
-void Vzext2(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vzext2(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 2:
@@ -173,8 +173,8 @@
   }
 }
 
-void Vsext2(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsext2(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 2:
@@ -196,8 +196,8 @@
   }
 }
 
-void Vzext4(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vzext4(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -215,8 +215,8 @@
   }
 }
 
-void Vsext4(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsext4(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -234,8 +234,8 @@
   }
 }
 
-void Vzext8(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vzext8(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 8:
@@ -249,8 +249,8 @@
   }
 }
 
-void Vsext8(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vsext8(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 8:
@@ -265,20 +265,20 @@
 }
 
 // Vector mask set-before-first mask bit.
-void Vmsbf(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsbf(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   bool before_first = true;
   int last = 0;
@@ -307,20 +307,20 @@
 }
 
 // Vector mask set-including-first mask bit.
-void Vmsif(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsif(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   uint8_t value = 1;
   for (int i = 0; i < vlen; i++) {
@@ -344,20 +344,20 @@
 }
 
 // Vector maks set-only-first mask bit.
-void Vmsof(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vmsof(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   bool first = true;
   for (int i = 0; i < vlen; i++) {
@@ -382,8 +382,8 @@
 // writes to each element of the destination vector register group the sum
 // of all bits of elements in the mask register whose index is less than the
 // element. This is subject to masking.
-void Viota(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Viota(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   int count = 0;
   switch (sew) {
@@ -420,8 +420,8 @@
 
 // Writes the index of each active (mask true) element to the destination
 // vector elements.
-void Vid(Instruction *inst) {
-  auto *rv_vector = static_cast<CheriotState *>(inst->state())->rv_vector();
+void Vid(Instruction* inst) {
+  auto* rv_vector = static_cast<CheriotState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   int index = 0;
   switch (sew) {

diff --git a/cheriot/riscv_cheriot_vector_unary_instructions.h b/cheriot/riscv_cheriot_vector_unary_instructions.h
index 4043a11..89f44e7 100644
--- a/cheriot/riscv_cheriot_vector_unary_instructions.h
+++ b/cheriot/riscv_cheriot_vector_unary_instructions.h

@@ -29,46 +29,46 @@
 // Moves a value from index 0 element of a vector register to a scalar register.
 // This instruction takes 1 source and 1 destination. One is a vector register,
 // the other is a scalar (x) register.
-void VmvToScalar(Instruction *inst);
+void VmvToScalar(Instruction* inst);
 // Moves a scalar to index 0 element of a vector register. This instruction
 // takes 1 source and 1 destination. One is a vector register, the other is
 // a scalar (x) register.
-void VmvFromScalar(Instruction *inst);
+void VmvFromScalar(Instruction* inst);
 // Does a population count on the vector mask in the source operand 0 (subject
 // to masking), and writes the result to the scalar register in the destination
 // operand. Operand 1 is a mask register. Only vlen bits are considered.
-void Vcpop(Instruction *inst);
+void Vcpop(Instruction* inst);
 // Computes the index of the first set bit of the vector mask in the source
 // operand 0 (subject ot masking), and writes the result to the scalar register
 // in the destination operand. Operand 1 is a mask register. Only vlen bits
 // are considered.
-void Vfirst(Instruction *inst);
+void Vfirst(Instruction* inst);
 
 // VXUNARY0
 // Element wide zero extend from SEW/2 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext2(Instruction *inst);
+void Vzext2(Instruction* inst);
 // Element wide sign extend from SEW/2 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext2(Instruction *inst);
+void Vsext2(Instruction* inst);
 // Element wide zero extend from SEW/4 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext4(Instruction *inst);
+void Vzext4(Instruction* inst);
 // Element wide sign extend from SEW/4 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext4(Instruction *inst);
+void Vsext4(Instruction* inst);
 // Element wide zero extend from SEW/8 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext8(Instruction *inst);
+void Vzext8(Instruction* inst);
 // Element wide sign extend from SEW/8 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext8(Instruction *inst);
+void Vsext8(Instruction* inst);
 
 // VMUNARY0
 // Set before first mask bit. Takes a vector mask stored in a vector register
@@ -76,32 +76,32 @@
 // bit in the source mask set to 1. This instruction takes one vector source
 // operands, a mask register, and a vector destination operand. Source 0 is the
 // vs2 register source, source 1 is the vector mask operand.
-void Vmsbf(Instruction *inst);
+void Vmsbf(Instruction* inst);
 // Set only first mask bit. Takes a vector mask stored in a vector register
 // and produces a mask register with only the bit set that corresponds to the
 // the first set active bit in the source mask set to 1. This instruction takes
 // one vector source operands, a mask register, and a vector destination
 // operand. Source 0 is the vs2 register source, source 1 is the vector mask
 // operand.
-void Vmsof(Instruction *inst);
+void Vmsof(Instruction* inst);
 // Set including first mask bit. Takes a vector mask stored in a vector register
 // and produces a mask register with all active bits before and including the
 // first set active bit in the source mask set to 1. This instruction takes one
 // vector source operands, a mask register, and a vector destination operand.
 // Source 0 is the vs2 register source, source 1 is the vector mask operand.
-void Vmsif(Instruction *inst);
+void Vmsif(Instruction* inst);
 // Vector Iota instruction. Takes a vector mask stored in a vector register
 // and writes to each element of the destination vector register group the sum
 // of all bits of elements in the mask register whose index is less than the
 // element (parallel prefix sum). This instruction takes two sources and one
 // destination. Source 0 is the vs2 register source, source 1 is the vector
 // mask operand.
-void Viota(Instruction *inst);
+void Viota(Instruction* inst);
 // Vector element index instruction. Writes the element index to the destination
 // vector element group (masking does not change the value written to active
 // elements, only which elements are written to). This instruction takes 1
 // source (mask register) and one destination.
-void Vid(Instruction *inst);
+void Vid(Instruction* inst);
 }  // namespace cheriot
 }  // namespace sim
 }  // namespace mpact

diff --git a/cheriot/riscv_cheriot_zicsr_instructions.cc b/cheriot/riscv_cheriot_zicsr_instructions.cc
index 16649b9..7225273 100644
--- a/cheriot/riscv_cheriot_zicsr_instructions.cc
+++ b/cheriot/riscv_cheriot_zicsr_instructions.cc

@@ -42,40 +42,40 @@
 using ::mpact::sim::generic::RegisterBase;
 
 // Helper to get capability destination registers.
-static inline CapReg *GetCapDest(const Instruction *instruction, int i) {
-  return static_cast<CapReg *>(
-      std::any_cast<RegisterBase *>(instruction->Destination(i)->GetObject()));
+static inline CapReg* GetCapDest(const Instruction* instruction, int i) {
+  return static_cast<CapReg*>(
+      std::any_cast<RegisterBase*>(instruction->Destination(i)->GetObject()));
 }
 
 // Writing an integer result requires invalidating the capability and setting
 // it to null.
 template <typename Result>
-static inline void WriteCapIntResult(const Instruction *instruction, int i,
+static inline void WriteCapIntResult(const Instruction* instruction, int i,
                                      Result value) {
-  auto *cap_reg = GetCapDest(instruction, i);
+  auto* cap_reg = GetCapDest(instruction, i);
   cap_reg->data_buffer()->Set<Result>(0, value);
   cap_reg->Invalidate();
   cap_reg->set_is_null();
 }
 
 template <typename T>
-inline T ReadCsr(RiscVCsrInterface *) {}
+inline T ReadCsr(RiscVCsrInterface*) {}
 
 template <>
-inline uint32_t ReadCsr<uint32_t>(RiscVCsrInterface *csr) {
+inline uint32_t ReadCsr<uint32_t>(RiscVCsrInterface* csr) {
   return csr->AsUint32();
 }
 template <>
-inline uint64_t ReadCsr<uint64_t>(RiscVCsrInterface *csr) {
+inline uint64_t ReadCsr<uint64_t>(RiscVCsrInterface* csr) {
   return csr->AsUint64();
 }
 
 // Helper function to check that the CSR permission is valid. If not, throw
 // an illegal instruction exception.
-bool CheckCsrPermission(int csr_index, Instruction *instruction,
+bool CheckCsrPermission(int csr_index, Instruction* instruction,
                         bool is_write) {
   auto required_mode = (csr_index >> 8) & 0x3;
-  auto *state = static_cast<CheriotState *>(instruction->state());
+  auto* state = static_cast<CheriotState*>(instruction->state());
   auto current_mode = PrivilegeMode::kMachine;
   // If the register isn't available in CHERIoT, throw an exception.
   if (required_mode == *PrivilegeMode::kSupervisor) {
@@ -116,9 +116,9 @@
 
 // Read the CSR, write a new value back.
 template <typename T>
-static inline void RVZiCsrrw(Instruction *instruction) {
+static inline void RVZiCsrrw(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<CheriotState *>(instruction->state());
+  auto state = static_cast<CheriotState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction, /*is_write=*/true)) return;
@@ -134,7 +134,7 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Update the register.
   auto csr_val = ReadCsr<T>(csr);
   WriteCapIntResult(instruction, 0, csr_val);
@@ -144,9 +144,9 @@
 
 // Read the CSR, set the bits specified by the new value and write back.
 template <typename T>
-static inline void RVZiCsrrs(Instruction *instruction) {
+static inline void RVZiCsrrs(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<CheriotState *>(instruction->state());
+  auto state = static_cast<CheriotState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction, /*is_write=*/true)) return;
@@ -162,7 +162,7 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Update the register.
   auto csr_val = ReadCsr<T>(csr);
   WriteCapIntResult(instruction, 0, csr_val);
@@ -172,9 +172,9 @@
 
 // Read the CSR, clear the bits specified by the new value and write back.
 template <typename T>
-static inline void RVZiCsrrc(Instruction *instruction) {
+static inline void RVZiCsrrc(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<CheriotState *>(instruction->state());
+  auto state = static_cast<CheriotState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction, /*is_write=*/true)) return;
@@ -190,7 +190,7 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Write the current value of the CSR to the destination register.
   auto csr_val = ReadCsr<T>(csr);
   WriteCapIntResult(instruction, 0, csr_val);
@@ -200,9 +200,9 @@
 
 // Do not read the CSR, just write the new value back.
 template <typename T>
-static inline void RVZiCsrrwNr(Instruction *instruction) {
+static inline void RVZiCsrrwNr(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<CheriotState *>(instruction->state());
+  auto state = static_cast<CheriotState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction, /*is_write=*/true)) return;
@@ -215,7 +215,7 @@
                                ": ", result.status().message());
     return;
   }
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Write the new value to the csr.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
   csr->Write(new_value);
@@ -223,9 +223,9 @@
 
 // Do not write a value back to the CSR, just read it.
 template <typename T>
-static inline void RVZiCsrrNw(Instruction *instruction) {
+static inline void RVZiCsrrNw(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<CheriotState *>(instruction->state());
+  auto state = static_cast<CheriotState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(0)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction, /*is_write=*/false)) return;
@@ -239,7 +239,7 @@
     return;
   }
   // Get the CSR object.
-  auto *csr = result.value();
+  auto* csr = result.value();
   auto csr_val = ReadCsr<T>(csr);
   WriteCapIntResult(instruction, 0, csr_val);
 }
@@ -248,21 +248,21 @@
 using UintReg = RegisterType::ValueType;
 
 // Read the CSR, write a new value back.
-void RiscVZiCsrrw(Instruction *instruction) { RVZiCsrrw<UintReg>(instruction); }
+void RiscVZiCsrrw(Instruction* instruction) { RVZiCsrrw<UintReg>(instruction); }
 
 // Read the CSR, set the bits specified by the new value and write back.
-void RiscVZiCsrrs(Instruction *instruction) { RVZiCsrrs<UintReg>(instruction); }
+void RiscVZiCsrrs(Instruction* instruction) { RVZiCsrrs<UintReg>(instruction); }
 
 // Read the CSR, clear the bits specified by the new value and write back.
-void RiscVZiCsrrc(Instruction *instruction) { RVZiCsrrc<UintReg>(instruction); }
+void RiscVZiCsrrc(Instruction* instruction) { RVZiCsrrc<UintReg>(instruction); }
 
 // Do not read the CSR, just write the new value back.
-void RiscVZiCsrrwNr(Instruction *instruction) {
+void RiscVZiCsrrwNr(Instruction* instruction) {
   RVZiCsrrwNr<UintReg>(instruction);
 }
 
 // Do not write a value back to the CSR, just read it.
-void RiscVZiCsrrNw(Instruction *instruction) {
+void RiscVZiCsrrNw(Instruction* instruction) {
   RVZiCsrrNw<UintReg>(instruction);
 }
 

diff --git a/cheriot/riscv_cheriot_zicsr_instructions.h b/cheriot/riscv_cheriot_zicsr_instructions.h
index 763785c..44d6cc4 100644
--- a/cheriot/riscv_cheriot_zicsr_instructions.h
+++ b/cheriot/riscv_cheriot_zicsr_instructions.h

@@ -25,11 +25,11 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVZiCsrrw(Instruction *instruction);
-void RiscVZiCsrrs(Instruction *instruction);
-void RiscVZiCsrrc(Instruction *instruction);
-void RiscVZiCsrrwNr(Instruction *instruction);
-void RiscVZiCsrrNw(Instruction *instruction);
+void RiscVZiCsrrw(Instruction* instruction);
+void RiscVZiCsrrs(Instruction* instruction);
+void RiscVZiCsrrc(Instruction* instruction);
+void RiscVZiCsrrwNr(Instruction* instruction);
+void RiscVZiCsrrNw(Instruction* instruction);
 
 }  // namespace cheriot
 }  // namespace sim

diff --git a/cheriot/test/BUILD b/cheriot/test/BUILD
index b8420f6..4539463 100644
--- a/cheriot/test/BUILD
+++ b/cheriot/test/BUILD

@@ -368,6 +368,7 @@
         "@com_google_absl//absl/strings",
         "@com_google_googletest//:gtest_main",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
+        "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
     ],
 )
 
@@ -384,6 +385,7 @@
         "//cheriot:riscv_cheriot_vector",
         "@com_google_absl//absl/random",
         "@com_google_absl//absl/strings",
+        "@com_google_absl//absl/types:span",
         "@com_google_googletest//:gtest_main",
         "@com_google_mpact-riscv//riscv:riscv_state",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",

diff --git a/cheriot/test/cheriot_ibex_hw_revoker_test.cc b/cheriot/test/cheriot_ibex_hw_revoker_test.cc
index cde592b..38fc602 100644
--- a/cheriot/test/cheriot_ibex_hw_revoker_test.cc
+++ b/cheriot/test/cheriot_ibex_hw_revoker_test.cc

@@ -65,35 +65,35 @@
 class MemoryViewer : public TaggedMemoryInterface {
  public:
   MemoryViewer() = delete;
-  MemoryViewer(TaggedMemoryInterface *memory) : memory_(memory) {}
+  MemoryViewer(TaggedMemoryInterface* memory) : memory_(memory) {}
   ~MemoryViewer() override = default;
 
-  void Load(uint64_t address, DataBuffer *db, DataBuffer *tags,
-            Instruction *inst, ReferenceCount *context) override {
+  void Load(uint64_t address, DataBuffer* db, DataBuffer* tags,
+            Instruction* inst, ReferenceCount* context) override {
     ld_address_ = address;
     memory_->Load(address, db, tags, inst, context);
   }
-  void Load(uint64_t address, DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override {
+  void Load(uint64_t address, DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override {
     ld_address_ = address;
     memory_->Load(address, db, inst, context);
   }
-  void Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-            DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override {
+  void Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+            DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override {
     ld_address_ = address_db->Get<uint64_t>(0);
     memory_->Load(address_db, mask_db, el_size, db, inst, context);
   }
-  void Store(uint64_t address, DataBuffer *db, DataBuffer *tags) override {
+  void Store(uint64_t address, DataBuffer* db, DataBuffer* tags) override {
     st_address_ = address;
     memory_->Store(address, db, tags);
   }
-  void Store(uint64_t address, DataBuffer *db) override {
+  void Store(uint64_t address, DataBuffer* db) override {
     st_address_ = address;
     memory_->Store(address, db);
   }
-  void Store(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-             DataBuffer *db) override {
+  void Store(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+             DataBuffer* db) override {
     st_address_ = address_db->Get<uint64_t>(0);
     memory_->Store(address_db, mask_db, el_size, db);
   }
@@ -102,7 +102,7 @@
   uint64_t st_address() const { return st_address_; }
 
  private:
-  TaggedMemoryInterface *memory_ = nullptr;
+  TaggedMemoryInterface* memory_ = nullptr;
   uint64_t ld_address_ = 0;
   uint64_t st_address_ = 0;
 };
@@ -237,7 +237,7 @@
   }
 
   // Convenience method to read a capability from memory with the given base.
-  CheriotRegister *ReadCapability(uint64_t address) {
+  CheriotRegister* ReadCapability(uint64_t address) {
     heap_memory_->Load(address, db8_, db1_, nullptr, nullptr);
     cap_reg_->Expand(db8_->Get<uint32_t>(0), db8_->Get<uint32_t>(1),
                      db1_->Get<uint8_t>(0));
@@ -246,21 +246,21 @@
 
   uint64_t GetLoadAddress() { return memory_viewer_->ld_address(); }
   uint64_t GetStoreAddress() { return memory_viewer_->st_address(); }
-  MockPlicSource *plic_irq() { return plic_irq_; }
+  MockPlicSource* plic_irq() { return plic_irq_; }
 
  private:
-  CheriotRegister *cap_reg_ = nullptr;
+  CheriotRegister* cap_reg_ = nullptr;
   DataBufferFactory db_factory_;
-  DataBuffer *db1_;
-  DataBuffer *db4_;
-  DataBuffer *db8_;
-  DataBuffer *db128_;
-  DataBuffer *cap_db_;
-  CheriotIbexHWRevoker *revoker_ = nullptr;
-  MockPlicSource *plic_irq_ = nullptr;
-  TaggedFlatDemandMemory *heap_memory_ = nullptr;
-  FlatDemandMemory *revocation_memory_ = nullptr;
-  MemoryViewer *memory_viewer_ = nullptr;
+  DataBuffer* db1_;
+  DataBuffer* db4_;
+  DataBuffer* db8_;
+  DataBuffer* db128_;
+  DataBuffer* cap_db_;
+  CheriotIbexHWRevoker* revoker_ = nullptr;
+  MockPlicSource* plic_irq_ = nullptr;
+  TaggedFlatDemandMemory* heap_memory_ = nullptr;
+  FlatDemandMemory* revocation_memory_ = nullptr;
+  MemoryViewer* memory_viewer_ = nullptr;
 };
 
 // Initial state should all be clear.
@@ -303,7 +303,7 @@
   // Write a capability at the sweep base.
   for (auto offset = 0; offset < 0x100; offset += 0x8) {
     WriteCapability(kSweepBase + offset, kHeapBase + offset);
-    auto *cap = ReadCapability(kSweepBase);
+    auto* cap = ReadCapability(kSweepBase);
     EXPECT_TRUE(cap->tag());
   }
   // Revoke one capability.
@@ -324,7 +324,7 @@
   EXPECT_EQ(GetStatus(), 0);
   // Verify that only the one revoked capability was invalidated.
   for (auto offset = 0; offset < 0x100; offset += 0x8) {
-    auto *cap = ReadCapability(kSweepBase + offset);
+    auto* cap = ReadCapability(kSweepBase + offset);
     if (offset == 0x20) {
       EXPECT_FALSE(cap->tag());
     } else {
@@ -337,7 +337,7 @@
   // Write a capability at the sweep base.
   for (auto offset = 0; offset < 0x100; offset += 0x8) {
     WriteCapability(kSweepBase + offset, kHeapBase + offset);
-    auto *cap = ReadCapability(kSweepBase);
+    auto* cap = ReadCapability(kSweepBase);
     EXPECT_TRUE(cap->tag());
   }
   // Revoke one capability.

diff --git a/cheriot/test/cheriot_load_filter_test.cc b/cheriot/test/cheriot_load_filter_test.cc
index 232ccd6..c6f6b16 100644
--- a/cheriot/test/cheriot_load_filter_test.cc
+++ b/cheriot/test/cheriot_load_filter_test.cc

@@ -137,8 +137,8 @@
 
  protected:
   DataBufferFactory db_factory_;
-  DataBuffer *db_;
-  DataBuffer *tag_db_;
+  DataBuffer* db_;
+  DataBuffer* tag_db_;
   SimpleCounter<uint64_t> counter_;
   CheriotRegister cap_reg_;
   std::unique_ptr<TaggedMemoryInterface> memory_;

diff --git a/cheriot/test/cheriot_state_test.cc b/cheriot/test/cheriot_state_test.cc
index 85c728e..b6bdeb9 100644
--- a/cheriot/test/cheriot_state_test.cc
+++ b/cheriot/test/cheriot_state_test.cc

@@ -43,17 +43,17 @@
 TEST(CheriotStateTest, Basic) {
   TaggedFlatDemandMemory mem(8);
 
-  auto *state = new CheriotState("test", &mem, nullptr);
+  auto* state = new CheriotState("test", &mem, nullptr);
   // Make sure pc has been created.
   auto iter = state->registers()->find("pcc");
-  auto *ptr = (iter != state->registers()->end()) ? iter->second : nullptr;
+  auto* ptr = (iter != state->registers()->end()) ? iter->second : nullptr;
   CHECK_NE(ptr, nullptr);
-  auto *pcc = static_cast<CheriotRegister *>(ptr);
+  auto* pcc = static_cast<CheriotRegister*>(ptr);
   // Make pcc an executable root.
   pcc->CopyFrom(*state->executable_root());
   // Set pc to 0x1000, then read value back through pc operand.
   pcc->data_buffer()->Set<uint32_t>(0, kPcValue);
-  auto *pc_op = state->pc_operand();
+  auto* pc_op = state->pc_operand();
   EXPECT_EQ(pc_op->AsUint32(0), kPcValue);
   delete state;
 }
@@ -61,8 +61,8 @@
 TEST(CheriotStateTest, Memory) {
   TaggedFlatDemandMemory mem(8);
 
-  auto *state = new CheriotState("test", &mem, nullptr);
-  auto *db = state->db_factory()->Allocate<uint32_t>(1);
+  auto* state = new CheriotState("test", &mem, nullptr);
+  auto* db = state->db_factory()->Allocate<uint32_t>(1);
   state->LoadMemory(nullptr, kMemAddr, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), 0);
   db->Set<uint32_t>(0, kMemValue);
@@ -77,11 +77,11 @@
 TEST(CheriotStateTest, OutOfBoundLoad) {
   TaggedFlatDemandMemory mem(8);
 
-  auto *state = new CheriotState("test", &mem, nullptr);
+  auto* state = new CheriotState("test", &mem, nullptr);
   state->set_max_physical_address(kMemAddr - 4);
   state->set_on_trap([](bool is_interrupt, uint64_t trap_value,
                         uint64_t exception_code, uint64_t epc,
-                        const mpact::sim::riscv::Instruction *inst) -> bool {
+                        const mpact::sim::riscv::Instruction* inst) -> bool {
     if (exception_code ==
         static_cast<uint64_t>(
             mpact::sim::riscv::ExceptionCode::kLoadAccessFault)) {
@@ -90,9 +90,9 @@
     }
     return false;
   });
-  auto *db = state->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state->db_factory()->Allocate<uint32_t>(1);
   // Create a dummy instruction so trap can dereference the address.
-  auto *dummy_inst = new mpact::sim::generic::Instruction(0x0, nullptr);
+  auto* dummy_inst = new mpact::sim::generic::Instruction(0x0, nullptr);
   dummy_inst->set_size(4);
   testing::internal::CaptureStderr();
   state->LoadMemory(dummy_inst, kMemAddr, db, nullptr, nullptr);
@@ -105,15 +105,15 @@
 
 // Verify that the mshwm register decrements by 16.
 TEST(CheriotStateTest, Mshwm) {
-  auto *mem = new mpact::sim::util::TaggedFlatDemandMemory(8);
-  auto *state = new CheriotState("test", mem);
-  auto *byte_db = state->db_factory()->Allocate<uint8_t>(1);
+  auto* mem = new mpact::sim::util::TaggedFlatDemandMemory(8);
+  auto* state = new CheriotState("test", mem);
+  auto* byte_db = state->db_factory()->Allocate<uint8_t>(1);
   auto mshwmb_res = state->csr_set()->GetCsr("mshwmb");
   CHECK_OK(mshwmb_res);
-  auto *mshwmb = mshwmb_res.value();
+  auto* mshwmb = mshwmb_res.value();
   auto mshwm_res = state->csr_set()->GetCsr("mshwm");
   CHECK_OK(mshwm_res);
-  auto *mshwm = mshwm_res.value();
+  auto* mshwm = mshwm_res.value();
   mshwmb->Write(0x0U);
   mshwm->Write(0x80000000);
   state->StoreMemory(nullptr, 0x7fff'ffff, byte_db);

diff --git a/cheriot/test/librenode_mpact_cheriot_so_test.cc b/cheriot/test/librenode_mpact_cheriot_so_test.cc
index 15f06cb..736c48f 100644
--- a/cheriot/test/librenode_mpact_cheriot_so_test.cc
+++ b/cheriot/test/librenode_mpact_cheriot_so_test.cc

@@ -24,7 +24,7 @@
 
   ~LibRenodeMpactCheriotSoTest() { dlclose(lib_); }
 
-  void *lib_ = nullptr;
+  void* lib_ = nullptr;
 };
 
 TEST_F(LibRenodeMpactCheriotSoTest, Construct) {

diff --git a/cheriot/test/riscv_cheriot_a_instructions_test.cc b/cheriot/test/riscv_cheriot_a_instructions_test.cc
index 27388d9..d9819f2 100644
--- a/cheriot/test/riscv_cheriot_a_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_a_instructions_test.cc

@@ -104,21 +104,21 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
@@ -126,9 +126,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -147,7 +147,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
     if (std::is_signed<T>::value) {
       return static_cast<T>(reg->data_buffer()->Get<int32_t>(0));
     } else {
@@ -155,12 +155,12 @@
     }
   }
 
-  DataBuffer *db_w_;
-  TaggedFlatDemandMemory *memory_;
-  AtomicMemory *atomic_memory_;
-  CheriotState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
+  DataBuffer* db_w_;
+  TaggedFlatDemandMemory* memory_;
+  AtomicMemory* atomic_memory_;
+  CheriotState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
 };
 
 TEST_F(RiscVAInstructionsTest, ALrw) {

diff --git a/cheriot/test/riscv_cheriot_encoding_test.cc b/cheriot/test/riscv_cheriot_encoding_test.cc
index 33616e7..c947393 100644
--- a/cheriot/test/riscv_cheriot_encoding_test.cc
+++ b/cheriot/test/riscv_cheriot_encoding_test.cc

@@ -200,9 +200,9 @@
     delete state_;
   }
 
-  TaggedFlatDemandMemory *mem_;
-  CheriotState *state_;
-  RiscVCheriotEncoding *enc_;
+  TaggedFlatDemandMemory* mem_;
+  CheriotState* state_;
+  RiscVCheriotEncoding* enc_;
 };
 
 constexpr int kRdValue = 1;
@@ -229,7 +229,7 @@
 }
 
 TEST_F(RiscVCheriotEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -237,7 +237,7 @@
 }
 
 TEST_F(RiscVCheriotEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";

diff --git a/cheriot/test/riscv_cheriot_i_instructions_test.cc b/cheriot/test/riscv_cheriot_i_instructions_test.cc
index d5ab010..e5659ae 100644
--- a/cheriot/test/riscv_cheriot_i_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_i_instructions_test.cc

@@ -73,7 +73,7 @@
     creg_3_ = state_->GetRegister<CheriotRegister>(kC3).first;
     state_->set_on_trap([this](bool is_interrupt, uint64_t trap_value,
                                uint64_t exception_code, uint64_t epc,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
       return TrapHandler(is_interrupt, trap_value, exception_code, epc, inst);
     });
   }
@@ -86,29 +86,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
+  void AppendRegisterOperands(Instruction* inst,
                               absl::Span<const std::string> sources,
                               absl::Span<const std::string> destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -117,8 +117,8 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       reg->set_address(value);
     }
   }
@@ -131,33 +131,33 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(std::string_view reg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
     return reg->address();
   }
   // Gets called on a trap.
   bool TrapHandler(bool is_interrupt, uint64_t trap_value,
                    uint64_t exception_code, uint64_t epc,
-                   const Instruction *inst);
+                   const Instruction* inst);
 
-  TaggedFlatDemandMemory *mem_;
-  CheriotState *state_;
-  Instruction *instruction_;
-  CheriotRegister *creg_1_;
-  CheriotRegister *creg_2_;
-  CheriotRegister *creg_3_;
+  TaggedFlatDemandMemory* mem_;
+  CheriotState* state_;
+  Instruction* instruction_;
+  CheriotRegister* creg_1_;
+  CheriotRegister* creg_2_;
+  CheriotRegister* creg_3_;
   bool trap_taken_ = false;
   bool trap_is_interrupt_ = false;
   uint64_t trap_value_ = 0;
   uint64_t trap_exception_code_ = 0;
   uint64_t trap_epc_ = 0;
-  const Instruction *trap_inst_ = nullptr;
+  const Instruction* trap_inst_ = nullptr;
 };
 
 bool RVCheriotIInstructionTest::TrapHandler(bool is_interrupt,
                                             uint64_t trap_value,
                                             uint64_t exception_code,
                                             uint64_t epc,
-                                            const Instruction *inst) {
+                                            const Instruction* inst) {
   trap_taken_ = true;
   trap_is_interrupt_ = is_interrupt;
   trap_value_ = trap_value;
@@ -489,7 +489,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILw) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -498,7 +498,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -519,7 +519,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILwTagViolation) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -528,7 +528,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -549,7 +549,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILwSealViolation) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -558,7 +558,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -580,7 +580,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILwPermitLoadViolation) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -589,7 +589,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -611,7 +611,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILwBoundsViolation) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -620,7 +620,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -642,7 +642,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILh) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -651,7 +651,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILh);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILhChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -672,7 +672,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILhu) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -681,7 +681,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILhu);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILhuChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -702,7 +702,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILb) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -711,7 +711,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILb);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILbChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -732,7 +732,7 @@
 
 TEST_F(RVCheriotIInstructionTest, RV32ILbu) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -741,7 +741,7 @@
   AppendRegisterOperands({kC1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::cheriot::RiscVILbu);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::cheriot::RiscVILbuChild);
   AppendRegisterOperands(child, {}, {kC3});
   instruction_->AppendChild(child);
@@ -772,7 +772,7 @@
   SetRegisterValues<uint32_t>({{kC1, kMemAddress}, {kC3, kMemValue}});
   instruction_->Execute(nullptr);
   EXPECT_FALSE(trap_taken_);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -787,7 +787,7 @@
   SetRegisterValues<uint32_t>({{kC1, kMemAddress}, {kC3, kMemValue}});
   creg_1_->Invalidate();
   instruction_->Execute(nullptr);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_NE(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -809,7 +809,7 @@
   SetRegisterValues<uint32_t>({{kC1, kMemAddress}, {kC3, kMemValue}});
   (void)creg_1_->Seal(*state_->sealing_root(), 9);
   instruction_->Execute(nullptr);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_NE(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -831,7 +831,7 @@
   creg_1_->ClearPermissions(PB::kPermitStore);
   SetRegisterValues<uint32_t>({{kC1, kMemAddress}, {kC3, kMemValue}});
   instruction_->Execute(nullptr);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_NE(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -854,7 +854,7 @@
   creg_1_->SetBounds(kMemAddress, kOffset - 0x100);
   creg_3_->ResetMemoryRoot();
   instruction_->Execute(nullptr);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_NE(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -877,7 +877,7 @@
   instruction_->Execute(nullptr);
   EXPECT_FALSE(trap_taken_);
 
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), static_cast<uint16_t>(kMemValue));
   db->DecRef();
@@ -893,7 +893,7 @@
   instruction_->Execute(nullptr);
   EXPECT_FALSE(trap_taken_);
 
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), static_cast<uint8_t>(kMemValue));
   db->DecRef();

diff --git a/cheriot/test/riscv_cheriot_instructions_test.cc b/cheriot/test/riscv_cheriot_instructions_test.cc
index 60aeb85..0dfc98c 100644
--- a/cheriot/test/riscv_cheriot_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_instructions_test.cc

@@ -112,8 +112,8 @@
     memory_ = new TaggedFlatDemandMemory(kCapabilityGranule);
     state_ = new CheriotState("test_state", memory_);
     ResetInstruction(kInstSizeNormal);
-    for (auto &[reg_name, cap_reg_ptr] :
-         std::vector<std::tuple<std::string, CheriotRegister **>>{
+    for (auto& [reg_name, cap_reg_ptr] :
+         std::vector<std::tuple<std::string, CheriotRegister**>>{
              {kC1, &c1_reg_},
              {kC2, &c2_reg_},
              {kC3, &c3_reg_},
@@ -124,7 +124,7 @@
     }
     state_->set_on_trap([this](bool is_interrupt, uint64_t trap_value,
                                uint64_t exception_code, uint64_t epc,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
       return TrapHandler(is_interrupt, trap_value, exception_code, epc, inst);
     });
   }
@@ -139,32 +139,32 @@
   // information for checks.
   bool TrapHandler(bool is_interrupt, uint64_t trap_value,
                    uint64_t exception_code, uint64_t epc,
-                   const Instruction *inst);
+                   const Instruction* inst);
   // Clear the captured trap values.
   void ResetTrapHandler();
 
-  void AppendCapabilityOperands(Instruction *inst,
+  void AppendCapabilityOperands(Instruction* inst,
                                 absl::Span<const std::string> sources,
                                 absl::Span<const std::string> dests) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand(reg_name));
     }
-    for (auto &reg_name : dests) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : dests) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0, reg_name));
     }
   }
 
   template <typename T>
-  void AppendImmediateOperand(Instruction *inst, T value) {
-    auto *src = new ImmediateOperand<T>(value);
+  void AppendImmediateOperand(Instruction* inst, T value) {
+    auto* src = new ImmediateOperand<T>(value);
     inst_->AppendSource(src);
   }
 
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
-    for (auto &value : values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
+    for (auto& value : values) {
       AppendImmediateOperand<T>(inst_, value);
     }
   }
@@ -173,8 +173,8 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       reg->set_address(value);
     }
   }
@@ -186,18 +186,18 @@
   }
 
   // Return true if the capability is null (except for address field).
-  bool IsNullCapability(CheriotRegister *cap) {
+  bool IsNullCapability(CheriotRegister* cap) {
     return cap->is_null() ||
            (cap->top() == 0 && cap->base() == 0 && cap->permissions() == 0 &&
             cap->tag() == 0 && cap->object_type() == 0 && cap->reserved() == 0);
   }
 
   void SetUpForLoadCapabilityTest(uint32_t address,
-                                  const CheriotRegister *cap) {
+                                  const CheriotRegister* cap) {
     ResetInstruction(kInstSizeNormal);
     inst()->set_semantic_function(&CheriotCLc);
     // Add the child instruction.
-    auto *child = new Instruction(kInstAddress, state());
+    auto* child = new Instruction(kInstAddress, state());
     child->set_semantic_function(&CheriotCLcChild);
     inst()->AppendChild(child);
     child->DecRef();
@@ -213,48 +213,48 @@
   }
 
   // Accessors.
-  Instruction *inst() { return inst_; }
-  TaggedFlatDemandMemory *memory() { return memory_; }
-  CheriotState *state() { return state_; }
+  Instruction* inst() { return inst_; }
+  TaggedFlatDemandMemory* memory() { return memory_; }
+  CheriotState* state() { return state_; }
   // Capability register pointers.
-  CheriotRegister *c1_reg() { return c1_reg_; }
-  CheriotRegister *c2_reg() { return c2_reg_; }
-  CheriotRegister *c3_reg() { return c3_reg_; }
-  CheriotRegister *c4_reg() { return c4_reg_; }
-  CheriotRegister *c5_reg() { return c5_reg_; }
-  CheriotRegister *cra_reg() { return cra_reg_; }
-  absl::BitGen &bitgen() { return bitgen_; }
+  CheriotRegister* c1_reg() { return c1_reg_; }
+  CheriotRegister* c2_reg() { return c2_reg_; }
+  CheriotRegister* c3_reg() { return c3_reg_; }
+  CheriotRegister* c4_reg() { return c4_reg_; }
+  CheriotRegister* c5_reg() { return c5_reg_; }
+  CheriotRegister* cra_reg() { return cra_reg_; }
+  absl::BitGen& bitgen() { return bitgen_; }
   bool trap_taken() { return trap_taken_; }
   bool trap_is_interrupt() { return trap_is_interrupt_; }
   uint64_t trap_value() { return trap_value_; }
   uint64_t trap_exception_code() { return trap_exception_code_; }
   uint64_t trap_epc() { return trap_epc_; }
-  const Instruction *trap_inst() { return trap_inst_; }
+  const Instruction* trap_inst() { return trap_inst_; }
 
  private:
-  Instruction *inst_ = nullptr;
-  TaggedFlatDemandMemory *memory_;
-  CheriotState *state_;
-  CheriotRegister *c1_reg_;
-  CheriotRegister *c2_reg_;
-  CheriotRegister *c3_reg_;
-  CheriotRegister *c4_reg_;
-  CheriotRegister *c5_reg_;
-  CheriotRegister *cra_reg_;
+  Instruction* inst_ = nullptr;
+  TaggedFlatDemandMemory* memory_;
+  CheriotState* state_;
+  CheriotRegister* c1_reg_;
+  CheriotRegister* c2_reg_;
+  CheriotRegister* c3_reg_;
+  CheriotRegister* c4_reg_;
+  CheriotRegister* c5_reg_;
+  CheriotRegister* cra_reg_;
   absl::BitGen bitgen_;
   bool trap_taken_ = false;
   bool trap_is_interrupt_ = false;
   uint64_t trap_value_ = 0;
   uint64_t trap_exception_code_ = 0;
   uint64_t trap_epc_ = 0;
-  const Instruction *trap_inst_ = nullptr;
+  const Instruction* trap_inst_ = nullptr;
 };
 
 bool RiscVCheriotInstructionsTest::TrapHandler(bool is_interrupt,
                                                uint64_t trap_value,
                                                uint64_t exception_code,
                                                uint64_t epc,
-                                               const Instruction *inst) {
+                                               const Instruction* inst) {
   trap_taken_ = true;
   trap_is_interrupt_ = is_interrupt;
   trap_value_ = trap_value;
@@ -1261,9 +1261,9 @@
   c3_reg()->set_address(kDataSeal10);
   inst()->Execute(nullptr);
   EXPECT_FALSE(trap_taken());
-  auto *db = state()->db_factory()->Allocate<uint32_t>(2);
+  auto* db = state()->db_factory()->Allocate<uint32_t>(2);
   db->set_latency(0);
-  auto *tag_db = state()->db_factory()->Allocate<uint8_t>(1);
+  auto* tag_db = state()->db_factory()->Allocate<uint8_t>(1);
   tag_db->set_latency(0);
   memory()->Load(kMemAddress + 0x200, db, tag_db, nullptr, nullptr);
   EXPECT_EQ(tag_db->Get<uint8_t>(0), 1);
@@ -1362,9 +1362,9 @@
   c3_reg()->ClearPermissions(PB::kPermitGlobal);
   inst()->Execute(nullptr);
   EXPECT_FALSE(trap_taken());
-  auto *db = state()->db_factory()->Allocate<uint32_t>(2);
+  auto* db = state()->db_factory()->Allocate<uint32_t>(2);
   db->set_latency(0);
-  auto *tag_db = state()->db_factory()->Allocate<uint8_t>(1);
+  auto* tag_db = state()->db_factory()->Allocate<uint8_t>(1);
   tag_db->set_latency(0);
   memory()->Load(kMemAddress + 0x200, db, tag_db, nullptr, nullptr);
   // Expect the tag to be cleared.
@@ -1389,9 +1389,9 @@
   EXPECT_TRUE(c3_reg()->IsBackwardSentry());
   inst()->Execute(nullptr);
   EXPECT_FALSE(trap_taken());
-  auto *db = state()->db_factory()->Allocate<uint32_t>(2);
+  auto* db = state()->db_factory()->Allocate<uint32_t>(2);
   db->set_latency(0);
-  auto *tag_db = state()->db_factory()->Allocate<uint8_t>(1);
+  auto* tag_db = state()->db_factory()->Allocate<uint8_t>(1);
   tag_db->set_latency(0);
   memory()->Load(kMemAddress + 0x200, db, tag_db, nullptr, nullptr);
   // Expect the tag to be cleared.

diff --git a/cheriot/test/riscv_cheriot_m_instructions_test.cc b/cheriot/test/riscv_cheriot_m_instructions_test.cc
index ec23951..35cdcb9 100644
--- a/cheriot/test/riscv_cheriot_m_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_m_instructions_test.cc

@@ -83,29 +83,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -114,8 +114,8 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       reg->set_address(value);
     }
   }
@@ -128,16 +128,16 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(std::string_view reg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
     return reg->address();
   }
 
-  TaggedFlatDemandMemory *mem_;
-  CheriotState *state_;
-  Instruction *instruction_;
-  CheriotRegister *creg_1_;
-  CheriotRegister *creg_2_;
-  CheriotRegister *creg_3_;
+  TaggedFlatDemandMemory* mem_;
+  CheriotState* state_;
+  Instruction* instruction_;
+  CheriotRegister* creg_1_;
+  CheriotRegister* creg_2_;
+  CheriotRegister* creg_3_;
   absl::BitGen bitgen_;
 };
 

diff --git a/cheriot/test/riscv_cheriot_rvv_encoding_test.cc b/cheriot/test/riscv_cheriot_rvv_encoding_test.cc
index 4f38e72..71475bd 100644
--- a/cheriot/test/riscv_cheriot_rvv_encoding_test.cc
+++ b/cheriot/test/riscv_cheriot_rvv_encoding_test.cc

@@ -46,13 +46,13 @@
     delete state_;
   }
 
-  TaggedFlatDemandMemory *mem_;
-  CheriotState *state_;
-  RiscVCheriotRVVEncoding *enc_;
+  TaggedFlatDemandMemory* mem_;
+  CheriotState* state_;
+  RiscVCheriotRVVEncoding* enc_;
 };
 
 TEST_F(RiscVCheriotRVVEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -60,7 +60,7 @@
 }
 
 TEST_F(RiscVCheriotRVVEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";

diff --git a/cheriot/test/riscv_cheriot_vector_fp_compare_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_fp_compare_instructions_test.cc
index f872142..53771b2 100644
--- a/cheriot/test/riscv_cheriot_vector_fp_compare_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_fp_compare_instructions_test.cc

@@ -56,7 +56,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskFPOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Vs1)) {
@@ -80,14 +80,14 @@
     // Overwrite the first few values of the input data with infinities,
     // zeros, denormals and NaNs.
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
     // Make every third value the same (at least if the types are same sized).
     for (int i = 0; i < std::min(vs1_size, vs2_size); i += 3) {
       vs1_span[i] = static_cast<Vs1>(vs2_span[i]);
@@ -157,10 +157,10 @@
               uint8_t expected_value =
                   operation(vs2_value[i], vs1_value[i], mask_value);
               auto int_vs2_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                       &vs2_value[i]);
               auto int_vs1_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                       &vs1_value[i]);
               EXPECT_EQ(expected_value, inst_value)
                   << absl::StrCat(name, "[", i, "] op(", vs2_value[i], "[0x",
@@ -182,7 +182,7 @@
   // not use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskFPOpTestHelperVV(absl::string_view name, int sew,
-                                  Instruction *inst,
+                                  Instruction* inst,
                                   std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskFPOpWithMaskTestHelperVV<Vs2, Vs1>(
         name, sew, inst,
@@ -198,7 +198,7 @@
   // use the mask bit.
   template <typename Vs2, typename Fs1, typename ScalarReg = CheriotRegister>
   void BinaryMaskFPOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Fs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Fs1)) {
@@ -282,10 +282,10 @@
               uint8_t expected_value =
                   operation(vs2_value[i], fs1_value, mask_value);
               auto int_vs2_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                       &vs2_value[i]);
               auto int_fs1_val =
-                  *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType*>(
                       &fs1_value);
               EXPECT_EQ(expected_value, inst_value)
                   << absl::StrCat(name, "[", i, "] op(", vs2_value[i], "[0x",
@@ -306,7 +306,7 @@
   // use the mask bit.
   template <typename Vs2, typename Fs1>
   void BinaryMaskFPOpTestHelperVX(absl::string_view name, int sew,
-                                  Instruction *inst,
+                                  Instruction* inst,
                                   std::function<uint8_t(Vs2, Fs1)> operation) {
     BinaryMaskFPOpWithMaskTestHelperVX<Vs2, Fs1, RVFpRegister>(
         name, sew, inst,

diff --git a/cheriot/test/riscv_cheriot_vector_fp_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_fp_instructions_test.cc
index c9f4d15..9e0f84f 100644
--- a/cheriot/test/riscv_cheriot_vector_fp_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_fp_instructions_test.cc

@@ -85,7 +85,7 @@
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void TernaryOpFPTestHelperVV(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs2, Vs1, Vd)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -120,49 +120,49 @@
       using VdInt = typename FPTypeInfo<Vd>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
-      *reinterpret_cast<VdInt *>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
-      *reinterpret_cast<VdInt *>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
-      *reinterpret_cast<VdInt *>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
-      *reinterpret_cast<VdInt *>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
+      *reinterpret_cast<VdInt*>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
+      *reinterpret_cast<VdInt*>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
+      *reinterpret_cast<VdInt*>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
+      *reinterpret_cast<VdInt*>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
       if (lmul_index == 4) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
       } else if (lmul_index == 5) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
       } else if (lmul_index == 6) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
       }
       // Modify the first mask bits to use each of the special floating point
       // values.
@@ -243,23 +243,23 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 auto int_vd_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &vd_value[count]);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val = operation(vs2_value[count], vs1_value[count],
                                           vd_value[count]);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                           &vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -296,7 +296,7 @@
   template <typename Vd, typename Vs2, typename Fs1,
             typename ScalarReg = CheriotRegister>
   void TernaryOpFPTestHelperVX(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs2, Fs1, Vd)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -322,29 +322,29 @@
     // Iterate across different lmul values.
     for (int lmul_index = 0; lmul_index < 7; lmul_index++) {
       // Clear vd_span.
-      for (auto &vd_val : vd_span) vd_val = 0;
+      for (auto& vd_val : vd_span) vd_val = 0;
       // Initialize input values.
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
       using VdInt = typename FPTypeInfo<Vd>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
-      *reinterpret_cast<VdInt *>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
-      *reinterpret_cast<VdInt *>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
-      *reinterpret_cast<VdInt *>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
-      *reinterpret_cast<VdInt *>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
+      *reinterpret_cast<VdInt*>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
+      *reinterpret_cast<VdInt*>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
+      *reinterpret_cast<VdInt*>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
+      *reinterpret_cast<VdInt*>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -432,10 +432,10 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 auto int_vd_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &vd_value[count]);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   // Set rounding mode and perform the computation.
@@ -445,13 +445,13 @@
                       operation(vs2_value[count], fs1_value, vd_value[count]);
                   // Extract the integer view of the fp values.
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_fs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType*>(
                           &fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -1100,10 +1100,10 @@
         sign_op) {
   using Int = typename FPTypeInfo<T>::IntType;
   Int sign_mask = 1ULL << (FPTypeInfo<T>::kBitSize - 1);
-  Int vs2i = *reinterpret_cast<Int *>(&vs2);
-  Int vs1i = *reinterpret_cast<Int *>(&vs1);
+  Int vs2i = *reinterpret_cast<Int*>(&vs2);
+  Int vs1i = *reinterpret_cast<Int*>(&vs1);
   Int resi = sign_op(vs2i, vs1i, sign_mask);
-  return *reinterpret_cast<T *>(&resi);
+  return *reinterpret_cast<T*>(&resi);
 }
 
 // The sign is that of vs1.
@@ -1244,7 +1244,7 @@
 template <typename T>
 bool is_snan(T value) {
   using IntType = typename FPTypeInfo<T>::IntType;
-  IntType int_value = *reinterpret_cast<IntType *>(&value);
+  IntType int_value = *reinterpret_cast<IntType*>(&value);
   bool signal = (int_value & (1ULL << (FPTypeInfo<T>::kSigSize - 1))) == 0;
   return std::isnan(value) && signal;
 }
@@ -1259,7 +1259,7 @@
   if (std::isnan(vs2) && std::isnan(vs1)) {
     // Canonical NaN.
     auto canonical = FPTypeInfo<T>::kCanonicalNaN;
-    T canonical_fp = *reinterpret_cast<T *>(&canonical);
+    T canonical_fp = *reinterpret_cast<T*>(&canonical);
     return std::tie(canonical_fp, flag);
   }
   if (std::isnan(vs2)) return std::tie(vs1, flag);

diff --git a/cheriot/test/riscv_cheriot_vector_fp_reduction_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_fp_reduction_instructions_test.cc
index ba3ad17..3ad2121 100644
--- a/cheriot/test/riscv_cheriot_vector_fp_reduction_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_fp_reduction_instructions_test.cc

@@ -55,7 +55,7 @@
   // Helper function for floating point reduction operations.
   template <typename Vd, typename Vs2, typename Vs1>
   void ReductionOpFPTestHelper(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs1, Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -181,8 +181,8 @@
 template <typename T>
 T MaxMinHelper(T vs2, T vs1, std::function<T(T, T)> operation) {
   using UInt = typename FPTypeInfo<T>::IntType;
-  UInt vs2_uint = *reinterpret_cast<UInt *>(&vs2);
-  UInt vs1_uint = *reinterpret_cast<UInt *>(&vs1);
+  UInt vs2_uint = *reinterpret_cast<UInt*>(&vs2);
+  UInt vs1_uint = *reinterpret_cast<UInt*>(&vs1);
   UInt mask = 1ULL << (FPTypeInfo<T>::kSigSize - 1);
   bool nan_vs2 = std::isnan(vs2);
   bool nan_vs1 = std::isnan(vs1);
@@ -191,7 +191,7 @@
     // Canonical NaN.
     UInt canonical = ((1ULL << (FPTypeInfo<T>::kExpSize + 1)) - 1)
                      << (FPTypeInfo<T>::kSigSize - 1);
-    T canonical_fp = *reinterpret_cast<T *>(&canonical);
+    T canonical_fp = *reinterpret_cast<T*>(&canonical);
     return canonical_fp;
   }
   if (nan_vs2) return vs1;

diff --git a/cheriot/test/riscv_cheriot_vector_fp_test_utilities.h b/cheriot/test/riscv_cheriot_vector_fp_test_utilities.h
index 90f59b5..d00463e 100644
--- a/cheriot/test/riscv_cheriot_vector_fp_test_utilities.h
+++ b/cheriot/test/riscv_cheriot_vector_fp_test_utilities.h

@@ -117,12 +117,12 @@
     if (exp > delta_position) {
       exp -= delta_position;
       UInt udelta = exp << FPTypeInfo<T>::kSigSize;
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     } else {
       // Becomes a denormal
       int diff = delta_position - exp;
       UInt udelta = 1ULL << (FPTypeInfo<T>::kSigSize - 1 - diff);
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     }
     EXPECT_THAT(reg, testing::NanSensitiveFloatNear(op, delta)) << str;
   } else {
@@ -142,12 +142,12 @@
     if (exp > delta_position) {
       exp -= delta_position;
       UInt udelta = exp << FPTypeInfo<T>::kSigSize;
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     } else {
       // Becomes a denormal
       int diff = delta_position - exp;
       UInt udelta = 1ULL << (FPTypeInfo<T>::kSigSize - 1 - diff);
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     }
     EXPECT_THAT(reg, testing::NanSensitiveDoubleNear(op, delta)) << str;
   } else {
@@ -176,7 +176,7 @@
 struct GreaterSize {
   static const bool value =
       sizeof(S) > sizeof(D) &&
-      std::is_floating_point<S>::value &&std::is_integral<D>::value;
+      std::is_floating_point<S>::value&& std::is_integral<D>::value;
 };
 
 template <typename S, typename D>
@@ -201,16 +201,16 @@
 inline typename std::enable_if<internal::LessSize<S, D>::value, D>::type NaNBox(
     S value) {
   using SInt = typename FPTypeInfo<S>::IntType;
-  SInt sval = *reinterpret_cast<SInt *>(&value);
+  SInt sval = *reinterpret_cast<SInt*>(&value);
   D dval = (~static_cast<D>(0) << (sizeof(S) * 8)) | sval;
-  return *reinterpret_cast<D *>(&dval);
+  return *reinterpret_cast<D*>(&dval);
 }
 
 // This version does a straight copy - as the data types are the same size.
 template <typename S, typename D>
 inline typename std::enable_if<internal::EqualSize<S, D>::value, D>::type
 NaNBox(S value) {
-  return *reinterpret_cast<D *>(&value);
+  return *reinterpret_cast<D*>(&value);
 }
 
 // Signal error if the register is smaller than the floating point value.
@@ -245,14 +245,14 @@
                              1ULL << FPTypeInfo<T>::kSigSize);
     UInt value = (sign & 1) << (FPTypeInfo<T>::kBitSize - 1) |
                  (exp << FPTypeInfo<T>::kSigSize) | sig;
-    T val = *reinterpret_cast<T *>(&value);
+    T val = *reinterpret_cast<T*>(&value);
     return val;
   }
 
   // This method uses random values for each field in the fp number.
   template <typename T>
   void FillArrayWithRandomFPValues(absl::Span<T> span) {
-    for (auto &val : span) {
+    for (auto& val : span) {
       val = RandomFPValue<T>();
     }
   }
@@ -267,41 +267,41 @@
     using Vs1Int = typename FPTypeInfo<Vs1>::IntType;
     // Overwrite the first few values of the input data with infinities,
     // zeros, denormals and NaNs.
-    *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
     if (count == 4) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
     } else if (count == 5) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
     } else if (count == 6) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
     }
     // Modify the first mask bits to use each of the special floating
     // point values.
@@ -312,7 +312,7 @@
   // NaN etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpFPTestHelperVV(absl::string_view name, int sew,
-                              Instruction *inst, int delta_position,
+                              Instruction* inst, int delta_position,
                               std::function<Vd(Vs2, Vs1)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -407,19 +407,19 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val = operation(vs2_value[count], vs1_value[count]);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                           &vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -453,7 +453,7 @@
   // NaN etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpWithFflagsFPTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2, Vs1)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -475,7 +475,7 @@
     auto vs2_span = Span<Vs2>(vs2_value);
     auto vs1_span = Span<Vs1>(vs1_value);
     AppendVectorRegisterOperands({kVs2, kVs1, kVmask}, {kVd});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});
@@ -555,7 +555,7 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   Vd op_val;
                   uint32_t flag;
@@ -566,11 +566,11 @@
                     op_val = op_val_tmp;
                     flag = flag_tmp;
                   }
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<Vs1Int *>(&vs1_value[count]);
+                      *reinterpret_cast<Vs1Int*>(&vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -607,7 +607,7 @@
   template <typename Vd, typename Vs2, typename Fs1,
             typename ScalarReg = CheriotRegister>
   void BinaryOpWithFflagsFPTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2, Fs1)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -627,7 +627,7 @@
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {kVd});
     AppendRegisterOperands<ScalarReg>({kFs1Name}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     AppendVectorRegisterOperands({kVmask}, {});
     SetVectorRegisterValues<uint8_t>(
@@ -638,14 +638,14 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating
       // point values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -726,7 +726,7 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   Vd op_val;
                   uint32_t flag;
@@ -737,10 +737,10 @@
                     op_val = op_val_tmp;
                     flag = flag_tmp;
                   }
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
-                  auto int_fs1_val = *reinterpret_cast<Fs1Int *>(&fs1_value);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
+                  auto int_fs1_val = *reinterpret_cast<Fs1Int*>(&fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -777,7 +777,7 @@
   template <typename Vd, typename Vs2, typename Fs1,
             typename ScalarReg = CheriotRegister>
   void BinaryOpFPWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<Vd(Vs2, Fs1, bool)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -806,14 +806,14 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating
       // point values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -891,15 +891,15 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val =
                       operation(vs2_value[count], fs1_value, mask_value);
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
-                  auto int_fs1_val = *reinterpret_cast<Fs1Int *>(&fs1_value);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
+                  auto int_fs1_val = *reinterpret_cast<Fs1Int*>(&fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -932,7 +932,7 @@
   template <typename Vd, typename Vs2, typename Vs1,
             typename ScalarReg = CheriotRegister>
   void BinaryOpFPTestHelperVX(absl::string_view name, int sew,
-                              Instruction *inst, int delta_position,
+                              Instruction* inst, int delta_position,
                               std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpFPWithMaskTestHelperVX<Vd, Vs2, Vs1, ScalarReg>(
         name, sew, inst, delta_position,
@@ -945,7 +945,7 @@
   }
 
  protected:
-  mpact::sim::riscv::RiscVFPState *rv_fp_;
+  mpact::sim::riscv::RiscVFPState* rv_fp_;
 };
 
 #endif  // MPACT_CHERIOT_TEST_RISCV_CHERIOT_VECTOR_FP_TEST_UTILITIES_H_

diff --git a/cheriot/test/riscv_cheriot_vector_fp_unary_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_fp_unary_instructions_test.cc
index 6d525a5..9e36ced 100644
--- a/cheriot/test/riscv_cheriot_vector_fp_unary_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_fp_unary_instructions_test.cc

@@ -102,7 +102,7 @@
   template <typename T>
   void FillArrayWithRandomFPValues(absl::Span<T> span) {
     using UInt = typename FPTypeInfo<T>::IntType;
-    for (auto &val : span) {
+    for (auto& val : span) {
       UInt sign = absl::Uniform(absl::IntervalClosed, bitgen_, 0ULL, 1ULL);
       UInt exp = absl::Uniform(absl::IntervalClosedOpen, bitgen_, 0ULL,
                                1ULL << FPTypeInfo<T>::kExpSize);
@@ -110,14 +110,14 @@
                                1ULL << FPTypeInfo<T>::kSigSize);
       UInt value = (sign & 1) << (FPTypeInfo<T>::kBitSize - 1) |
                    (exp << FPTypeInfo<T>::kSigSize) | sig;
-      val = *reinterpret_cast<T *>(&value);
+      val = *reinterpret_cast<T*>(&value);
     }
   }
 
   // Floating point test needs to ensure to use the fp special values (inf, NaN
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2>
-  void UnaryOpFPTestHelperV(absl::string_view name, int sew, Instruction *inst,
+  void UnaryOpFPTestHelperV(absl::string_view name, int sew, Instruction* inst,
                             int delta_position,
                             std::function<Vd(Vs2)> operation) {
     int byte_sew = sew / 8;
@@ -142,17 +142,17 @@
       using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[8]) = 0x0119515e;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[9]) = 0x0007fea3;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[10]) = 0x800bc58f;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[8]) = 0x0119515e;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[9]) = 0x0007fea3;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[10]) = 0x800bc58f;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -219,13 +219,13 @@
                   auto op_val = operation(vs2_value[count]);
                   // Do separate comparison if the result is a NaN.
                   auto int_reg_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &reg_val);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -259,7 +259,7 @@
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2>
   void UnaryOpWithFflagsFPTestHelperV(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -276,7 +276,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2, kVmask}, {kVd});
-    auto *op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(op);
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});
@@ -286,17 +286,17 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[8]) = 0x0119515e;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[9]) = 0x0007fea3;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[10]) = 0x800bc58f;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[8]) = 0x0119515e;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[9]) = 0x0007fea3;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[10]) = 0x800bc58f;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -379,10 +379,10 @@
                   }
                   fflags_test |= (rv_fp_->fflags()->AsUint32() | flag);
                   // Do separate comparison if the result is a NaN.
-                  auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -413,8 +413,8 @@
   }
 
  protected:
-  mpact::sim::riscv::RiscVFPState *rv_fp_ = nullptr;
-  RiscVCsrInterface *fflags_ = nullptr;
+  mpact::sim::riscv::RiscVFPState* rv_fp_ = nullptr;
+  RiscVCsrInterface* fflags_ = nullptr;
 };
 
 // Templated helper function for classifying fp numbers.
@@ -425,8 +425,7 @@
     case FP_INFINITE:
       return std::signbit(val) ? 1 : 1 << 7;
     case FP_NAN: {
-      auto uint_val =
-          *reinterpret_cast<typename FPTypeInfo<T>::IntType *>(&val);
+      auto uint_val = *reinterpret_cast<typename FPTypeInfo<T>::IntType*>(&val);
       bool quiet_nan = (uint_val >> (FPTypeInfo<T>::kSigSize - 1)) & 1;
       return quiet_nan ? 1 << 9 : 1 << 8;
     }
@@ -481,7 +480,7 @@
 
 // Helper function for fp to integer conversions.
 template <typename F, typename I>
-std::tuple<I, uint32_t> ConvertHelper(F value, RiscVFPState *fp_state) {
+std::tuple<I, uint32_t> ConvertHelper(F value, RiscVFPState* fp_state) {
   constexpr F kMin = static_cast<F>(std::numeric_limits<I>::min());
   constexpr F kMax = static_cast<F>(std::numeric_limits<I>::max());
   ScopedFPStatus status(fp_state->host_fp_interface());
@@ -701,15 +700,15 @@
         }
         using UIntD = typename FPTypeInfo<double>::IntType;
         using UIntF = typename FPTypeInfo<float>::IntType;
-        UIntD uval = *reinterpret_cast<UIntD *>(&vs2);
+        UIntD uval = *reinterpret_cast<UIntD*>(&vs2);
         int diff = FPTypeInfo<double>::kSigSize - FPTypeInfo<float>::kSigSize;
         UIntF bit = (uval & (FPTypeInfo<double>::kSigMask >> diff)) != 0;
         float res = static_cast<float>(vs2);
         // The narrowing conversion may have generated an infinity, so check
         // for infinity before doing rounding.
         if (std::isinf(res)) return res;
-        UIntF ures = *reinterpret_cast<UIntF *>(&res) | bit;
-        return *reinterpret_cast<float *>(&ures);
+        UIntF ures = *reinterpret_cast<UIntF*>(&res) | bit;
+        return *reinterpret_cast<float*>(&ures);
       });
 }
 
@@ -787,11 +786,11 @@
 
 // Helper function for testing approximate reciprocal instruction.
 template <typename T>
-inline T Vrecip7vTestHelper(T vs2, RiscVFPState *rv_fp) {
+inline T Vrecip7vTestHelper(T vs2, RiscVFPState* rv_fp) {
   using UInt = typename FPTypeInfo<T>::IntType;
   if (FPTypeInfo<T>::IsNaN(vs2)) {
     auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-    return *reinterpret_cast<T *>(&nan_value);
+    return *reinterpret_cast<T*>(&nan_value);
   }
   if (std::isinf(vs2)) {
     return std::signbit(vs2) ? -0.0 : 0.0;
@@ -799,9 +798,9 @@
   if (vs2 == 0.0) {
     UInt value =
         std::signbit(vs2) ? FPTypeInfo<T>::kNegInf : FPTypeInfo<T>::kPosInf;
-    return *reinterpret_cast<T *>(&value);
+    return *reinterpret_cast<T*>(&value);
   }
-  UInt uint_vs2 = *reinterpret_cast<UInt *>(&vs2);
+  UInt uint_vs2 = *reinterpret_cast<UInt*>(&vs2);
   auto exp = (uint_vs2 & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
   auto sig2 =
       (uint_vs2 & FPTypeInfo<T>::kSigMask) >> (FPTypeInfo<T>::kSigSize - 2);
@@ -813,7 +812,7 @@
         return std::numeric_limits<T>::lowest();
       } else {
         UInt value = FPTypeInfo<T>::kNegInf;
-        return *reinterpret_cast<T *>(&value);
+        return *reinterpret_cast<T*>(&value);
       }
     } else {
       if ((rm == FPRoundingMode::kRoundTowardsZero) ||
@@ -821,17 +820,17 @@
         return std::numeric_limits<T>::max();
       } else {
         UInt value = FPTypeInfo<T>::kPosInf;
-        return *reinterpret_cast<T *>(&value);
+        return *reinterpret_cast<T*>(&value);
       }
     }
   }
   ScopedFPStatus status(rv_fp->host_fp_interface(),
                         FPRoundingMode::kRoundTowardsZero);
   T value = 1.0 / vs2;
-  UInt uint_val = *reinterpret_cast<UInt *>(&value);
+  UInt uint_val = *reinterpret_cast<UInt*>(&value);
   UInt mask = FPTypeInfo<T>::kSigMask >> 7;
   uint_val = uint_val & ~mask;
-  return *reinterpret_cast<T *>(&uint_val);
+  return *reinterpret_cast<T*>(&uint_val);
 }
 
 // Test approximate reciprocal instruction.
@@ -846,18 +845,18 @@
 
 // Helper function for testing approximate reciprocal square root instruction.
 template <typename T>
-inline std::tuple<T, uint32_t> Vfrsqrt7vTestHelper(T vs2, RiscVFPState *rv_fp) {
+inline std::tuple<T, uint32_t> Vfrsqrt7vTestHelper(T vs2, RiscVFPState* rv_fp) {
   using UInt = typename FPTypeInfo<T>::IntType;
   T return_value;
   uint32_t fflags = 0;
   if (FPTypeInfo<T>::IsNaN(vs2) || (vs2 < 0.0)) {
     auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-    return_value = *reinterpret_cast<T *>(&nan_value);
+    return_value = *reinterpret_cast<T*>(&nan_value);
     fflags = static_cast<uint32_t>(FPExceptions::kInvalidOp);
   } else if (vs2 == 0.0) {
     UInt value =
         std::signbit(vs2) ? FPTypeInfo<T>::kNegInf : FPTypeInfo<T>::kPosInf;
-    return_value = *reinterpret_cast<T *>(&value);
+    return_value = *reinterpret_cast<T*>(&value);
     fflags = static_cast<uint32_t>(FPExceptions::kDivByZero);
   } else if (std::isinf(vs2)) {
     return_value = 0.0;
@@ -866,10 +865,10 @@
     ScopedFPStatus status(rv_fp->host_fp_interface(),
                           FPRoundingMode::kRoundTowardsZero);
     T value = 1.0 / sqrt(vs2);
-    UInt uint_val = *reinterpret_cast<UInt *>(&value);
+    UInt uint_val = *reinterpret_cast<UInt*>(&value);
     UInt mask = FPTypeInfo<T>::kSigMask >> 7;
     uint_val = uint_val & ~mask;
-    return_value = *reinterpret_cast<T *>(&uint_val);
+    return_value = *reinterpret_cast<T*>(&uint_val);
   }
   return std::make_tuple(return_value, fflags);
 }
@@ -901,7 +900,7 @@
     if (!mpact::sim::generic::FPTypeInfo<T>::IsQNaN(vs2)) {
       flags = (uint32_t)FPExceptions::kInvalidOp;
     }
-    return std::make_tuple(*reinterpret_cast<const T *>(&val),
+    return std::make_tuple(*reinterpret_cast<const T*>(&val),
                            (uint32_t)FPExceptions::kInvalidOp);
   }
   T res = sqrt(vs2);

diff --git a/cheriot/test/riscv_cheriot_vector_instructions_test_base.h b/cheriot/test/riscv_cheriot_vector_instructions_test_base.h
index 4239658..df66768 100644
--- a/cheriot/test/riscv_cheriot_vector_instructions_test_base.h
+++ b/cheriot/test/riscv_cheriot_vector_instructions_test_base.h

@@ -124,7 +124,7 @@
     child_instruction_ = new Instruction(kInstAddress, state_);
     child_instruction_->set_size(4);
     // Initialize a portion of memory with a known pattern.
-    auto *db = state_->db_factory()->Allocate(8192);
+    auto* db = state_->db_factory()->Allocate(8192);
     auto span = db->Get<uint8_t>();
     for (int i = 0; i < 8192; i++) {
       span[i] = i & 0xff;
@@ -162,10 +162,10 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the given instruction.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -173,22 +173,22 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the default instruction.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     AppendImmediateOperands<T>(instruction_, values);
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
   template <typename T = CheriotRegister>
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
@@ -196,25 +196,25 @@
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
   template <typename T = CheriotRegister>
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands<T>(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T, typename RegisterType = CheriotRegister>
   T GetRegisterValue(absl::string_view vreg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(vreg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(vreg_name).first;
     return reg->data_buffer()->Get<T>();
   }
 
   // named register and sets it to the corresponding value.
   template <typename T, typename RegisterType = CheriotRegister>
   void SetRegisterValues(
-      const std::vector<tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RegisterType>(reg_name).first;
-      auto *db =
+      const std::vector<tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RegisterType>(reg_name).first;
+      auto* db =
           state_->db_factory()->Allocate<typename RegisterType::ValueType>(1);
       db->template Set<T>(0, value);
       reg->SetDataBuffer(db);
@@ -224,43 +224,43 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendVectorRegisterOperands(Instruction *inst,
-                                    const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
-    for (auto &reg_no : sources) {
-      std::vector<RegisterBase *> reg_vec;
+  void AppendVectorRegisterOperands(Instruction* inst,
+                                    const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
+    for (auto& reg_no : sources) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorSourceOperand(
-          absl::Span<RegisterBase *>(reg_vec), absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorSourceOperand(absl::Span<RegisterBase*>(reg_vec),
+                                             absl::StrCat("v", reg_no));
       inst->AppendSource(op);
     }
-    for (auto &reg_no : destinations) {
-      std::vector<RegisterBase *> reg_vec;
+    for (auto& reg_no : destinations) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorDestinationOperand(
-          absl::Span<RegisterBase *>(reg_vec), 0, absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorDestinationOperand(
+          absl::Span<RegisterBase*>(reg_vec), 0, absl::StrCat("v", reg_no));
       inst->AppendDestination(op);
     }
   }
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendVectorRegisterOperands(const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
+  void AppendVectorRegisterOperands(const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
     AppendVectorRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetVectorRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -269,10 +269,10 @@
   // value.
   template <typename T>
   void SetVectorRegisterValues(
-      const std::vector<tuple<std::string, Span<const T>>> &values) {
-    for (auto &[vreg_name, span] : values) {
-      auto *vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
-      auto *db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
+      const std::vector<tuple<std::string, Span<const T>>>& values) {
+    for (auto& [vreg_name, span] : values) {
+      auto* vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
+      auto* db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
       db->template Set<T>(span);
       vreg->SetDataBuffer(db);
       db->DecRef();
@@ -280,7 +280,7 @@
   }
 
   // Initializes the semantic function of the instruction object.
-  void SetSemanticFunction(Instruction *inst,
+  void SetSemanticFunction(Instruction* inst,
                            Instruction::SemanticFunction fcn) {
     inst->set_semantic_function(fcn);
   }
@@ -300,7 +300,7 @@
 
   // Configure the vector unit according to the vtype and vlen values.
   void ConfigureVectorUnit(uint32_t vtype, uint32_t vlen) {
-    Instruction *inst = new Instruction(state_);
+    Instruction* inst = new Instruction(state_);
     AppendImmediateOperands<uint32_t>(inst, {vlen, vtype});
     SetSemanticFunction(inst, absl::bind_front(&Vsetvl, true, false));
     inst->Execute(nullptr);
@@ -325,14 +325,14 @@
   // Fill the span with random values.
   template <typename T>
   void FillArrayWithRandomValues(absl::Span<T> span) {
-    for (auto &val : span) {
+    for (auto& val : span) {
       val = RandomValue<T>();
     }
   }
 
   // Helper function for testing unary vector-vector instructions.
   template <typename Vd, typename Vs2>
-  void UnaryOpTestHelperV(absl::string_view name, int sew, Instruction *inst,
+  void UnaryOpTestHelperV(absl::string_view name, int sew, Instruction* inst,
                           std::function<Vd(Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2)) {
@@ -427,7 +427,7 @@
   // of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -534,7 +534,7 @@
   // Helper function for testing vector-vector instructions that do not
   // use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
-  void BinaryOpTestHelperVV(absl::string_view name, int sew, Instruction *inst,
+  void BinaryOpTestHelperVV(absl::string_view name, int sew, Instruction* inst,
                             std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpWithMaskTestHelperVV<Vd, Vs2, Vs1>(
         name, sew, inst, [operation](Vs2 vs2, Vs1 vs1, bool mask_value) -> Vd {
@@ -550,7 +550,7 @@
   template <typename Vd, typename Vs2, typename Rs1,
             typename ScalarReg = CheriotRegister>
   void BinaryOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Rs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -664,7 +664,7 @@
   // not use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1,
             typename ScalarReg = CheriotRegister>
-  void BinaryOpTestHelperVX(absl::string_view name, int sew, Instruction *inst,
+  void BinaryOpTestHelperVX(absl::string_view name, int sew, Instruction* inst,
                             std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpWithMaskTestHelperVX<Vd, Vs2, Vs1, ScalarReg>(
         name, sew, inst, [operation](Vs2 vs2, Vs1 vs1, bool mask_value) -> Vd {
@@ -679,7 +679,7 @@
   // of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
   void TernaryOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Vs1, Vd, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -800,7 +800,7 @@
   // Helper function for testing vector-vector instructions that do not
   // use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
-  void TernaryOpTestHelperVV(absl::string_view name, int sew, Instruction *inst,
+  void TernaryOpTestHelperVV(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vs2, Vs1, Vd)> operation) {
     TernaryOpWithMaskTestHelperVV<Vd, Vs2, Vs1>(
         name, sew, inst,
@@ -817,7 +817,7 @@
   template <typename Vd, typename Vs2, typename Rs1,
             typename ScalarReg = CheriotRegister>
   void TernaryOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Rs1, Vd, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -947,7 +947,7 @@
   // not use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Rs1,
             typename ScalarReg = CheriotRegister>
-  void TernaryOpTestHelperVX(absl::string_view name, int sew, Instruction *inst,
+  void TernaryOpTestHelperVX(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vs2, Rs1, Vd)> operation) {
     TernaryOpWithMaskTestHelperVX<Vd, Vs2, Rs1, ScalarReg>(
         name, sew, inst,
@@ -963,7 +963,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Vs1)) {
@@ -1062,7 +1062,7 @@
   // not use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskOpTestHelperVV(absl::string_view name, int sew,
-                                Instruction *inst,
+                                Instruction* inst,
                                 std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskOpWithMaskTestHelperVV<Vs2, Vs1>(
         name, sew, inst,
@@ -1078,7 +1078,7 @@
   // use the mask bit.
   template <typename Vs2, typename Rs1, typename ScalarReg = CheriotRegister>
   void BinaryMaskOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Rs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Rs1)) {
@@ -1174,7 +1174,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskOpTestHelperVX(absl::string_view name, int sew,
-                                Instruction *inst,
+                                Instruction* inst,
                                 std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskOpWithMaskTestHelperVX<Vs2, Vs1>(
         name, sew, inst,
@@ -1215,25 +1215,25 @@
     }
   }
 
-  CheriotVectorState *rv_vector() const { return rv_vector_; }
-  absl::Span<RVVectorRegister *> vreg() {
-    return absl::Span<RVVectorRegister *>(vreg_);
+  CheriotVectorState* rv_vector() const { return rv_vector_; }
+  absl::Span<RVVectorRegister*> vreg() {
+    return absl::Span<RVVectorRegister*>(vreg_);
   }
-  absl::Span<CheriotRegister *> creg() {
-    return absl::Span<CheriotRegister *>(creg_);
+  absl::Span<CheriotRegister*> creg() {
+    return absl::Span<CheriotRegister*>(creg_);
   }
-  absl::BitGen &bitgen() { return bitgen_; }
-  Instruction *instruction() { return instruction_; }
+  absl::BitGen& bitgen() { return bitgen_; }
+  Instruction* instruction() { return instruction_; }
 
  protected:
-  CheriotRegister *creg_[32];
-  RVVectorRegister *vreg_[32];
-  RVFpRegister *freg_[32];
-  CheriotState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
-  TaggedFlatDemandMemory *memory_;
-  CheriotVectorState *rv_vector_;
+  CheriotRegister* creg_[32];
+  RVVectorRegister* vreg_[32];
+  RVFpRegister* freg_[32];
+  CheriotState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
+  TaggedFlatDemandMemory* memory_;
+  CheriotVectorState* rv_vector_;
   absl::BitGen bitgen_;
 };
 

diff --git a/cheriot/test/riscv_cheriot_vector_memory_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_memory_instructions_test.cc
index 78b7f03..6ca5334 100644
--- a/cheriot/test/riscv_cheriot_vector_memory_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_memory_instructions_test.cc

@@ -129,7 +129,7 @@
     child_instruction_ = new Instruction(kInstAddress, state_);
     child_instruction_->set_size(4);
     // Initialize a portion of memory with a known pattern.
-    auto *db = state_->db_factory()->Allocate(8192);
+    auto* db = state_->db_factory()->Allocate(8192);
     auto span = db->Get<uint8_t>();
     for (int i = 0; i < 8192; i++) {
       span[i] = i & 0xff;
@@ -158,10 +158,10 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the given instruction.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -169,46 +169,46 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the default instruction.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     AppendImmediateOperands<T>(instruction_, values);
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetRegisterValue(absl::string_view vreg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(vreg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(vreg_name).first;
     return reg->data_buffer()->Get<T>();
   }
 
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(
-      const std::vector<tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
+      const std::vector<tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -217,43 +217,43 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendVectorRegisterOperands(Instruction *inst,
-                                    const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
-    for (auto &reg_no : sources) {
-      std::vector<RegisterBase *> reg_vec;
+  void AppendVectorRegisterOperands(Instruction* inst,
+                                    const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
+    for (auto& reg_no : sources) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorSourceOperand(
-          absl::Span<RegisterBase *>(reg_vec), absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorSourceOperand(absl::Span<RegisterBase*>(reg_vec),
+                                             absl::StrCat("v", reg_no));
       inst->AppendSource(op);
     }
-    for (auto &reg_no : destinations) {
-      std::vector<RegisterBase *> reg_vec;
+    for (auto& reg_no : destinations) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorDestinationOperand(
-          absl::Span<RegisterBase *>(reg_vec), 0, absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorDestinationOperand(
+          absl::Span<RegisterBase*>(reg_vec), 0, absl::StrCat("v", reg_no));
       inst->AppendDestination(op);
     }
   }
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendVectorRegisterOperands(const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
+  void AppendVectorRegisterOperands(const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
     AppendVectorRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetVectorRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -262,10 +262,10 @@
   // value.
   template <typename T>
   void SetVectorRegisterValues(
-      const std::vector<tuple<std::string, Span<const T>>> &values) {
-    for (auto &[vreg_name, span] : values) {
-      auto *vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
-      auto *db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
+      const std::vector<tuple<std::string, Span<const T>>>& values) {
+    for (auto& [vreg_name, span] : values) {
+      auto* vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
+      auto* db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
       db->template Set<T>(span);
       vreg->SetDataBuffer(db);
       db->DecRef();
@@ -273,7 +273,7 @@
   }
 
   // Initializes the semantic function of the instruction object.
-  void SetSemanticFunction(Instruction *inst,
+  void SetSemanticFunction(Instruction* inst,
                            Instruction::SemanticFunction fcn) {
     inst->set_semantic_function(fcn);
   }
@@ -293,7 +293,7 @@
 
   // Configure the vector unit according to the vtype and vlen values.
   void ConfigureVectorUnit(uint32_t vtype, uint32_t vlen) {
-    Instruction *inst = new Instruction(state_);
+    Instruction* inst = new Instruction(state_);
     AppendImmediateOperands<uint32_t>(inst, {vlen, vtype});
     SetSemanticFunction(inst, absl::bind_front(&Vsetvl, true, false));
     inst->Execute(nullptr);
@@ -303,7 +303,7 @@
   template <typename T>
   T ComputeValue(int address) {
     T value = 0;
-    uint8_t *ptr = reinterpret_cast<uint8_t *>(&value);
+    uint8_t* ptr = reinterpret_cast<uint8_t*>(&value);
     for (int j = 0; j < sizeof(T); j++) {
       ptr[j] = (address + j) & 0xff;
     }
@@ -815,7 +815,7 @@
         reg_span[i] = static_cast<T>(reg * reg_span.size() + i + 1);
       }
     }
-    auto *clear_mem_db = state_->db_factory()->Allocate<T>(0x8000);
+    auto* clear_mem_db = state_->db_factory()->Allocate<T>(0x8000);
     memset(clear_mem_db->raw_ptr(), 0, 0x8000);
     // Iterate over different lmul values.
     for (int lmul_index = 0; lmul_index < 7; lmul_index++) {
@@ -833,7 +833,7 @@
         instruction_->Execute(nullptr);
 
         // Check memory values.
-        auto *data_db = state_->db_factory()->Allocate<T>(1);
+        auto* data_db = state_->db_factory()->Allocate<T>(1);
         uint64_t base = kDataStoreAddress;
         T value = 1;
         for (int i = 0; i < 8 * kVectorLengthInBytes / sizeof(T); i++) {
@@ -883,7 +883,7 @@
       }
     }
 
-    auto *data_db = state_->db_factory()->Allocate<ValueType>(1);
+    auto* data_db = state_->db_factory()->Allocate<ValueType>(1);
     // Iterate over different lmul values.
     for (int lmul_index = 0; lmul_index < 7; lmul_index++) {
       // Configure vector unit.
@@ -976,7 +976,7 @@
 
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
     // Can load all the data in one load, so set the data_db size accordingly.
-    auto *data_db =
+    auto* data_db =
         state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes * 8);
     // Iterate over legal values in the nf field.
     for (int nf = 1; nf < 8; nf++) {
@@ -1089,7 +1089,7 @@
 
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
 
-    auto *data_db = state_->db_factory()->Allocate<T>(1);
+    auto* data_db = state_->db_factory()->Allocate<T>(1);
     // Iterate over legal values in the nf field.
     for (int nf = 1; nf < 8; nf++) {
       int num_fields = nf + 1;
@@ -1211,7 +1211,7 @@
     int index_values_per_reg = kVectorLengthInBytes / sizeof(IndexType);
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
 
-    auto *data_db = state_->db_factory()->Allocate<T>(1);
+    auto* data_db = state_->db_factory()->Allocate<T>(1);
     // Iterate over legal values in the nf field.
     for (int num_fields = 1; num_fields < 8; num_fields++) {
       // Set the number of fields in the source operand.
@@ -1341,13 +1341,13 @@
   }
 
  protected:
-  CheriotRegister *creg_[32];
-  RVVectorRegister *vreg_[32];
-  CheriotState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
-  TaggedFlatDemandMemory *memory_;
-  CheriotVectorState *rv_vector_;
+  CheriotRegister* creg_[32];
+  RVVectorRegister* vreg_[32];
+  CheriotState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
+  TaggedFlatDemandMemory* memory_;
+  CheriotVectorState* rv_vector_;
 };
 
 // Test the vector configuration set instructions. There are three separate
@@ -1798,7 +1798,7 @@
 
   // Verify result.
   EXPECT_FALSE(rv_vector_->vector_exception());
-  auto *data_db = state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes);
+  auto* data_db = state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes);
   state_->DbgLoadMemory(kDataStoreAddress, data_db);
   auto span = data_db->Get<uint8_t>();
   for (int i = 0; i < kVectorLengthInBytes; i++) {

diff --git a/cheriot/test/riscv_cheriot_vector_opi_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_opi_instructions_test.cc
index 268099f..08d5334 100644
--- a/cheriot/test/riscv_cheriot_vector_opi_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_opi_instructions_test.cc

@@ -2036,8 +2036,8 @@
 }
 
 // This wrapper function factors out the main body of the Vmvr test.
-void VmvrWrapper(int num_reg, RiscVCheriotVectorInstructionsTest *tester,
-                 Instruction *inst) {
+void VmvrWrapper(int num_reg, RiscVCheriotVectorInstructionsTest* tester,
+                 Instruction* inst) {
   tester->SetSemanticFunction(absl::bind_front(&Vmvr, num_reg));
   // Number of elements per vector register.
   constexpr int vs2_size = kVectorLengthInBytes / sizeof(uint64_t);
@@ -2087,7 +2087,7 @@
 
 // Templated helper functions for Vssr testing.
 template <typename T>
-T VssrHelper(RiscVCheriotVectorInstructionsTest *tester, T vs2, T vs1,
+T VssrHelper(RiscVCheriotVectorInstructionsTest* tester, T vs2, T vs1,
              int rounding_mode) {
   using UT = typename MakeUnsigned<T>::type;
   int max_shift = (sizeof(T) << 3) - 1;
@@ -2105,8 +2105,8 @@
 // These wrapper functions simplify the test bodies, and make it a little
 // easier to avoid errors due to type and sew specifications.
 template <typename T>
-void VssrVVWrapper(absl::string_view base_name, Instruction *inst,
-                   RiscVCheriotVectorInstructionsTest *tester) {
+void VssrVVWrapper(absl::string_view base_name, Instruction* inst,
+                   RiscVCheriotVectorInstructionsTest* tester) {
   // Iterate across rounding modes.
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2118,8 +2118,8 @@
   }
 }
 template <typename T>
-void VssrVXWrapper(absl::string_view base_name, Instruction *inst,
-                   RiscVCheriotVectorInstructionsTest *tester) {
+void VssrVXWrapper(absl::string_view base_name, Instruction* inst,
+                   RiscVCheriotVectorInstructionsTest* tester) {
   // Iterate across rounding modes.
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2204,8 +2204,8 @@
 
 // Templated helper functions for Vnclip/Vnclipu instructions.
 template <typename T, typename WideT>
-T VnclipHelper(RiscVCheriotVectorInstructionsTest *tester, WideT vs2, T vs1,
-               int rm, CheriotVectorState *rv_vector) {
+T VnclipHelper(RiscVCheriotVectorInstructionsTest* tester, WideT vs2, T vs1,
+               int rm, CheriotVectorState* rv_vector) {
   auto vs1_16 = static_cast<WideT>(vs1);
   auto shifted = VssrHelper<WideT>(tester, vs2, vs1_16, rm);
   if (shifted < std::numeric_limits<T>::min()) {
@@ -2220,8 +2220,8 @@
 }
 
 template <typename T>
-void VnclipVVWrapper(absl::string_view base_name, Instruction *inst,
-                     RiscVCheriotVectorInstructionsTest *tester) {
+void VnclipVVWrapper(absl::string_view base_name, Instruction* inst,
+                     RiscVCheriotVectorInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2233,8 +2233,8 @@
   }
 }
 template <typename T>
-void VnclipVXWrapper(absl::string_view base_name, Instruction *inst,
-                     RiscVCheriotVectorInstructionsTest *tester) {
+void VnclipVXWrapper(absl::string_view base_name, Instruction* inst,
+                     RiscVCheriotVectorInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2304,8 +2304,8 @@
 
 // Vector fractional multiply with rounding and saturation.
 template <typename T>
-T VsmulHelper(RiscVCheriotVectorInstructionsTest *tester, T vs2, T vs1, int rm,
-              CheriotVectorState *rv_vector) {
+T VsmulHelper(RiscVCheriotVectorInstructionsTest* tester, T vs2, T vs1, int rm,
+              CheriotVectorState* rv_vector) {
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
   WT vs1_w = static_cast<WT>(vs1);
@@ -2321,8 +2321,8 @@
 }
 
 template <typename T>
-void VsmulVVWrapper(absl::string_view base_name, Instruction *inst,
-                    RiscVCheriotVectorInstructionsTest *tester) {
+void VsmulVVWrapper(absl::string_view base_name, Instruction* inst,
+                    RiscVCheriotVectorInstructionsTest* tester) {
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
     tester->BinaryOpTestHelperVV<T, T, T>(
@@ -2333,8 +2333,8 @@
   }
 }
 template <typename T>
-void VsmulVXWrapper(absl::string_view base_name, Instruction *inst,
-                    RiscVCheriotVectorInstructionsTest *tester) {
+void VsmulVXWrapper(absl::string_view base_name, Instruction* inst,
+                    RiscVCheriotVectorInstructionsTest* tester) {
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
     tester->BinaryOpTestHelperVV<T, T, T>(

diff --git a/cheriot/test/riscv_cheriot_vector_opm_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_opm_instructions_test.cc
index 9ca5087..9e736ac 100644
--- a/cheriot/test/riscv_cheriot_vector_opm_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_opm_instructions_test.cc

@@ -21,10 +21,13 @@
 
 #include "absl/base/casts.h"
 #include "absl/log/check.h"
+#include "absl/numeric/int128.h"
+#include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
 #include "cheriot/test/riscv_cheriot_vector_instructions_test_base.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/instruction.h"
+#include "mpact/sim/generic/type_helpers.h"
 
 namespace {
 
@@ -123,7 +126,7 @@
 
 // Helper functions for averaging add and subtract.
 template <typename T>
-T VaaddHelper(RiscVCheriotVectorOpmInstructionsTest *tester, T vs2, T vs1) {
+T VaaddHelper(RiscVCheriotVectorOpmInstructionsTest* tester, T vs2, T vs1) {
   // Create two sums, lower nibble, and the upper part. Then combine after
   // rounding.
   T vs2_l = vs2 & 0xf;
@@ -141,7 +144,7 @@
 }
 
 template <typename T>
-T VasubHelper(RiscVCheriotVectorOpmInstructionsTest *tester, T vs2, T vs1) {
+T VasubHelper(RiscVCheriotVectorOpmInstructionsTest* tester, T vs2, T vs1) {
   // Create two diffs, lower nibble, and the upper part. Then combine after
   // rounding.
   T vs2_l = vs2 & 0xf;
@@ -160,7 +163,7 @@
 
 // Vaaddu vector-vector test helper function.
 template <typename T>
-inline void VaadduVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VaadduVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaaddu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -171,7 +174,7 @@
 
 // Vaaddu vector-scalar test helper function.
 template <typename T>
-inline void VaadduVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VaadduVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaaddu);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -203,7 +206,7 @@
 
 // Vaadd vector-vector test helper function.
 template <typename T>
-inline void VaaddVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VaaddVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaadd);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -214,7 +217,7 @@
 
 // Vaadd vector-vector test helper function.
 template <typename T>
-inline void VaaddVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VaaddVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaadd);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -246,7 +249,7 @@
 
 // Vasubu vector-vector test helper function.
 template <typename T>
-inline void VasubuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VasubuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasubu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vasubu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -256,7 +259,7 @@
 }
 // Vasubu vector-scalar test helper function.
 template <typename T>
-inline void VasubuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VasubuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasubu);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vasubu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -288,7 +291,7 @@
 
 // Vasub vector-vector test helper function.
 template <typename T>
-inline void VasubVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VasubVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasub);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vasub", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -298,7 +301,7 @@
 }
 // Vasub vector-scalar test helper function.
 template <typename T>
-inline void VasubVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VasubVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasub);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vasub", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -381,7 +384,7 @@
 
 // Vdivu vector-vector test helper function.
 template <typename T>
-inline void VdivuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VdivuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdivu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vdivu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -392,7 +395,7 @@
 }
 // Vdivu vector-scalar test helper function.
 template <typename T>
-inline void VdivuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VdivuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdivu);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vdivu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -425,7 +428,7 @@
 
 // Vdiv vector-vector test helper function.
 template <typename T>
-inline void VdivVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VdivVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdiv);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vdiv", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -436,7 +439,7 @@
 }
 // Vdiv vector-scalar test helper function.
 template <typename T>
-inline void VdivVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VdivVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdiv);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vdiv", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -469,7 +472,7 @@
 
 // Vremu vector-vector test helper function.
 template <typename T>
-inline void VremuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VremuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vremu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vremu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -480,7 +483,7 @@
 }
 // Vremu vector-scalar test helper function.
 template <typename T>
-inline void VremuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VremuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vremu);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vremu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -513,7 +516,7 @@
 
 // Vrem vector-vector test helper function.
 template <typename T>
-inline void VremVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VremVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vrem);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vrem", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -524,7 +527,7 @@
 }
 // Vrem vector-scalar test helper function.
 template <typename T>
-inline void VremVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VremVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vrem);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vrem", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -557,7 +560,7 @@
 
 // Vmulhu vector-vector test helper function.
 template <typename T>
-inline void VmulhuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulhu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmulhu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -570,7 +573,7 @@
 }
 // Vmulhu vector-scalar test helper function.
 template <typename T>
-inline void VmulhuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulhu);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vmulhu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -605,7 +608,7 @@
 
 // Vmulh vector-vector test helper function.
 template <typename T>
-inline void VmulhVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulh);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmulh", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -619,7 +622,7 @@
 
 // Vmulh vector-scalar test helper function.
 template <typename T>
-inline void VmulhVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulh);
   tester->BinaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vmulh", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -654,7 +657,7 @@
 
 // Vmul vector-vector test helper function.
 template <typename T>
-inline void VmulVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vmul);
   tester->BinaryOpTestHelperVV<T, T, T>(
@@ -666,7 +669,7 @@
 
 // Vmul vector-scalar test helper function.
 template <typename T>
-inline void VmulVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vmul);
   tester->BinaryOpTestHelperVX<T, T, T>(
@@ -699,7 +702,7 @@
 
 // Vmulhsu vector-vector test helper function.
 template <typename T>
-inline void VmulhsuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhsuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using ST = typename std::make_signed<T>::type;
   tester->SetSemanticFunction(&Vmulhsu);
   tester->BinaryOpTestHelperVV<T, ST, T>(
@@ -714,7 +717,7 @@
 
 // Vmulhsu vector-scalar test helper function.
 template <typename T>
-inline void VmulhsuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmulhsuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using ST = typename std::make_signed<T>::type;
   tester->SetSemanticFunction(&Vmulhsu);
   tester->BinaryOpTestHelperVX<T, ST, T>(
@@ -750,7 +753,7 @@
 
 // Vmadd vector-vector test helper function.
 template <typename T>
-inline void VmaddVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmaddVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmadd);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmadd", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -768,7 +771,7 @@
 
 // Vmadd vector-scalar test helper function.
 template <typename T>
-inline void VmaddVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmaddVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmadd);
   tester->TernaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vmadd", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -807,7 +810,7 @@
 
 // Vnmsub vector-vector test helper function.
 template <typename T>
-inline void VnmsubVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VnmsubVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsub);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vnmsub", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -825,7 +828,7 @@
 
 // Vnmsub vector-scalar test helper function.
 template <typename T>
-inline void VnmsubVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VnmsubVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsub);
   tester->TernaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vnmsub", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -864,7 +867,7 @@
 
 // Vmacc vector-vector test helper function.
 template <typename T>
-inline void VmaccVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmaccVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmacc);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmacc", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -882,7 +885,7 @@
 
 // Vmacc vector-scalar test helper function.
 template <typename T>
-inline void VmaccVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VmaccVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmacc);
   tester->TernaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vmacc", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -921,7 +924,7 @@
 
 // Vnmsac vector-vector test helper function.
 template <typename T>
-inline void VnmsacVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VnmsacVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsac);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vnmsac", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -939,7 +942,7 @@
 
 // Vnmsac vector-scalar test helper function.
 template <typename T>
-inline void VnmsacVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VnmsacVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsac);
   tester->TernaryOpTestHelperVX<T, T, T>(
       absl::StrCat("Vnmsac", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -978,7 +981,7 @@
 
 // Vwaddu vector-vector test helper function.
 template <typename T>
-inline void VwadduVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwadduVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -990,7 +993,7 @@
 
 // Vwaddu vector-scalar test helper function.
 template <typename T>
-inline void VwadduVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwadduVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddu);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1021,7 +1024,7 @@
 
 // Vwsubu vector-vector test helper function.
 template <typename T>
-inline void VwsubuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1033,7 +1036,7 @@
 
 // Vwsubu vector-scalar test helper function.
 template <typename T>
-inline void VwsubuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubu);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1064,7 +1067,7 @@
 
 // Vwadd vector-vector test helper function.
 template <typename T>
-inline void VwaddVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwaddVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadd);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1076,7 +1079,7 @@
 
 // Vwadd vector-scalar test helper function.
 template <typename T>
-inline void VwaddVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwaddVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadd);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1107,7 +1110,7 @@
 
 // Vwsub vector-vector test helper function.
 template <typename T>
-inline void VwsubVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsub);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1122,7 +1125,7 @@
 
 // Vwsub vector-scalar test helper function.
 template <typename T>
-inline void VwsubVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsub);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1156,7 +1159,7 @@
 
 // Vwadduw vector-vector test helper function.
 template <typename T>
-inline void VwadduwVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwadduwVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadduw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1167,7 +1170,7 @@
 
 // Vwadduw vector-scalar test helper function.
 template <typename T>
-inline void VwadduwVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwadduwVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadduw);
   tester->BinaryOpTestHelperVX<WT, WT, T>(
@@ -1197,7 +1200,7 @@
 
 // Vwsubuw vector-vector test helper function.
 template <typename T>
-inline void VwsubuwVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubuwVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubuw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1208,7 +1211,7 @@
 
 // Vwsubuw vector-scalar test helper function.
 template <typename T>
-inline void VwsubuwVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubuwVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubuw);
   tester->BinaryOpTestHelperVX<WT, WT, T>(
@@ -1238,7 +1241,7 @@
 
 // Vwaddw vector-vector test helper function.
 template <typename T>
-inline void VwaddwVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwaddwVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1249,7 +1252,7 @@
 
 // Vwaddw vector-scalar test helper function.
 template <typename T>
-inline void VwaddwVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwaddwVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddw);
   tester->BinaryOpTestHelperVX<WT, WT, T>(
@@ -1279,7 +1282,7 @@
 
 // Vwsubw vector-vector test helper function.
 template <typename T>
-inline void VwsubwVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubwVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1290,7 +1293,7 @@
 
 // Vwsubw vector-scalar test helper function.
 template <typename T>
-inline void VwsubwVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwsubwVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubw);
   tester->BinaryOpTestHelperVX<WT, WT, T>(
@@ -1320,7 +1323,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmuluVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmuluVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmulu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1332,7 +1335,7 @@
 
 // Vwmulu vector-scalar test helper function.
 template <typename T>
-inline void VwmuluVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmuluVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmulu);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1363,7 +1366,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmulVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmulVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmul);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1375,7 +1378,7 @@
 
 // Vwmul vector-scalar test helper function.
 template <typename T>
-inline void VwmulVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmulVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmul);
   tester->BinaryOpTestHelperVX<WT, T, T>(
@@ -1406,7 +1409,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmulsuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmulsuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmulsu);
@@ -1419,7 +1422,7 @@
 
 // Vwmulsu vector-scalar test helper function.
 template <typename T>
-inline void VwmulsuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmulsuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmulsu);
@@ -1451,7 +1454,7 @@
 
 // Vmaccu vector-vector test helper function.
 template <typename T>
-inline void VwmaccuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmaccu);
   tester->TernaryOpTestHelperVV<WT, T, T>(
@@ -1463,7 +1466,7 @@
 
 // Vwmaccu vector-scalar test helper function.
 template <typename T>
-inline void VwmaccuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmaccu);
   tester->TernaryOpTestHelperVX<WT, T, T>(
@@ -1492,7 +1495,7 @@
 
 // Vmacc vector-vector test helper function.
 template <typename T>
-inline void VwmaccVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmacc);
   tester->TernaryOpTestHelperVV<WT, T, T>(
@@ -1509,7 +1512,7 @@
 
 // Vwmacc vector-scalar test helper function.
 template <typename T>
-inline void VwmaccVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmacc);
   tester->TernaryOpTestHelperVX<WT, T, T>(
@@ -1543,7 +1546,7 @@
 
 // Vmaccus vector-vector test helper function.
 template <typename T>
-inline void VwmaccusVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccusVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccus);
@@ -1561,7 +1564,7 @@
 
 // Vwmaccus vector-scalar test helper function.
 template <typename T>
-inline void VwmaccusVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccusVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccus);
@@ -1596,7 +1599,7 @@
 
 // Vmaccsu vector-vector test helper function.
 template <typename T>
-inline void VwmaccsuVVHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccsuVVHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccsu);
@@ -1614,7 +1617,7 @@
 
 // Vwmaccsu vector-scalar test helper function.
 template <typename T>
-inline void VwmaccsuVXHelper(RiscVCheriotVectorOpmInstructionsTest *tester) {
+inline void VwmaccsuVXHelper(RiscVCheriotVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccsu);

diff --git a/cheriot/test/riscv_cheriot_vector_permute_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_permute_instructions_test.cc
index 8fd7ad5..6532d26 100644
--- a/cheriot/test/riscv_cheriot_vector_permute_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_permute_instructions_test.cc

@@ -45,9 +45,9 @@
 
 // Helper function for vector-vector vrgather instructions.
 template <typename T, typename I>
-void VrgatherVVHelper(RiscVCheriotVectorPermuteInstructionsTest *tester,
-                      Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void VrgatherVVHelper(RiscVCheriotVectorPermuteInstructionsTest* tester,
+                      Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   // Configure vector unit for sew and maximum lmul.
   uint32_t vtype = 0;
   int max_regs = 8;
@@ -115,9 +115,9 @@
 
 // Helper function for vector-scalar vrgather instructions.
 template <typename T>
-void VrgatherVSHelper(RiscVCheriotVectorPermuteInstructionsTest *tester,
-                      Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void VrgatherVSHelper(RiscVCheriotVectorPermuteInstructionsTest* tester,
+                      Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   // Configure vector unit.
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
@@ -255,9 +255,9 @@
 
 // Helper function for slideup/down instructions.
 template <typename T>
-void SlideHelper(RiscVCheriotVectorPermuteInstructionsTest *tester,
-                 Instruction *inst, bool is_slide_up) {
-  auto *rv_vector = tester->rv_vector();
+void SlideHelper(RiscVCheriotVectorPermuteInstructionsTest* tester,
+                 Instruction* inst, bool is_slide_up) {
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);
@@ -401,9 +401,9 @@
 }
 
 template <typename T>
-void Slide1Helper(RiscVCheriotVectorPermuteInstructionsTest *tester,
-                  Instruction *inst, bool is_slide_up) {
-  auto *rv_vector = tester->rv_vector();
+void Slide1Helper(RiscVCheriotVectorPermuteInstructionsTest* tester,
+                  Instruction* inst, bool is_slide_up) {
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);
@@ -539,9 +539,9 @@
 }
 
 template <typename T>
-void CompressHelper(RiscVCheriotVectorPermuteInstructionsTest *tester,
-                    Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void CompressHelper(RiscVCheriotVectorPermuteInstructionsTest* tester,
+                    Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);

diff --git a/cheriot/test/riscv_cheriot_vector_reduction_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_reduction_instructions_test.cc
index b7b6b28..7592879 100644
--- a/cheriot/test/riscv_cheriot_vector_reduction_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_reduction_instructions_test.cc

@@ -20,7 +20,9 @@
 #include <vector>
 
 #include "absl/random/random.h"
+#include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
+#include "absl/types/span.h"
 #include "cheriot/test/riscv_cheriot_vector_instructions_test_base.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/instruction.h"
@@ -49,7 +51,7 @@
     : public RiscVCheriotVectorInstructionsTestBase {
  public:
   template <typename Vd, typename Vs2>
-  void ReductionOpTestHelper(absl::string_view name, int sew, Instruction *inst,
+  void ReductionOpTestHelper(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vd, Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2)) {

diff --git a/cheriot/test/riscv_cheriot_vector_true_test.cc b/cheriot/test/riscv_cheriot_vector_true_test.cc
index 05b73f2..f980d63 100644
--- a/cheriot/test/riscv_cheriot_vector_true_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_true_test.cc

@@ -41,12 +41,12 @@
   }
 
   TaggedFlatDemandMemory memory_;
-  CheriotState *state_;
-  CheriotVectorState *vstate_;
+  CheriotState* state_;
+  CheriotVectorState* vstate_;
 };
 
 TEST_F(CheriotVectorTrueTest, Initial) {
-  auto *op = new CheriotVectorTrueOperand(state_);
+  auto* op = new CheriotVectorTrueOperand(state_);
   for (int i = 0; i < op->shape()[0]; ++i) {
     EXPECT_EQ(op->AsUint8(i), 0xff) << "element: " << i;
   }
@@ -54,8 +54,8 @@
 }
 
 TEST_F(CheriotVectorTrueTest, Register) {
-  auto *op = new CheriotVectorTrueOperand(state_);
-  auto *reg = op->GetRegister(0);
+  auto* op = new CheriotVectorTrueOperand(state_);
+  auto* reg = op->GetRegister(0);
   auto span = reg->data_buffer()->Get<uint8_t>();
   for (int i = 0; i < op->shape()[0]; ++i) {
     EXPECT_EQ(span[i], 0xff) << "element: " << i;

diff --git a/cheriot/test/riscv_cheriot_vector_unary_instructions_test.cc b/cheriot/test/riscv_cheriot_vector_unary_instructions_test.cc
index 29a4a69..082b549 100644
--- a/cheriot/test/riscv_cheriot_vector_unary_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_vector_unary_instructions_test.cc

@@ -527,8 +527,8 @@
 
 // Helper function for testing Viota instructions.
 template <typename T>
-void TestViota(RiscVCheriotVectorUnaryInstructionsTest *tester,
-               Instruction *inst) {
+void TestViota(RiscVCheriotVectorUnaryInstructionsTest* tester,
+               Instruction* inst) {
   // Set up vector unit.
   int byte_sew = sizeof(T);
   uint32_t vtype =
@@ -603,8 +603,8 @@
 
 // Helper function for testing Vid instructions.
 template <typename T>
-void TestVid(RiscVCheriotVectorUnaryInstructionsTest *tester,
-             Instruction *inst) {
+void TestVid(RiscVCheriotVectorUnaryInstructionsTest* tester,
+             Instruction* inst) {
   // Initialize the vector unit.
   int byte_sew = sizeof(T);
   uint32_t vtype =

diff --git a/cheriot/test/riscv_cheriot_zicsr_instructions_test.cc b/cheriot/test/riscv_cheriot_zicsr_instructions_test.cc
index 6d75d87..b42c349 100644
--- a/cheriot/test/riscv_cheriot_zicsr_instructions_test.cc
+++ b/cheriot/test/riscv_cheriot_zicsr_instructions_test.cc

@@ -67,7 +67,7 @@
     instruction_->set_size(4);
     state_->set_on_trap([this](bool is_interrupt, uint64_t trap_value,
                                uint64_t exception_code, uint64_t epc,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
       return TrapHandler(is_interrupt, trap_value, exception_code, epc, inst);
     });
   }
@@ -80,25 +80,25 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
+  void AppendRegisterOperands(Instruction* inst,
                               absl::Span<const std::string> sources,
                               absl::Span<const std::string> destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -107,9 +107,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<CheriotRegister::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -124,7 +124,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<CheriotRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<CheriotRegister>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -132,23 +132,23 @@
   // information for checks.
   bool TrapHandler(bool is_interrupt, uint64_t trap_value,
                    uint64_t exception_code, uint64_t epc,
-                   const Instruction *inst);
+                   const Instruction* inst);
 
-  TaggedFlatDemandMemory *mem_;
-  RiscV32SimpleCsr *csr_;
-  CheriotState *state_;
-  Instruction *instruction_;
+  TaggedFlatDemandMemory* mem_;
+  RiscV32SimpleCsr* csr_;
+  CheriotState* state_;
+  Instruction* instruction_;
   bool trap_taken_ = false;
   bool trap_is_interrupt_ = false;
   uint64_t trap_value_ = 0;
   uint64_t trap_exception_code_ = 0;
   uint64_t trap_epc_ = 0;
-  const Instruction *trap_inst_ = nullptr;
+  const Instruction* trap_inst_ = nullptr;
 };
 
 bool ZicsrInstructionsTest::TrapHandler(bool is_interrupt, uint64_t trap_value,
                                         uint64_t exception_code, uint64_t epc,
-                                        const Instruction *inst) {
+                                        const Instruction* inst) {
   trap_taken_ = true;
   trap_is_interrupt_ = is_interrupt;
   trap_value_ = trap_value;
@@ -170,7 +170,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrw) {
   auto result = state_->csr_set()->GetCsr(kMScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -190,7 +190,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrs) {
   auto result = state_->csr_set()->GetCsr(kMScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -209,7 +209,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrc) {
   auto result = state_->csr_set()->GetCsr(kMScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -228,7 +228,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrwNr) {
   auto result = state_->csr_set()->GetCsr(kMScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -247,7 +247,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrNw) {
   auto result = state_->csr_set()->GetCsr(kMScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});