diff --git a/cheriot/cheriot_renode.cc b/cheriot/cheriot_renode.cc
index da29a83..4ab981b 100644
--- a/cheriot/cheriot_renode.cc
+++ b/cheriot/cheriot_renode.cc
@@ -469,6 +469,10 @@
     auto *cfg = cheriot_top_->GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return status;
+    // Hook the cache into the memory port.
+    auto *dcache = cheriot_top_->dcache();
+    dcache->set_tagged_memory(cheriot_top_->state()->tagged_memory());
+    cheriot_top_->state()->set_tagged_memory(dcache);
   }
   return absl::OkStatus();
 }
diff --git a/cheriot/cheriot_top.cc b/cheriot/cheriot_top.cc
index d683b61..8643188 100644
--- a/cheriot/cheriot_top.cc
+++ b/cheriot/cheriot_top.cc
@@ -103,6 +103,7 @@
   if (branch_trace_db_ != nullptr) branch_trace_db_->DecRef();
 
   delete icache_;
+  delete dcache_;
   if (inst_db_) inst_db_->DecRef();
   delete rv_bp_manager_;
   delete cheriot_decode_cache_;
diff --git a/cheriot/mpact_cheriot.cc b/cheriot/mpact_cheriot.cc
index dc6185f..ced488d 100644
--- a/cheriot/mpact_cheriot.cc
+++ b/cheriot/mpact_cheriot.cc
@@ -156,8 +156,9 @@
 ABSL_FLAG(uint64_t, clint, 0x0200'0000ULL, "Base address of clint");
 ABSL_FLAG(uint64_t, uart, 0x1000'0000ULL, "Base address of uart");
 
-// Flag to enable and configure the instruction cache.
+// Flag to enable and configure the instruction and data caches.
 ABSL_FLAG(std::string, icache, "", "Instruction cache configuration");
+ABSL_FLAG(std::string, dcache, "", "Data cache configuration");
 
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
@@ -301,7 +302,18 @@
     if (!status.ok()) return -1;
   }
 
-  // TODO: enable dcache.
+  if (!absl::GetFlag(FLAGS_dcache).empty()) {
+    ComponentValueEntry dcache_value;
+    dcache_value.set_name("dcache");
+    dcache_value.set_string_value(absl::GetFlag(FLAGS_dcache));
+    auto *cfg = cheriot_top.GetConfig("dcache");
+    auto status = cfg->Import(&dcache_value);
+    if (!status.ok()) return -1;
+    // Hook the cache into the memory port.
+    auto *dcache = cheriot_top.dcache();
+    dcache->set_memory(cheriot_top.state()->tagged_memory());
+    cheriot_top.state()->set_tagged_memory(dcache);
+  }
 
   // Enable instruction profiling if the flag is set.
   InstructionProfiler *inst_profiler = nullptr;