)]}'
{
  "commit": "11806ed385da07b889bbf300708bfe4ee6fd7cae",
  "tree": "334397c7aac0422d34fa92c82c0142832d73d1ec",
  "parents": [
    "be8eeb781d7adcdbefa12c942c49fda0471aefaa"
  ],
  "author": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Thu Jan 16 11:35:32 2025 -0800"
  },
  "committer": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Thu Jan 16 15:25:05 2025 -0800"
  },
  "message": "This makes a couple of changes to how the assembler works.\n\n- Comments are removed earlier in the scanning, and do not have to be\n  accounted for in later regex matches.\n- Multiline instructions are allowed if the newline is escaped.\n  - This is done to support cases where the target architecture is a VLIW\n    where the instructions in one bundle may be spread over multiple lines.\n- The class impelementing the OpcodeAssemblerInterface is responsible to\n  add any symbols that occur on the same line(s) as instructions. Labels that\n  occur on an unescaped line by itself will be handled by SimpleAssembler.\n  - If the target ISA is a VLIW, the class implementing the\n    OpcodeAssemblerInterface is responsible for breaking the multiple\n    instructions up into separate strings and passing each such string to the\n    corresponding \"slot matcher\".\n\nPiperOrigin-RevId: 716315088\nChange-Id: Ic509d6b8f5c42ffff41796967f5eb365e42d1720\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fc1ff3e6f761280c4aa4b0f7a2af86132864e360",
      "old_mode": 33188,
      "old_path": "riscv/riscv64g_as_main.cc",
      "new_id": "3893308194c3667215892a8e5ad1ddeb011d2237",
      "new_mode": 33188,
      "new_path": "riscv/riscv64g_as_main.cc"
    }
  ]
}