diff --git a/riscv/BUILD b/riscv/BUILD
index d3ccbff..67b9439 100644
--- a/riscv/BUILD
+++ b/riscv/BUILD
@@ -255,11 +255,15 @@
 cc_library(
     name = "riscv_rvm23_instructions",
     srcs = [
+        "riscv_zhintpause_instructions.cc",
         "riscv_zicond_instructions.cc",
+        "riscv_zihintntl_instructions.cc",
         "riscv_zimop_instructions.cc",
     ],
     hdrs = [
+        "riscv_zhintpause_instructions.h",
         "riscv_zicond_instructions.h",
+        "riscv_zihintntl_instructions.h",
         "riscv_zimop_instructions.h",
     ],
     copts = [
@@ -368,7 +372,9 @@
         "riscv32v.isa",
         "riscv32zb.isa",
         "riscv_vector.isa",
+        "riscv_zhintpause.isa",
         "riscv_zicond.isa",
+        "riscv_zihintntl.isa",
         "riscv_zimop.isa",
     ],
     isa_name = "RVM23",
@@ -390,7 +396,9 @@
         "riscv32g.bin_fmt",
         "riscv32v.bin_fmt",
         "riscv32zb.bin_fmt",
+        "riscv_zhintpause.bin_fmt",
         "riscv_zicond.bin_fmt",
+        "riscv_zihintntl.bin_fmt",
         "riscv_zimop.bin_fmt",
     ],
     prefix = "rvm23",
diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt
index 22d8f8d..d281e06 100644
--- a/riscv/riscv32g.bin_fmt
+++ b/riscv/riscv32g.bin_fmt
@@ -159,7 +159,7 @@
   slli   : RType  : func7 == 0b000'0000, func3==0b001, opcode == 0b001'0011;
   srli   : RType  : func7 == 0b000'0000, func3==0b101, opcode == 0b001'0011;
   srai   : RType  : func7 == 0b010'0000, func3==0b101, opcode == 0b001'0011;
-  add    : RType  : func7 == 0b000'0000, func3==0b000, opcode == 0b011'0011;
+  add    : RType  : func7 == 0b000'0000, func3==0b000, rd != 0, opcode == 0b011'0011;
   sub    : RType  : func7 == 0b010'0000, func3==0b000, opcode == 0b011'0011;
   sll    : RType  : func7 == 0b000'0000, func3==0b001, opcode == 0b011'0011;
   slt    : RType  : func7 == 0b000'0000, func3==0b010, opcode == 0b011'0011;
diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt
index 9870382..9e52660 100644
--- a/riscv/riscv64g.bin_fmt
+++ b/riscv/riscv64g.bin_fmt
@@ -187,7 +187,7 @@
   slliw  : RType  : func7 == 0b000'0000, func3==0b001, opcode == 0b001'1011;
   srliw  : RType  : func7 == 0b000'0000, func3==0b101, opcode == 0b001'1011;
   sraiw  : RType  : func7 == 0b010'0000, func3==0b101, opcode == 0b001'1011;
-  add    : RType  : func7 == 0b000'0000, func3==0b000, opcode == 0b011'0011;
+  add    : RType  : func7 == 0b000'0000, func3==0b000, rd != 0,  opcode == 0b011'0011;
   addw   : RType  : func7 == 0b000'0000, func3==0b000, opcode == 0b011'1011;
   sub    : RType  : func7 == 0b010'0000, func3==0b000, opcode == 0b011'0011;
   subw   : RType  : func7 == 0b010'0000, func3==0b000, opcode == 0b011'1011;
diff --git a/riscv/riscv_zhintpause.bin_fmt b/riscv/riscv_zhintpause.bin_fmt
new file mode 100644
index 0000000..792c7e5
--- /dev/null
+++ b/riscv/riscv_zhintpause.bin_fmt
@@ -0,0 +1,19 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This file contains the encoding for the Zhintpause instruction.
+
+instruction group RiscVZhintpause[32] : Inst32Format {
+  pause: Fence : fm == 0, pred == 0b0001, succ == 0, rd == 0, rs1 == 0, opcode == 0b000'1111;
+}
\ No newline at end of file
diff --git a/riscv/riscv_zhintpause.isa b/riscv/riscv_zhintpause.isa
new file mode 100644
index 0000000..a842838
--- /dev/null
+++ b/riscv/riscv_zhintpause.isa
@@ -0,0 +1,29 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This file contains the ISA definition for the Zhintpause instruction.
+
+includes {
+  #include "riscv/riscv_zhintpause_instructions.h"
+}
+
+slot riscv_zhintpause {
+  resources ZeroOp = {next_pc};
+  opcodes {
+    pause{},
+    resources: ZeroOp,
+    disasm: "pause",
+    semfunc: "&RiscVPause";
+  }
+}
\ No newline at end of file
diff --git a/riscv/riscv_zhintpause_instructions.cc b/riscv/riscv_zhintpause_instructions.cc
new file mode 100644
index 0000000..0421184
--- /dev/null
+++ b/riscv/riscv_zhintpause_instructions.cc
@@ -0,0 +1,11 @@
+#include "riscv/riscv_zhintpause_instructions.h"
+
+#include "mpact/sim/generic/instruction.h"
+
+namespace mpact::sim::riscv {
+
+using ::mpact::sim::generic::Instruction;
+
+void RiscVPause(const Instruction *inst) { /* empty */ }
+
+}  // namespace mpact::sim::riscv
diff --git a/riscv/riscv_zhintpause_instructions.h b/riscv/riscv_zhintpause_instructions.h
new file mode 100644
index 0000000..e682d10
--- /dev/null
+++ b/riscv/riscv_zhintpause_instructions.h
@@ -0,0 +1,32 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef THIRD_PARTY_MPACT_RISCV_RISCV_ZHINTPAUSE_INSTRUCTIONS_H_
+#define THIRD_PARTY_MPACT_RISCV_RISCV_ZHINTPAUSE_INSTRUCTIONS_H_
+
+#include "mpact/sim/generic/instruction.h"
+
+// This file declares the semantic function for the RiscV Pause hint
+// instruction.
+
+namespace mpact::sim::riscv {
+
+using ::mpact::sim::generic::Instruction;
+
+// This instruction semantic function takes no source or destination operands.
+void RiscVPause(const Instruction *inst);
+
+}  // namespace mpact::sim::riscv
+
+#endif  // THIRD_PARTY_MPACT_RISCV_RISCV_ZHINTPAUSE_INSTRUCTIONS_H_
diff --git a/riscv/riscv_zihintntl.bin_fmt b/riscv/riscv_zihintntl.bin_fmt
new file mode 100644
index 0000000..39bf985
--- /dev/null
+++ b/riscv/riscv_zihintntl.bin_fmt
@@ -0,0 +1,29 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This file defines the non-temporal localicty hint instruction encodings.
+
+instruction group RiscVZihintntl[32] : Inst32Format {
+  ntl_p1  : RType : func7 == 0b000'0000, rs1 == 0, rs2 == 2, func3 == 0b000, rd == 0, opcode == 0b011'0011;
+  ntl_pall: RType : func7 == 0b000'0000, rs1 == 0, rs2 == 3, func3 == 0b000, rd == 0, opcode == 0b011'0011;
+  ntl_s1  : RType : func7 == 0b000'0000, rs1 == 0, rs2 == 4, func3 == 0b000, rd == 0, opcode == 0b011'0011;
+  ntl_all : RType : func7 == 0b000'0000, rs1 == 0, rs2 == 5, func3 == 0b000, rd == 0, opcode == 0b011'0011;
+};
+
+instruction group RiscVCZihintntl[16] : Inst16Format {
+  c_ntl_p1  : CR : func4 == 0b1001, rs1 == 0, rs2 == 2, op == 0b10;
+  c_ntl_pall: CR : func4 == 0b1001, rs1 == 0, rs2 == 3, op == 0b10;
+  c_ntl_s1  : CR : func4 == 0b1001, rs1 == 0, rs2 == 4, op == 0b10;
+  c_ntl_all : CR : func4 == 0b1001, rs1 == 0, rs2 == 5, op == 0b10;
+}
\ No newline at end of file
diff --git a/riscv/riscv_zihintntl.isa b/riscv/riscv_zihintntl.isa
new file mode 100644
index 0000000..df64759
--- /dev/null
+++ b/riscv/riscv_zihintntl.isa
@@ -0,0 +1,55 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This file defines the non-temporal localicty hint instruction encodings.
+
+includes {
+  #include "riscv/riscv_zihintntl_instructions.h"
+}
+
+slot riscv_zihintntl {
+  default size = 4;
+  opcodes {
+    ntl_p1{},
+      disasm: "ntl.p1",
+      semfunc: "&RiscVNtlP1";
+    ntl_pall{},
+      disasm: "ntl.pall",
+      semfunc: "&RiscVNtlPall";
+    ntl_s1{},
+      disasm: "ntl.s1",
+      semfunc: "&RiscVNtlS1";
+    ntl_all{},
+      disasm: "ntl.all",
+      semfunc: "&RiscVNtlAll";
+  }
+}
+
+slot riscv_czihintntl {
+  default size = 2;
+  opcodes {
+    c_ntl_p1{},
+      disasm: "c.ntl.p1",
+      semfunc: "&RiscVNtlP1";
+    c_ntl_pall{},
+      disasm: "c.ntl.pall",
+      semfunc: "&RiscVNtlPall";
+    c_ntl_s1{},
+      disasm: "c.ntl.s1",
+      semfunc: "&RiscVNtlS1";
+    c_ntl_all{},
+      disasm: "c.ntl.all",
+      semfunc: "&RiscVNtlAll";
+  }
+}
\ No newline at end of file
diff --git a/riscv/riscv_zihintntl_instructions.cc b/riscv/riscv_zihintntl_instructions.cc
new file mode 100644
index 0000000..802139f
--- /dev/null
+++ b/riscv/riscv_zihintntl_instructions.cc
@@ -0,0 +1,14 @@
+#include "riscv/riscv_zihintntl_instructions.h"
+
+#include "mpact/sim/generic/instruction.h"
+
+namespace mpact::sim::riscv {
+
+using ::mpact::sim::generic::Instruction;
+
+void RiscVNtlP1(const Instruction *) { /* empty */ }
+void RiscVNtlPall(const Instruction *) { /* empty */ }
+void RiscVNtlS1(const Instruction *) { /* empty */ }
+void RiscVNtlAll(const Instruction *) { /* empty */ }
+
+}  // namespace mpact::sim::riscv
diff --git a/riscv/riscv_zihintntl_instructions.h b/riscv/riscv_zihintntl_instructions.h
new file mode 100644
index 0000000..e08bd1f
--- /dev/null
+++ b/riscv/riscv_zihintntl_instructions.h
@@ -0,0 +1,35 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef THIRD_PARTY_MPACT_RISCV_RISCV_ZIHINTNTL_INSTRUCTIONS_H_
+#define THIRD_PARTY_MPACT_RISCV_RISCV_ZIHINTNTL_INSTRUCTIONS_H_
+
+#include "mpact/sim/generic/instruction.h"
+
+// This file declares the semantic function for the RiscV non-temporal locality
+// hint instructions.
+
+namespace mpact::sim::riscv {
+
+using ::mpact::sim::generic::Instruction;
+
+// These instructions take no source or destination operands.
+void RiscVNtlP1(const Instruction *);
+void RiscVNtlPall(const Instruction *);
+void RiscVNtlS1(const Instruction *);
+void RiscVNtlAll(const Instruction *);
+
+}  // namespace mpact::sim::riscv
+
+#endif  // THIRD_PARTY_MPACT_RISCV_RISCV_ZIHINTNTL_INSTRUCTIONS_H_
diff --git a/riscv/rvm23.bin_fmt b/riscv/rvm23.bin_fmt
index 5ea41d2..7c13e74 100644
--- a/riscv/rvm23.bin_fmt
+++ b/riscv/rvm23.bin_fmt
@@ -30,10 +30,13 @@
     // Conditional zero.
     RiscVZicond,
     RiscVZimop,
+    RiscVZhintpause,
+    RiscVZihintntl,
   };
   RVM23Inst16 = {
     RiscVCInst16,
     RiscVZcmop,
+    RiscVCZihintntl,
   };
 }
 
@@ -41,3 +44,5 @@
 #include "riscv/riscv32zb.bin_fmt"
 #include "riscv/riscv_zicond.bin_fmt"
 #include "riscv/riscv_zimop.bin_fmt"
+#include "riscv/riscv_zhintpause.bin_fmt"
+#include "riscv/riscv_zihintntl.bin_fmt"
diff --git a/riscv/rvm23.isa b/riscv/rvm23.isa
index c4ed17a..91852a1 100644
--- a/riscv/rvm23.isa
+++ b/riscv/rvm23.isa
@@ -24,6 +24,8 @@
 #include "riscv/riscv_vector.isa"
 #include "riscv/riscv_zicond.isa"
 #include "riscv/riscv_zimop.isa"
+#include "riscv/riscv_zhintpause.isa"
+#include "riscv/riscv_zihintntl.isa"
 
 slot rvm23 :
   riscv32i,
@@ -39,7 +41,10 @@
   riscv32_zb,
   riscv32_zicond,
   riscv32_zimop,
-  riscv_zcmop {
+  riscv_zcmop,
+  riscv_zhintpause,
+  riscv_zihintntl,
+  riscv_czihintntl {
   default opcode =
     disasm: "Illegal instruction at 0x%(@:08x)",
     semfunc: "&RiscVIllegalInstruction";