diff --git a/riscv/riscv32_decoder.cc b/riscv/riscv32_decoder.cc
index 847c03e..809aed0 100644
--- a/riscv/riscv32_decoder.cc
+++ b/riscv/riscv32_decoder.cc
@@ -37,10 +37,11 @@
   riscv_isa_ = std::make_unique<isa32::RiscV32GInstructionSet>(
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa32::RiscV32GEncoding>(state);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa32::OpcodeEnum, isa32::RiscV32GEncoding,
-                          isa32::RiscV32GInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa32::OpcodeEnum,
+                                           isa32::RiscV32GEncoding,
+                                           isa32::RiscV32GInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32Decoder::DecodeInstruction(uint64_t address) {
diff --git a/riscv/riscv32_decoder.h b/riscv/riscv32_decoder.h
index 4926a79..5b96385 100644
--- a/riscv/riscv32_decoder.h
+++ b/riscv/riscv32_decoder.h
@@ -71,9 +71,9 @@
  private:
   RiscVState* state_;
   util::MemoryInterface* memory_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa32::OpcodeEnum, isa32::RiscV32GEncoding,
-                          isa32::RiscV32GInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa32::OpcodeEnum,
+                                      isa32::RiscV32GEncoding,
+                                      isa32::RiscV32GInstructionSet>>
       decoder_;
   std::unique_ptr<isa32::RiscV32GEncoding> riscv_encoding_;
   std::unique_ptr<RV32IsaFactory> riscv_isa_factory_;
diff --git a/riscv/riscv32g_bitmanip_decoder.cc b/riscv/riscv32g_bitmanip_decoder.cc
index 220a466..f3b3023 100644
--- a/riscv/riscv32g_bitmanip_decoder.cc
+++ b/riscv/riscv32g_bitmanip_decoder.cc
@@ -38,10 +38,11 @@
   riscv_isa_ = std::make_unique<isa32gzb::RiscV32GZBInstructionSet>(
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa32gzb::RiscV32GZBEncoding>(state);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa32gzb::OpcodeEnum, isa32gzb::RiscV32GZBEncoding,
-                          isa32gzb::RiscV32GZBInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa32gzb::OpcodeEnum,
+                                           isa32gzb::RiscV32GZBEncoding,
+                                           isa32gzb::RiscV32GZBInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32GBitmanipDecoder::DecodeInstruction(
diff --git a/riscv/riscv32g_bitmanip_decoder.h b/riscv/riscv32g_bitmanip_decoder.h
index 8a54958..c3e957a 100644
--- a/riscv/riscv32g_bitmanip_decoder.h
+++ b/riscv/riscv32g_bitmanip_decoder.h
@@ -75,9 +75,9 @@
 
  private:
   RiscVState* state_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa32gzb::OpcodeEnum, isa32gzb::RiscV32GZBEncoding,
-                          isa32gzb::RiscV32GZBInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa32gzb::OpcodeEnum,
+                                      isa32gzb::RiscV32GZBEncoding,
+                                      isa32gzb::RiscV32GZBInstructionSet>>
       decoder_;
   util::MemoryInterface* memory_;
   generic::DataBuffer* inst_db_;
diff --git a/riscv/riscv32g_vec_decoder.cc b/riscv/riscv32g_vec_decoder.cc
index f9f2939..76d0694 100644
--- a/riscv/riscv32g_vec_decoder.cc
+++ b/riscv/riscv32g_vec_decoder.cc
@@ -38,10 +38,11 @@
   riscv_isa_ = std::make_unique<isa32v::RiscV32GVInstructionSet>(
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa32v::RiscV32GVecEncoding>(state);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa32v::OpcodeEnum, isa32v::RiscV32GVecEncoding,
-                          isa32v::RiscV32GVInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa32v::OpcodeEnum,
+                                           isa32v::RiscV32GVecEncoding,
+                                           isa32v::RiscV32GVInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32GVecDecoder::DecodeInstruction(uint64_t address) {
diff --git a/riscv/riscv32g_vec_decoder.h b/riscv/riscv32g_vec_decoder.h
index a6c38e9..b549db0 100644
--- a/riscv/riscv32g_vec_decoder.h
+++ b/riscv/riscv32g_vec_decoder.h
@@ -75,9 +75,9 @@
  private:
   RiscVState* state_;
   util::MemoryInterface* memory_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa32v::OpcodeEnum, isa32v::RiscV32GVecEncoding,
-                          isa32v::RiscV32GVInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa32v::OpcodeEnum,
+                                      isa32v::RiscV32GVecEncoding,
+                                      isa32v::RiscV32GVInstructionSet>>
       decoder_;
   std::unique_ptr<isa32v::RiscV32GVecEncoding> riscv_encoding_;
   std::unique_ptr<RV32GVIsaFactory> riscv_isa_factory_;
diff --git a/riscv/riscv32gzb_vec_decoder.cc b/riscv/riscv32gzb_vec_decoder.cc
index c4e2498..e88e01e 100644
--- a/riscv/riscv32gzb_vec_decoder.cc
+++ b/riscv/riscv32gzb_vec_decoder.cc
@@ -42,7 +42,7 @@
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa32gvzb::RiscV32GZBVecEncoding>(state);
   decoder_ = std::make_unique<RiscVGenericDecoder<
-      isa32gvzb::OpcodeEnum, isa32gvzb::RiscV32GZBVecEncoding,
+      RiscVState, isa32gvzb::OpcodeEnum, isa32gvzb::RiscV32GZBVecEncoding,
       isa32gvzb::RiscV32GVZBInstructionSet>>(
       state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
diff --git a/riscv/riscv32gzb_vec_decoder.h b/riscv/riscv32gzb_vec_decoder.h
index 8039cea..c0feb7e 100644
--- a/riscv/riscv32gzb_vec_decoder.h
+++ b/riscv/riscv32gzb_vec_decoder.h
@@ -70,7 +70,7 @@
  private:
   RiscVState* const state_;
   util::MemoryInterface* const memory_;
-  std::unique_ptr<RiscVGenericDecoder<isa32gvzb::OpcodeEnum,
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa32gvzb::OpcodeEnum,
                                       isa32gvzb::RiscV32GZBVecEncoding,
                                       isa32gvzb::RiscV32GVZBInstructionSet>>
       decoder_;
diff --git a/riscv/riscv64_decoder.cc b/riscv/riscv64_decoder.cc
index 3bb579c..845dc54 100644
--- a/riscv/riscv64_decoder.cc
+++ b/riscv/riscv64_decoder.cc
@@ -42,10 +42,11 @@
       state, riscv_isa_factory_.get());
   riscv_encoding_ =
       std::make_unique<isa64::RiscV64GEncoding>(state, use_abi_names);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa64::OpcodeEnum, isa64::RiscV64GEncoding,
-                          isa64::RiscV64GInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa64::OpcodeEnum,
+                                           isa64::RiscV64GEncoding,
+                                           isa64::RiscV64GInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64Decoder::DecodeInstruction(uint64_t address) {
diff --git a/riscv/riscv64_decoder.h b/riscv/riscv64_decoder.h
index a109899..9918b98 100644
--- a/riscv/riscv64_decoder.h
+++ b/riscv/riscv64_decoder.h
@@ -76,9 +76,9 @@
  private:
   RiscVState* state_;
   util::MemoryInterface* memory_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa64::OpcodeEnum, isa64::RiscV64GEncoding,
-                          isa64::RiscV64GInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa64::OpcodeEnum,
+                                      isa64::RiscV64GEncoding,
+                                      isa64::RiscV64GInstructionSet>>
       decoder_;
   std::unique_ptr<isa64::RiscV64GEncoding> riscv_encoding_;
   std::unique_ptr<RV64IsaFactory> riscv_isa_factory_;
diff --git a/riscv/riscv64g_bitmanip_decoder.cc b/riscv/riscv64g_bitmanip_decoder.cc
index c6adf3f..826a39f 100644
--- a/riscv/riscv64g_bitmanip_decoder.cc
+++ b/riscv/riscv64g_bitmanip_decoder.cc
@@ -38,10 +38,11 @@
   riscv_isa_ = std::make_unique<isa64gzb::RiscV64GZBInstructionSet>(
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa64gzb::RiscV64GZBEncoding>(state);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa64gzb::OpcodeEnum, isa64gzb::RiscV64GZBEncoding,
-                          isa64gzb::RiscV64GZBInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa64gzb::OpcodeEnum,
+                                           isa64gzb::RiscV64GZBEncoding,
+                                           isa64gzb::RiscV64GZBInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64GBitmanipDecoder::DecodeInstruction(
diff --git a/riscv/riscv64g_bitmanip_decoder.h b/riscv/riscv64g_bitmanip_decoder.h
index 847243a..4f57d68 100644
--- a/riscv/riscv64g_bitmanip_decoder.h
+++ b/riscv/riscv64g_bitmanip_decoder.h
@@ -73,9 +73,9 @@
  private:
   RiscVState* state_;
   util::MemoryInterface* memory_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa64gzb::OpcodeEnum, isa64gzb::RiscV64GZBEncoding,
-                          isa64gzb::RiscV64GZBInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa64gzb::OpcodeEnum,
+                                      isa64gzb::RiscV64GZBEncoding,
+                                      isa64gzb::RiscV64GZBInstructionSet>>
       decoder_;
   std::unique_ptr<isa64gzb::RiscV64GZBEncoding> riscv_encoding_;
   std::unique_ptr<RV64GZBIsaFactory> riscv_isa_factory_;
diff --git a/riscv/riscv64g_vec_decoder.cc b/riscv/riscv64g_vec_decoder.cc
index 9707e09..007c8b8 100644
--- a/riscv/riscv64g_vec_decoder.cc
+++ b/riscv/riscv64g_vec_decoder.cc
@@ -38,10 +38,11 @@
   riscv_isa_ = std::make_unique<isa64v::RiscV64GVInstructionSet>(
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa64v::RiscV64GVecEncoding>(state);
-  decoder_ = std::make_unique<
-      RiscVGenericDecoder<isa64v::OpcodeEnum, isa64v::RiscV64GVecEncoding,
-                          isa64v::RiscV64GVInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+  decoder_ =
+      std::make_unique<RiscVGenericDecoder<RiscVState, isa64v::OpcodeEnum,
+                                           isa64v::RiscV64GVecEncoding,
+                                           isa64v::RiscV64GVInstructionSet>>(
+          state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64GVecDecoder::DecodeInstruction(uint64_t address) {
diff --git a/riscv/riscv64g_vec_decoder.h b/riscv/riscv64g_vec_decoder.h
index 0b584f1..f28222d 100644
--- a/riscv/riscv64g_vec_decoder.h
+++ b/riscv/riscv64g_vec_decoder.h
@@ -72,9 +72,9 @@
  private:
   RiscVState* const state_;
   util::MemoryInterface* const memory_;
-  std::unique_ptr<
-      RiscVGenericDecoder<isa64v::OpcodeEnum, isa64v::RiscV64GVecEncoding,
-                          isa64v::RiscV64GVInstructionSet>>
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa64v::OpcodeEnum,
+                                      isa64v::RiscV64GVecEncoding,
+                                      isa64v::RiscV64GVInstructionSet>>
       decoder_;
   std::unique_ptr<isa64v::RiscV64GVecEncoding> riscv_encoding_;
   std::unique_ptr<RV64GVIsaFactory> riscv_isa_factory_;
diff --git a/riscv/riscv64gzb_vec_decoder.cc b/riscv/riscv64gzb_vec_decoder.cc
index bc5bbbe..f621fa3 100644
--- a/riscv/riscv64gzb_vec_decoder.cc
+++ b/riscv/riscv64gzb_vec_decoder.cc
@@ -39,7 +39,7 @@
       state, riscv_isa_factory_.get());
   riscv_encoding_ = std::make_unique<isa64gvzb::RiscV64GZBVecEncoding>(state);
   decoder_ = std::make_unique<RiscVGenericDecoder<
-      isa64gvzb::OpcodeEnum, isa64gvzb::RiscV64GZBVecEncoding,
+      RiscVState, isa64gvzb::OpcodeEnum, isa64gvzb::RiscV64GZBVecEncoding,
       isa64gvzb::RiscV64GVZBInstructionSet>>(
       state, memory, riscv_encoding_.get(), riscv_isa_.get());
 }
diff --git a/riscv/riscv64gzb_vec_decoder.h b/riscv/riscv64gzb_vec_decoder.h
index 954e56b..c04df62 100644
--- a/riscv/riscv64gzb_vec_decoder.h
+++ b/riscv/riscv64gzb_vec_decoder.h
@@ -72,7 +72,7 @@
  private:
   RiscVState* const state_;
   util::MemoryInterface* const memory_;
-  std::unique_ptr<RiscVGenericDecoder<isa64gvzb::OpcodeEnum,
+  std::unique_ptr<RiscVGenericDecoder<RiscVState, isa64gvzb::OpcodeEnum,
                                       isa64gvzb::RiscV64GZBVecEncoding,
                                       isa64gvzb::RiscV64GVZBInstructionSet>>
       decoder_;
diff --git a/riscv/riscv_generic_decoder.h b/riscv/riscv_generic_decoder.h
index 9e24d9b..a93700d 100644
--- a/riscv/riscv_generic_decoder.h
+++ b/riscv/riscv_generic_decoder.h
@@ -33,10 +33,10 @@
 
 using ::mpact::sim::generic::Instruction;
 
-template <typename OpcodeEnum, typename Encoding, typename Isa>
+template <typename State, typename OpcodeEnum, typename Encoding, typename Isa>
 class RiscVGenericDecoder {
  public:
-  RiscVGenericDecoder(RiscVState* state, util::MemoryInterface* memory,
+  RiscVGenericDecoder(State* state, util::MemoryInterface* memory,
                       Encoding* encoding, Isa* isa)
       : state_(state), memory_(memory), encoding_(encoding), isa_(isa) {
     auto res =
diff --git a/riscv/rv32g_sim.cc b/riscv/rv32g_sim.cc
index e246cc7..a45c698 100644
--- a/riscv/rv32g_sim.cc
+++ b/riscv/rv32g_sim.cc
@@ -53,6 +53,7 @@
 #include "riscv/riscv32_htif_semihost.h"
 #include "riscv/riscv32g_bitmanip_decoder.h"
 #include "riscv/riscv_arm_semihost.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_fp_state.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_register_aliases.h"
@@ -156,6 +157,9 @@
 ABSL_FLAG(std::string, icache, "", "Instruction cache configuration");
 ABSL_FLAG(std::string, dcache, "", "Data cache configuration");
 
+// Flag to set the default value for the misa CSR.
+ABSL_FLAG(std::optional<uint64_t>, misa, std::nullopt, "misa value");
+
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
@@ -295,6 +299,16 @@
         reg_name, ::mpact::sim::riscv::kFRegisterAliases[i]);
   }
 
+  if (absl::GetFlag(FLAGS_misa).has_value()) {
+    auto misa_res = rv_state.csr_set()->GetCsr(
+        static_cast<uint32_t>(::mpact::sim::riscv::RiscVCsrEnum::kMIsa));
+    if (!misa_res.ok()) {
+      LOG(FATAL) << "Failed to get misa CSR: " << misa_res.status();
+    }
+    auto misa_csr = misa_res.value();
+    misa_csr->Set(absl::GetFlag(FLAGS_misa).value());
+  }
+
   RiscVTop riscv_top("RiscV32Sim", &rv_state, rv_decoder);
 
   if (!absl::GetFlag(FLAGS_icache).empty()) {
diff --git a/riscv/rv32gv_sim.cc b/riscv/rv32gv_sim.cc
index c7cd8a9..36d52fb 100644
--- a/riscv/rv32gv_sim.cc
+++ b/riscv/rv32gv_sim.cc
@@ -53,6 +53,7 @@
 #include "riscv/riscv32g_vec_decoder.h"
 #include "riscv/riscv32gzb_vec_decoder.h"
 #include "riscv/riscv_arm_semihost.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_fp_state.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_register_aliases.h"
@@ -157,6 +158,9 @@
 ABSL_FLAG(std::string, icache, "", "Instruction cache configuration");
 ABSL_FLAG(std::string, dcache, "", "Data cache configuration");
 
+// Flag to set the default value for the misa CSR.
+ABSL_FLAG(std::optional<uint64_t>, misa, std::nullopt, "misa value");
+
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
@@ -296,6 +300,16 @@
         reg_name, ::mpact::sim::riscv::kFRegisterAliases[i]);
   }
 
+  if (absl::GetFlag(FLAGS_misa).has_value()) {
+    auto misa_res = rv_state.csr_set()->GetCsr(
+        static_cast<uint32_t>(::mpact::sim::riscv::RiscVCsrEnum::kMIsa));
+    if (!misa_res.ok()) {
+      LOG(FATAL) << "Failed to get misa CSR: " << misa_res.status();
+    }
+    auto misa_csr = misa_res.value();
+    misa_csr->Set(absl::GetFlag(FLAGS_misa).value());
+  }
+
   RiscVTop riscv_top("RiscV32GVSim", &rv_state, rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
diff --git a/riscv/rv64g_sim.cc b/riscv/rv64g_sim.cc
index d2ac4c5..fe80fcc 100644
--- a/riscv/rv64g_sim.cc
+++ b/riscv/rv64g_sim.cc
@@ -50,6 +50,7 @@
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv64_decoder.h"
 #include "riscv/riscv_arm_semihost.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_fp_state.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_register_aliases.h"
@@ -146,6 +147,9 @@
 // Quiet mode. Suppress informational and warning messages.
 ABSL_FLAG(bool, quiet, false, "Suppress informational and warning messages");
 
+// Flag to set the default value for the misa CSR.
+ABSL_FLAG(std::optional<uint64_t>, misa, std::nullopt, "misa value");
+
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
@@ -259,6 +263,16 @@
         reg_name, ::mpact::sim::riscv::kFRegisterAliases[i]);
   }
 
+  if (absl::GetFlag(FLAGS_misa).has_value()) {
+    auto misa_res = rv_state.csr_set()->GetCsr(
+        static_cast<uint32_t>(::mpact::sim::riscv::RiscVCsrEnum::kMIsa));
+    if (!misa_res.ok()) {
+      LOG(FATAL) << "Failed to get misa CSR: " << misa_res.status();
+    }
+    auto misa_csr = misa_res.value();
+    misa_csr->Set(absl::GetFlag(FLAGS_misa).value());
+  }
+
   RiscVTop riscv_top("RiscV32Sim", &rv_state, &rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
@@ -439,7 +453,7 @@
   std::fstream proto_file(proto_file_name.c_str(), std::ios_base::out);
   std::string serialized;
   if (!proto_file.good() || !google::protobuf::TextFormat::PrintToString(
-                                *component_proto.get(), &serialized)) {
+                                *component_proto, &serialized)) {
     LOG(ERROR) << "Failed to write proto to file";
   } else {
     proto_file << serialized;
diff --git a/riscv/rv64gv_sim.cc b/riscv/rv64gv_sim.cc
index 5a2cc15..2bac95d 100644
--- a/riscv/rv64gv_sim.cc
+++ b/riscv/rv64gv_sim.cc
@@ -52,6 +52,7 @@
 #include "riscv/riscv64g_vec_decoder.h"
 #include "riscv/riscv64gzb_vec_decoder.h"
 #include "riscv/riscv_arm_semihost.h"
+#include "riscv/riscv_csr.h"
 #include "riscv/riscv_fp_state.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_register_aliases.h"
@@ -151,6 +152,9 @@
 // Quiet mode. Suppress informational and warning messages.
 ABSL_FLAG(bool, quiet, false, "Suppress informational and warning messages");
 
+// Flag to set the default value for the misa CSR.
+ABSL_FLAG(std::optional<uint64_t>, misa, std::nullopt, "misa value");
+
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
@@ -271,6 +275,16 @@
         reg_name, ::mpact::sim::riscv::kFRegisterAliases[i]);
   }
 
+  if (absl::GetFlag(FLAGS_misa).has_value()) {
+    auto misa_res = rv_state.csr_set()->GetCsr(
+        static_cast<uint32_t>(::mpact::sim::riscv::RiscVCsrEnum::kMIsa));
+    if (!misa_res.ok()) {
+      LOG(FATAL) << "Failed to get misa CSR: " << misa_res.status();
+    }
+    auto misa_csr = misa_res.value();
+    misa_csr->Set(absl::GetFlag(FLAGS_misa).value());
+  }
+
   RiscVTop riscv_top("RiscV32Sim", &rv_state, rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {