)]}'
{
  "commit": "610d1a7020b32de5e725762f547bd2a277066aaf",
  "tree": "551947d295ea329ca8c9b4b6b0a6fbfbd805fe9d",
  "parents": [
    "c25b5f9ec9dd4a37f503f97945287e0cb1bda587"
  ],
  "author": {
    "name": "MPACT-Sim team",
    "email": "no-reply@google.com",
    "time": "Tue Sep 08 14:11:33 2026 -0700"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Tue Sep 08 14:13:48 2026 -0700"
  },
  "message": "Fix RISC-V vector mask logical and unary operations to respect tail-agnostic policy limits\n\nThis change fixes a bug introduced in an earlier change where vector mask logical operations (e.g., `vmnand`, `vmand`) and vector unary mask instructions (`vmsbf`, `vmsif`, `vmsof`) were extended to evaluate across the entire physical register block (`physical_bits`) rather than safely bounding execution at the dynamic vector length (`vlen`).\n\nAccording to Section 3.4.3 of the RISC-V V-Extension specification:\n- \"Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta.\"\n- \"When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s.\"\n\nBy running the active bitwise logical lambdas (such as `~` for NAND/NOR) over the tail zeroes, the ISS unconditionally modified tail elements. Worse, for operations lacking a bitwise NOT (such as `vmand`), this approach overwrote the tail elements with `0`s, which is an explicit violation of the specification (must be undisturbed or overwritten with `1`s).\n\nThis commit reverts the `BitwiseMaskBinaryOp` and unary mask instructions to bound processing up to `vlen`, aligning the ISS with the valid \"undisturbed\" implementation of the tail-agnostic policy. This resolves mismatches against Spike trace outputs and ensures `vmnand.elf_test` and related architectural tests pass successfully.\n\nPiperOrigin-RevId: 978109338\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "riscv/riscv_vector_opm_instructions.cc",
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      "new_mode": 33188,
      "new_path": "riscv/riscv_vector_opm_instructions.cc"
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      "new_path": "riscv/riscv_vector_unary_instructions.cc"
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      "type": "modify",
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}