tree 551947d295ea329ca8c9b4b6b0a6fbfbd805fe9d
parent c25b5f9ec9dd4a37f503f97945287e0cb1bda587
author MPACT-Sim team <no-reply@google.com> 1788901893 -0700
committer Copybara-Service <copybara-worker@google.com> 1788902028 -0700

Fix RISC-V vector mask logical and unary operations to respect tail-agnostic policy limits

This change fixes a bug introduced in an earlier change where vector mask logical operations (e.g., `vmnand`, `vmand`) and vector unary mask instructions (`vmsbf`, `vmsif`, `vmsof`) were extended to evaluate across the entire physical register block (`physical_bits`) rather than safely bounding execution at the dynamic vector length (`vlen`).

According to Section 3.4.3 of the RISC-V V-Extension specification:
- "Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of vta."
- "When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s."

By running the active bitwise logical lambdas (such as `~` for NAND/NOR) over the tail zeroes, the ISS unconditionally modified tail elements. Worse, for operations lacking a bitwise NOT (such as `vmand`), this approach overwrote the tail elements with `0`s, which is an explicit violation of the specification (must be undisturbed or overwritten with `1`s).

This commit reverts the `BitwiseMaskBinaryOp` and unary mask instructions to bound processing up to `vlen`, aligning the ISS with the valid "undisturbed" implementation of the tail-agnostic policy. This resolves mismatches against Spike trace outputs and ensures `vmnand.elf_test` and related architectural tests pass successfully.

PiperOrigin-RevId: 978109338