diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt
index 9e8c4e6..5cb31e5 100644
--- a/riscv/riscv32g.bin_fmt
+++ b/riscv/riscv32g.bin_fmt
@@ -23,8 +23,8 @@
   RiscVCInst16;
 };
 
-#include "riscv/riscv_format32.bin_fmt"
-#include "riscv/riscv_format16.bin_fmt"
+#include "riscv_format32.bin_fmt"
+#include "riscv_format16.bin_fmt"
 
 instruction group RiscVGInst32[32] : Inst32Format {
   lui    : UType  : opcode == 0b011'0111;
diff --git a/riscv/riscv32gzb.bin_fmt b/riscv/riscv32gzb.bin_fmt
index e42a60d..3619f96 100644
--- a/riscv/riscv32gzb.bin_fmt
+++ b/riscv/riscv32gzb.bin_fmt
@@ -24,5 +24,5 @@
   RiscV32GZBInst16 = {RiscVCInst16};
 }
 
-#include "riscv/riscv32g.bin_fmt"
-#include "riscv/riscv32zb.bin_fmt"
+#include "riscv32g.bin_fmt"
+#include "riscv32zb.bin_fmt"
diff --git a/riscv/riscv32gzb.isa b/riscv/riscv32gzb.isa
index 6add27d..5e0c778 100644
--- a/riscv/riscv32gzb.isa
+++ b/riscv/riscv32gzb.isa
@@ -19,8 +19,8 @@
   }
 }
 
-#include "riscv/riscv32g.isa"
-#include "riscv/riscv32zb.isa"
+#include "riscv32g.isa"
+#include "riscv32zb.isa"
 
 slot riscv32gzb : riscv32g, riscv32_zba, riscv32_zbb, riscv32_zbb_imm,
                   riscv32_zbc, riscv32_zbs, riscv32_zbs_imm {
diff --git a/riscv/riscv32v.bin_fmt b/riscv/riscv32v.bin_fmt
index f5eb8f8..7869752 100644
--- a/riscv/riscv32v.bin_fmt
+++ b/riscv/riscv32v.bin_fmt
@@ -38,6 +38,6 @@
   RiscVCInst16;
 }
 
-#include "riscv/riscv32zb.bin_fmt"
-#include "riscv/riscv32g.bin_fmt"
-#include "riscv/riscv_vector.bin_fmt"
+#include "riscv32zb.bin_fmt"
+#include "riscv32g.bin_fmt"
+#include "riscv_vector.bin_fmt"
diff --git a/riscv/riscv32v.isa b/riscv/riscv32v.isa
index 60ab378..1dd9aa2 100644
--- a/riscv/riscv32v.isa
+++ b/riscv/riscv32v.isa
@@ -29,8 +29,8 @@
   slots { riscv32gvzb; }
 }
 
-#include "riscv/riscv32gzb.isa"
-#include "riscv/riscv_vector.isa"
+#include "riscv32gzb.isa"
+#include "riscv_vector.isa"
 
 slot riscv32gv : riscv32g, riscv_vector {
   default size = 4;
diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt
index 69e3062..f749576 100644
--- a/riscv/riscv64g.bin_fmt
+++ b/riscv/riscv64g.bin_fmt
@@ -23,8 +23,8 @@
   RiscVCInst16;
 };
 
-#include "riscv/riscv_format32.bin_fmt"
-#include "riscv/riscv_format16.bin_fmt"
+#include "riscv_format32.bin_fmt"
+#include "riscv_format16.bin_fmt"
 
 instruction group RiscVGInst32[32] : Inst32Format {
   lui    : UType  : opcode == 0b011'0111;
diff --git a/riscv/riscv64gzb.bin_fmt b/riscv/riscv64gzb.bin_fmt
index 0744bd4..907d5ce 100644
--- a/riscv/riscv64gzb.bin_fmt
+++ b/riscv/riscv64gzb.bin_fmt
@@ -25,6 +25,6 @@
   RiscV64GZBInst16 = {RiscVCInst16};
 }
 
-#include "riscv/riscv64g.bin_fmt"
-#include "riscv/riscv64zb.bin_fmt"
-#include "riscv/riscv32zb.bin_fmt"
+#include "riscv64g.bin_fmt"
+#include "riscv64zb.bin_fmt"
+#include "riscv32zb.bin_fmt"
diff --git a/riscv/riscv64gzb.isa b/riscv/riscv64gzb.isa
index c3a53f0..e222ac2 100644
--- a/riscv/riscv64gzb.isa
+++ b/riscv/riscv64gzb.isa
@@ -19,8 +19,8 @@
   }
 }
 
-#include "riscv/riscv64g.isa"
-#include "riscv/riscv64zb.isa"
+#include "riscv64g.isa"
+#include "riscv64zb.isa"
 
 slot riscv64gzb : riscv64g, riscv64_zba , riscv64_zbb, riscv64_zbb_imm,
                   riscv64_zbc, riscv64_zbs, riscv64_zbs_imm {
diff --git a/riscv/riscv64v.bin_fmt b/riscv/riscv64v.bin_fmt
index 9b4df0d..849be79 100644
--- a/riscv/riscv64v.bin_fmt
+++ b/riscv/riscv64v.bin_fmt
@@ -39,7 +39,7 @@
   RiscVCInst16;
 }
 
-#include "riscv/riscv32zb.bin_fmt"
-#include "riscv/riscv64g.bin_fmt"
-#include "riscv/riscv64zb.bin_fmt"
-#include "riscv/riscv_vector.bin_fmt"
+#include "riscv32zb.bin_fmt"
+#include "riscv64g.bin_fmt"
+#include "riscv64zb.bin_fmt"
+#include "riscv_vector.bin_fmt"
diff --git a/riscv/riscv64v.isa b/riscv/riscv64v.isa
index 5ed1809..a0cffe2 100644
--- a/riscv/riscv64v.isa
+++ b/riscv/riscv64v.isa
@@ -29,8 +29,8 @@
   slots { riscv64gvzb; }
 }
 
-#include "riscv/riscv64gzb.isa"
-#include "riscv/riscv_vector.isa"
+#include "riscv64gzb.isa"
+#include "riscv_vector.isa"
 
 // This adds vector instructions.
 slot riscv64gv : riscv64g, riscv_vector {
diff --git a/riscv/riscv64zb.isa b/riscv/riscv64zb.isa
index f5562dc..a158bdd 100644
--- a/riscv/riscv64zb.isa
+++ b/riscv/riscv64zb.isa
@@ -19,7 +19,7 @@
   #include "riscv/riscv_bitmanip_instructions.h"
 }
 
-#include "riscv/riscv32zb.isa"
+#include "riscv32zb.isa"
 
 disasm widths = {-18};
 
diff --git a/riscv/riscv_vector.bin_fmt b/riscv/riscv_vector.bin_fmt
index 1c76737..4d930cb 100644
--- a/riscv/riscv_vector.bin_fmt
+++ b/riscv/riscv_vector.bin_fmt
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "riscv/riscv_format32.bin_fmt"
+#include "riscv_format32.bin_fmt"
 
 // RiscV vector instruction encodings.
 instruction group RiscVVInst32[32] : Inst32Format {
diff --git a/riscv/riscv_zc.bin_fmt b/riscv/riscv_zc.bin_fmt
index 1eb8f5e..8e9262a 100644
--- a/riscv/riscv_zc.bin_fmt
+++ b/riscv/riscv_zc.bin_fmt
@@ -15,7 +15,7 @@
 // This file refactors the original "C" extension into the new set of Zc*
 // extensions. These should be preferred for new simulator targets.
 
-#include "riscv/riscv_format16.bin_fmt"
+#include "riscv_format16.bin_fmt"
 
 // Compact instruction formats.
 
diff --git a/riscv/riscv_zfh32.bin_fmt b/riscv/riscv_zfh32.bin_fmt
index 0bb8708..cde4d13 100644
--- a/riscv/riscv_zfh32.bin_fmt
+++ b/riscv/riscv_zfh32.bin_fmt
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "riscv/riscv32g.bin_fmt"
+#include "riscv32g.bin_fmt"
 
 decoder ZFH {
   namespace mpact::sim::riscv::zfh32;
diff --git a/riscv/riscv_zfh64.bin_fmt b/riscv/riscv_zfh64.bin_fmt
index ede34bf..8afbc6b 100644
--- a/riscv/riscv_zfh64.bin_fmt
+++ b/riscv/riscv_zfh64.bin_fmt
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "riscv/riscv32g.bin_fmt"
+#include "riscv32g.bin_fmt"
 
 decoder ZFH {
   namespace mpact::sim::riscv::zfh64;
diff --git a/riscv/riscv_zicbop.bin_fmt b/riscv/riscv_zicbop.bin_fmt
index f665825..d6fbbb1 100644
--- a/riscv/riscv_zicbop.bin_fmt
+++ b/riscv/riscv_zicbop.bin_fmt
@@ -15,7 +15,7 @@
 // This file defines the encoding for the cache prefetch instructions in the
 // Zicbop extension.
 
-#include "riscv/riscv_format32.bin_fmt"
+#include "riscv_format32.bin_fmt"
 
 instruction group RiscVZicbop[32] : Inst32Format {
   prefetch_i : ZICBOP : func5 == 0b00000, func3 == 0b110, imm5 == 0b00000, op == 0b001'0011;
diff --git a/riscv/riscv_zimop.bin_fmt b/riscv/riscv_zimop.bin_fmt
index 9ed0c8a..c4cbf3f 100644
--- a/riscv/riscv_zimop.bin_fmt
+++ b/riscv/riscv_zimop.bin_fmt
@@ -14,8 +14,8 @@
 
 // This file contains the encoding for the Zimop and Zcmop instructions.
 
-#include "riscv/riscv_format32.bin_fmt"
-#include "riscv/riscv_format16.bin_fmt"
+#include "riscv_format32.bin_fmt"
+#include "riscv_format16.bin_fmt"
 
 instruction group RiscVZimop[32] : Inst32Format {
   mop_r_0: MopRType : mop_no == 0, func1 == 0b1, func2 == 0b00, func4 == 0b0111, func3 == 0b100, opcode == 0b111'0011;
diff --git a/riscv/riscv_zvbb.bin_fmt b/riscv/riscv_zvbb.bin_fmt
index a9fb0f7..dccc772 100644
--- a/riscv/riscv_zvbb.bin_fmt
+++ b/riscv/riscv_zvbb.bin_fmt
@@ -12,8 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "riscv/riscv32g.bin_fmt"
-#include "riscv/riscv_vector.bin_fmt"
+#include "riscv32g.bin_fmt"
+#include "riscv_vector.bin_fmt"
 
 decoder ZVBB {
   namespace mpact::sim::riscv::zvbb;
diff --git a/riscv/riscv_zvbb.isa b/riscv/riscv_zvbb.isa
index f6f5926..263bdcc 100644
--- a/riscv/riscv_zvbb.isa
+++ b/riscv/riscv_zvbb.isa
@@ -25,7 +25,7 @@
 // First disasm field is 18 char wide and left justified.
 disasm widths = {-18};
 
-#include "riscv/riscv_vector.isa"
+#include "riscv_vector.isa"
 
 slot riscv_zvkb {
   includes {
diff --git a/riscv/rvm23.bin_fmt b/riscv/rvm23.bin_fmt
index e8bdf11..b395e68 100644
--- a/riscv/rvm23.bin_fmt
+++ b/riscv/rvm23.bin_fmt
@@ -46,11 +46,11 @@
   };
 }
 
-#include "riscv/riscv32g.bin_fmt"
-#include "riscv/riscv32zb.bin_fmt"
-#include "riscv/riscv_zc.bin_fmt"
-#include "riscv/riscv_zhintpause.bin_fmt"
-#include "riscv/riscv_zicbop.bin_fmt"
-#include "riscv/riscv_zicond.bin_fmt"
-#include "riscv/riscv_zihintntl.bin_fmt"
-#include "riscv/riscv_zimop.bin_fmt"
+#include "riscv32g.bin_fmt"
+#include "riscv32zb.bin_fmt"
+#include "riscv_zc.bin_fmt"
+#include "riscv_zhintpause.bin_fmt"
+#include "riscv_zicbop.bin_fmt"
+#include "riscv_zicond.bin_fmt"
+#include "riscv_zihintntl.bin_fmt"
+#include "riscv_zimop.bin_fmt"
diff --git a/riscv/rvm23.isa b/riscv/rvm23.isa
index d71a93c..b988fad 100644
--- a/riscv/rvm23.isa
+++ b/riscv/rvm23.isa
@@ -19,15 +19,15 @@
   }
 }
 
-#include "riscv/riscv32g.isa"
-#include "riscv/riscv32zb.isa"
-#include "riscv/riscv_vector.isa"
-#include "riscv/riscv_zc.isa"
-#include "riscv/riscv_zicbop.isa"
-#include "riscv/riscv_zicond.isa"
-#include "riscv/riscv_zimop.isa"
-#include "riscv/riscv_zhintpause.isa"
-#include "riscv/riscv_zihintntl.isa"
+#include "riscv32g.isa"
+#include "riscv32zb.isa"
+#include "riscv_vector.isa"
+#include "riscv_zc.isa"
+#include "riscv_zicbop.isa"
+#include "riscv_zicond.isa"
+#include "riscv_zimop.isa"
+#include "riscv_zhintpause.isa"
+#include "riscv_zihintntl.isa"
 
 slot rvm23 :
   riscv32i,