// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

decoder RVM23 {
  namespace mpact::sim::riscv::rvm23;
  opcode_enum = "OpcodeEnum";
  includes {
    #include "riscv/rvm23_decoder.h"
  }

  RVM23Inst32 = {
    // GP instructions.
    RiscVGInst32,
    // Bitmanipulation instructions.
    RiscVZbaInst32,
    RiscVZbbInst32,
    RiscVZbcInst32,
    RiscVZbsInst32,
    // Conditional zero.
    RiscVZicond,
    RiscVZimop,
    RiscVZhintpause,
    RiscVZihintntl,
    // Cache prefetch instructions.
    RiscVZicbop,
  };
  RVM23Inst16 = {
    RiscVZcmop,
    RiscVCZihintntl,
    RiscVCZca,
    RiscVCZcf,
    RiscVCZcb32,
    RiscVCZcmp,
    RiscVCZcmt,
  };
}

#include "riscv32g.bin_fmt"
#include "riscv32zb.bin_fmt"
#include "riscv_zc.bin_fmt"
#include "riscv_zhintpause.bin_fmt"
#include "riscv_zicbop.bin_fmt"
#include "riscv_zicond.bin_fmt"
#include "riscv_zihintntl.bin_fmt"
#include "riscv_zimop.bin_fmt"