diff --git a/riscv/BUILD b/riscv/BUILD
index fe6c8b6..8519c32 100644
--- a/riscv/BUILD
+++ b/riscv/BUILD
@@ -325,6 +325,7 @@
         ":riscv_state",
         "@com_google_absl//absl/log",
         "@com_google_absl//absl/numeric:bits",
+        "@com_google_absl//absl/strings",
         "@com_google_absl//absl/types:span",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
         "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
@@ -1254,6 +1255,7 @@
     ],
     features = ["-use_header_modules"],
     deps = [
+        "@com_google_absl//absl/status",
         "@com_google_absl//absl/status:statusor",
     ],
 )
@@ -1408,6 +1410,8 @@
     ],
     deps = [
         "@com_google_absl//absl/strings",
+        "@com_google_mpact-sim//mpact/sim/generic:core",
+        "@com_google_mpact-sim//mpact/sim/generic:instruction",
         "@com_google_mpact-sim//mpact/sim/util/memory",
     ],
 )
diff --git a/riscv/debug_command_shell.cc b/riscv/debug_command_shell.cc
index 6afea13..c05ce16 100644
--- a/riscv/debug_command_shell.cc
+++ b/riscv/debug_command_shell.cc
@@ -165,19 +165,19 @@
 )raw";
 }
 
-void DebugCommandShell::AddCore(const CoreAccess &core_access) {
+void DebugCommandShell::AddCore(const CoreAccess& core_access) {
   core_access_.push_back(core_access);
   core_action_point_id_.push_back(0);
   core_action_point_info_.emplace_back();
 }
 
-void DebugCommandShell::AddCores(const std::vector<CoreAccess> &core_access) {
-  for (auto &core : core_access) {
+void DebugCommandShell::AddCores(const std::vector<CoreAccess>& core_access) {
+  for (auto& core : core_access) {
     AddCore(core);
   }
 }
 // NOLINTBEGIN(readability/fn_size)
-void DebugCommandShell::Run(std::istream &is, std::ostream &os) {
+void DebugCommandShell::Run(std::istream& is, std::ostream& os) {
   // Assumes the max linesize is 512.
   command_streams_.push_back(&is);
   constexpr int kLineSize = 512;
@@ -219,7 +219,7 @@
       }
     }
     if (pc_result.ok()) {
-      auto *loader = core_access_[current_core_].loader_getter();
+      auto* loader = core_access_[current_core_].loader_getter();
       if (loader != nullptr) {
         auto fcn_result = loader->GetFunctionName(pc_result.value());
         if (fcn_result.ok()) {
@@ -242,7 +242,7 @@
     }
     absl::StrAppend(&prompt, "[", current_core_, "] > ");
     while (!command_streams_.empty()) {
-      auto &current_is = *command_streams_.back();
+      auto& current_is = *command_streams_.back();
       // Ignore comments or empty lines.
       bool is_file = command_streams_.size() > 1;
       // Read a command from the input stream. If it's from a file, then ignore
@@ -286,7 +286,7 @@
 
     // First try any added custom commands.
     bool executed = false;
-    for (auto &fcn : command_functions_) {
+    for (auto& fcn : command_functions_) {
       std::string output;
       executed = fcn(line_view, core_access_[current_core_], output);
       if (executed) {
@@ -442,7 +442,7 @@
         os.flush();
         continue;
       }
-      auto *db = result.value();
+      auto* db = result.value();
       // Check for null data buffer.
       if (db == nullptr) {
         os << "Error: register '" << name << "' has no data buffer\n";
@@ -488,7 +488,7 @@
         os << "Error: " << result.status().message() << std::endl;
         continue;
       }
-      auto *db = result.value();
+      auto* db = result.value();
       // Check for null data buffer.
       if (db == nullptr) {
         os << "Error: register '" << name << "' has no data buffer\n";
@@ -649,7 +649,7 @@
         bool active =
             core_access_[current_core_].debug_interface->HasBreakpoint(address);
         std::string symbol;
-        auto *loader = core_access_[current_core_].loader_getter();
+        auto* loader = core_access_[current_core_].loader_getter();
         if (loader != nullptr) {
           auto res = loader->GetFcnSymbolName(address);
           if (res.ok()) symbol = std::move(res.value());
@@ -665,7 +665,7 @@
 
     // help
     if (RE2::FullMatch(line_view, *help_re_)) {
-      for (auto const &usage : command_usage_) {
+      for (auto const& usage : command_usage_) {
         os << usage << std::endl;
       }
       os << help_message_;
@@ -745,7 +745,7 @@
         continue;
       }
       size_t length = result.value();
-      auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+      auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto cmd_result =
           riscv_interface->SetDataWatchpoint(address, length, access_type);
@@ -784,7 +784,7 @@
       uint64_t address = iter->second.address;
       size_t length = iter->second.length;
       AccessType access_type = iter->second.access_type;
-      auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+      auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto status =
           riscv_interface->SetDataWatchpoint(address, length, access_type);
@@ -813,7 +813,7 @@
       if (!iter->second.active) continue;
       uint64_t address = iter->second.address;
       auto access_type = iter->second.access_type;
-      auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+      auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto status = riscv_interface->ClearDataWatchpoint(address, access_type);
       if (!status.ok()) {
@@ -826,12 +826,12 @@
 
     // watch clear-all
     if (RE2::FullMatch(line_view, *clear_all_watch_re_)) {
-      for (auto &[index, info] : core_access_[current_core_].watchpoint_map) {
+      for (auto& [index, info] : core_access_[current_core_].watchpoint_map) {
         if (!info.active) continue;
 
         uint64_t address = info.address;
         auto access_type = info.access_type;
-        auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+        auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
             core_access_[current_core_].debug_interface);
         auto status =
             riscv_interface->ClearDataWatchpoint(address, access_type);
@@ -866,10 +866,10 @@
         access_type = AccessType::kLoadStore;
       }
       bool done = false;
-      for (auto &[index, info] : core_access_[current_core_].watchpoint_map) {
+      for (auto& [index, info] : core_access_[current_core_].watchpoint_map) {
         if ((info.address == result.value()) &&
             (info.access_type == access_type)) {
-          auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+          auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
               core_access_[current_core_].debug_interface);
           auto cmd_result =
               riscv_interface->ClearDataWatchpoint(result.value(), access_type);
@@ -921,7 +921,7 @@
         continue;
       }
       size_t length = result.value();
-      auto *riscv_interface = reinterpret_cast<RiscVDebugInterface *>(
+      auto* riscv_interface = reinterpret_cast<RiscVDebugInterface*>(
           core_access_[current_core_].debug_interface);
       auto cmd_result =
           riscv_interface->SetDataWatchpoint(address, length, access_type);
@@ -942,10 +942,10 @@
     // watch list
     if (RE2::FullMatch(line_view, *list_watch_re_)) {
       std::string bp_list;
-      for (auto const &[index, info] :
+      for (auto const& [index, info] :
            core_access_[current_core_].watchpoint_map) {
         std::string symbol;
-        auto *loader = core_access_[current_core_].loader_getter();
+        auto* loader = core_access_[current_core_].loader_getter();
         if (loader != nullptr) {
           auto res = loader->GetFcnSymbolName(info.address);
           if (res.ok()) symbol = std::move(res.value());
@@ -1027,7 +1027,7 @@
         os << "Error: " << result.status().message() << "\n";
         continue;
       }
-      auto *db = result.value();
+      auto* db = result.value();
       // Check for null data buffer.
       if (db == nullptr) {
         os << "Error: register '$branch_trace' has no data buffer\n";
@@ -1052,7 +1052,7 @@
 
     if (std::string file_name;
         RE2::FullMatch(line_view, *exec_re_, &file_name)) {
-      auto *ifile = new std::ifstream(file_name);
+      auto* ifile = new std::ifstream(file_name);
       if (!ifile->is_open() || !ifile->good()) {
         os << "Error: unable to open '" << file_name << "'\n";
         os.flush();
@@ -1116,7 +1116,7 @@
 
 // Templated helper function to help format integer values of different widths.
 template <typename T>
-std::string FormatDbValue(generic::DataBuffer *db, const std::string &format,
+std::string FormatDbValue(generic::DataBuffer* db, const std::string& format,
                           int index) {
   std::string output;
   if (index < 0 || index >= db->size<T>()) return "Error: index out of range";
@@ -1145,9 +1145,9 @@
 }
 
 template <typename T>
-absl::Status WriteDbValue(const std::string &str_value,
-                          const std::string &format, int index,
-                          generic::DataBuffer *db) {
+absl::Status WriteDbValue(const std::string& str_value,
+                          const std::string& format, int index,
+                          generic::DataBuffer* db) {
   if (index < 0 || index >= db->size<T>())
     return absl::OutOfRangeError("Error: index out of range");
   if (format[0] == 'd') {
@@ -1182,8 +1182,8 @@
 
 }  // namespace
 
-std::string DebugCommandShell::FormatSingleDbValue(generic::DataBuffer *db,
-                                                   const std::string &format,
+std::string DebugCommandShell::FormatSingleDbValue(generic::DataBuffer* db,
+                                                   const std::string& format,
                                                    int width, int index) const {
   switch (width) {
     case 8:
@@ -1199,8 +1199,8 @@
   }
 }
 
-std::string DebugCommandShell::FormatAllDbValues(generic::DataBuffer *db,
-                                                 const std::string &format,
+std::string DebugCommandShell::FormatAllDbValues(generic::DataBuffer* db,
+                                                 const std::string& format,
                                                  int width) const {
   std::string output;
   std::string sep;
@@ -1237,7 +1237,7 @@
 }
 
 absl::Status DebugCommandShell::WriteSingleValueToDb(
-    const std::string &str_value, generic::DataBuffer *db, std::string format,
+    const std::string& str_value, generic::DataBuffer* db, std::string format,
     int width, int index) const {
   switch (width) {
     case 8:
@@ -1255,8 +1255,8 @@
 }
 
 std::string DebugCommandShell::ReadMemory(int core,
-                                          const std::string &str_value,
-                                          const std::string &format) {
+                                          const std::string& str_value,
+                                          const std::string& format) {
   int size = 0;
   char format_char = 'x';
   int bit_width = 32;
@@ -1310,15 +1310,15 @@
   }
 
   // Get the result and format it.
-  void *void_buffer = mem_buffer_;
+  void* void_buffer = mem_buffer_;
   std::string output;
   if ((format_char == 'f') && (bit_width >= 32)) {
     switch (bit_width) {
       case 32:
-        output = absl::StrCat(*reinterpret_cast<float *>(void_buffer));
+        output = absl::StrCat(*reinterpret_cast<float*>(void_buffer));
         break;
       case 64:
-        output = absl::StrCat(*reinterpret_cast<double *>(void_buffer));
+        output = absl::StrCat(*reinterpret_cast<double*>(void_buffer));
         break;
       default:
         break;
@@ -1326,16 +1326,16 @@
   } else if (format_char == 'd') {
     switch (bit_width) {
       case 8:
-        output = absl::StrCat(*static_cast<int8_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int8_t*>(void_buffer));
         break;
       case 16:
-        output = absl::StrCat(*static_cast<int16_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int16_t*>(void_buffer));
         break;
       case 32:
-        output = absl::StrCat(*static_cast<int32_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int32_t*>(void_buffer));
         break;
       case 64:
-        output = absl::StrCat(*static_cast<int64_t *>(void_buffer));
+        output = absl::StrCat(*static_cast<int64_t*>(void_buffer));
         break;
       default:
         break;
@@ -1345,19 +1345,19 @@
     auto pad = absl::PadSpec::kNoPad;
     switch (bit_width) {
       case 8:
-        val = *static_cast<uint8_t *>(void_buffer);
+        val = *static_cast<uint8_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad2;
         break;
       case 16:
-        val = *static_cast<uint16_t *>(void_buffer);
+        val = *static_cast<uint16_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad4;
         break;
       case 32:
-        val = *static_cast<uint32_t *>(void_buffer);
+        val = *static_cast<uint32_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad8;
         break;
       case 64:
-        val = *static_cast<uint64_t *>(void_buffer);
+        val = *static_cast<uint64_t*>(void_buffer);
         pad = absl::PadSpec::kZeroPad16;
         break;
     }
@@ -1375,9 +1375,9 @@
 }
 
 std::string DebugCommandShell::WriteMemory(int core,
-                                           const std::string &str_value1,
-                                           const std::string &format,
-                                           const std::string &str_value2) {
+                                           const std::string& str_value1,
+                                           const std::string& format,
+                                           const std::string& str_value2) {
   int size = 0;
   char format_char = '\0';
   int radix = 0;
@@ -1446,7 +1446,7 @@
 }
 
 absl::StatusOr<uint64_t> DebugCommandShell::GetValueFromString(
-    int core, const std::string &str_value, int radix) {
+    int core, const std::string& str_value, int radix) {
   size_t index;
   // Attempt to convert to a number.
   auto convert_result = internal::stoull(str_value, &index, radix);
@@ -1459,7 +1459,7 @@
     return convert_result.status();
   }
   // If all else fails, let's see if it's a symbol.
-  auto *loader = core_access_[current_core_].loader_getter();
+  auto* loader = core_access_[current_core_].loader_getter();
   if (loader == nullptr) return absl::NotFoundError("No symbol table");
   auto result = loader->GetSymbol(str_value);
   if (!result.ok()) return result.status();
@@ -1467,7 +1467,7 @@
 }
 
 std::string DebugCommandShell::FormatRegister(
-    int core, const std::string &reg_name) const {
+    int core, const std::string& reg_name) const {
   std::string output;
   auto result =
       core_access_[current_core_].debug_interface->ReadRegister(reg_name);
@@ -1482,7 +1482,7 @@
 
 std::string DebugCommandShell::FormatAllRegisters(int core) const {
   std::string output;
-  for (auto const &reg_name : reg_vector_) {
+  for (auto const& reg_name : reg_vector_) {
     absl::StrAppend(&output, FormatRegister(current_core_, reg_name), "\n");
   }
   return output;
@@ -1491,8 +1491,8 @@
 // Action point methods.
 std::string DebugCommandShell::ListActionPoints() {
   std::string output;
-  auto &action_map = core_action_point_info_[current_core_];
-  for (auto const &[local_id, info] : action_map) {
+  auto& action_map = core_action_point_info_[current_core_];
+  for (auto const& [local_id, info] : action_map) {
     absl::StrAppend(
         &output,
         absl::StrFormat("%02d  [0x%08lx] %8s  %s\n", local_id, info.address,
@@ -1502,24 +1502,24 @@
 }
 
 std::string DebugCommandShell::EnableActionPointN(
-    const std::string &index_str) {
+    const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
+  auto& info = it->second;
   if (info.is_enabled) {
     return absl::StrCat("Action point ", index, " is already enabled");
   }
   info.is_enabled = true;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *riscv_dbg_if = static_cast<RiscVDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* riscv_dbg_if = static_cast<RiscVDebugInterface*>(dbg_if);
   auto status = riscv_dbg_if->EnableAction(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1528,24 +1528,24 @@
 }
 
 std::string DebugCommandShell::DisableActionPointN(
-    const std::string &index_str) {
+    const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
+  auto& info = it->second;
   if (!info.is_enabled) {
     return absl::StrCat("Action point ", index, " is already disabled");
   }
   info.is_enabled = false;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *riscv_dbg_if = static_cast<RiscVDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* riscv_dbg_if = static_cast<RiscVDebugInterface*>(dbg_if);
   auto status = riscv_dbg_if->DisableAction(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1553,20 +1553,20 @@
   return "";
 }
 
-std::string DebugCommandShell::ClearActionPointN(const std::string &index_str) {
+std::string DebugCommandShell::ClearActionPointN(const std::string& index_str) {
   auto res = riscv::internal::stoull(index_str, nullptr, 10);
   if (!res.ok()) {
     return std::string(res.status().message());
   }
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   int index = res.value();
   auto it = action_map.find(index);
   if (it == action_map.end()) {
     return absl::StrCat("Action point ", index, " not found");
   }
-  auto &info = it->second;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *riscv_dbg_if = static_cast<RiscVDebugInterface *>(dbg_if);
+  auto& info = it->second;
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* riscv_dbg_if = static_cast<RiscVDebugInterface*>(dbg_if);
   auto status = riscv_dbg_if->ClearActionPoint(info.address, info.id);
   if (!status.ok()) {
     return absl::StrCat("Error: ", status.message());
@@ -1577,9 +1577,9 @@
 
 std::string DebugCommandShell::ClearAllActionPoints() {
   std::string output;
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *riscv_dbg_if = static_cast<RiscVDebugInterface *>(dbg_if);
-  for (auto &[local_id, info] : core_action_point_info_[current_core_]) {
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* riscv_dbg_if = static_cast<RiscVDebugInterface*>(dbg_if);
+  for (auto& [local_id, info] : core_action_point_info_[current_core_]) {
     auto status = riscv_dbg_if->ClearActionPoint(info.address, info.id);
     if (!status.ok()) {
       absl::StrAppend(&output, "Error: ", status.message());
@@ -1591,15 +1591,15 @@
 absl::Status DebugCommandShell::SetActionPoint(
     uint64_t address, std::string name,
     absl::AnyInvocable<void(uint64_t, int)> function) {
-  auto *dbg_if = core_access_[current_core_].debug_interface;
-  auto *riscv_dbg_if = static_cast<RiscVDebugInterface *>(dbg_if);
+  auto* dbg_if = core_access_[current_core_].debug_interface;
+  auto* riscv_dbg_if = static_cast<RiscVDebugInterface*>(dbg_if);
   auto result = riscv_dbg_if->SetActionPoint(address, std::move(function));
   if (!result.ok()) {
     return absl::InternalError(result.status().message());
   }
   int id = result.value();
   int local_id = core_action_point_id_[current_core_]++;
-  auto &action_map = core_action_point_info_[current_core_];
+  auto& action_map = core_action_point_info_[current_core_];
   action_map.emplace(local_id, ActionPointInfo{address, id, name, true});
   return absl::OkStatus();
 }
diff --git a/riscv/debug_command_shell.h b/riscv/debug_command_shell.h
index 5e3b445..eba421d 100644
--- a/riscv/debug_command_shell.h
+++ b/riscv/debug_command_shell.h
@@ -49,12 +49,12 @@
   DebugCommandShell();
 
   // Add core access to the system. All cores must be added before calling Run.
-  void AddCore(const CoreAccess &core_access) override;
-  void AddCores(const std::vector<CoreAccess> &core_access) override;
+  void AddCore(const CoreAccess& core_access) override;
+  void AddCores(const std::vector<CoreAccess>& core_access) override;
 
   // The run method is the command interpreter. It parses the command strings,
   // executes the corresponding commands, displays results and error messages.
-  void Run(std::istream &is, std::ostream &os) override;
+  void Run(std::istream& is, std::ostream& os) override;
 
   // This adds a custom command to the command interpreter. Usage will be added
   // to the standard command usage. The callable will be called before the
@@ -78,39 +78,39 @@
   };
 
   // Helper method for formatting single data buffer value.
-  std::string FormatSingleDbValue(generic::DataBuffer *db,
-                                  const std::string &format, int width,
+  std::string FormatSingleDbValue(generic::DataBuffer* db,
+                                  const std::string& format, int width,
                                   int index) const;
   // Helper method for formatting multiple data buffer values.
-  std::string FormatAllDbValues(generic::DataBuffer *db,
-                                const std::string &format, int width) const;
+  std::string FormatAllDbValues(generic::DataBuffer* db,
+                                const std::string& format, int width) const;
   // Helper method for writing single data buffer value.
-  absl::Status WriteSingleValueToDb(const std::string &str_value,
-                                    generic::DataBuffer *db, std::string format,
+  absl::Status WriteSingleValueToDb(const std::string& str_value,
+                                    generic::DataBuffer* db, std::string format,
                                     int width, int index) const;
 
   // Helper method for processing read memory command.
-  std::string ReadMemory(int core, const std::string &str_value,
-                         const std::string &format);
+  std::string ReadMemory(int core, const std::string& str_value,
+                         const std::string& format);
   // Helper method for processing write memory command.
-  std::string WriteMemory(int core, const std::string &str_value1,
-                          const std::string &format,
-                          const std::string &str_value2);
+  std::string WriteMemory(int core, const std::string& str_value1,
+                          const std::string& format,
+                          const std::string& str_value2);
   // Helper method used to parse a numeric string or use the string as a
   // symbol name for lookup in the loader.
   absl::StatusOr<uint64_t> GetValueFromString(int core,
-                                              const std::string &str_value,
+                                              const std::string& str_value,
                                               int radix);
   // Reads and formats a register.
-  std::string FormatRegister(int core, const std::string &reg_name) const;
+  std::string FormatRegister(int core, const std::string& reg_name) const;
   // Reads and formats $all registers - stored in reg_vec_.
   std::string FormatAllRegisters(int core) const;
 
   // Action point handling.
   std::string ListActionPoints();
-  std::string EnableActionPointN(const std::string &index_str);
-  std::string DisableActionPointN(const std::string &index_str);
-  std::string ClearActionPointN(const std::string &index_str);
+  std::string EnableActionPointN(const std::string& index_str);
+  std::string DisableActionPointN(const std::string& index_str);
+  std::string ClearActionPointN(const std::string& index_str);
   std::string ClearAllActionPoints();
 
   std::vector<CoreAccess> core_access_;
@@ -173,7 +173,7 @@
   std::vector<std::string> command_usage_;
   std::vector<std::string> reg_vector_;
   absl::flat_hash_set<std::string> exec_file_names_;
-  std::deque<std::istream *> command_streams_;
+  std::deque<std::istream*> command_streams_;
   std::deque<std::string> previous_commands_;
   std::vector<absl::btree_map<int, ActionPointInfo>> core_action_point_info_;
   std::vector<int> core_action_point_id_;
diff --git a/riscv/riscv32_decoder.cc b/riscv/riscv32_decoder.cc
index 6766049..c63a7c3 100644
--- a/riscv/riscv32_decoder.cc
+++ b/riscv/riscv32_decoder.cc
@@ -32,7 +32,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV32Decoder::RiscV32Decoder(RiscVState *state, util::MemoryInterface *memory)
+RiscV32Decoder::RiscV32Decoder(RiscVState* state, util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Get a handle to the internal error in the program error controller.
   decode_error_ = state->program_error_controller()->GetProgramError(
@@ -57,16 +57,16 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *RiscV32Decoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* RiscV32Decoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAddressMisaligned,
                    inst->address() ^ 0x1, inst);
@@ -77,12 +77,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAccessFault, inst->address(),
                    nullptr);
@@ -97,7 +97,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_);
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_);
   return instruction;
 }
 
diff --git a/riscv/riscv32_decoder.h b/riscv/riscv32_decoder.h
index c19469a..e557ef8 100644
--- a/riscv/riscv32_decoder.h
+++ b/riscv/riscv32_decoder.h
@@ -41,7 +41,7 @@
 class RV32IsaFactory : public isa32::RiscV32GInstructionSetFactory {
  public:
   std::unique_ptr<isa32::Riscv32gSlot> CreateRiscv32gSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32::Riscv32gSlot>(state);
   }
 };
@@ -53,32 +53,32 @@
   using SlotEnum = isa32::SlotEnum;
   using OpcodeEnum = isa32::OpcodeEnum;
 
-  RiscV32Decoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV32Decoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV32Decoder() = delete;
   ~RiscV32Decoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32::RiscV32GEncoding *riscv_encoding() const { return riscv_encoding_; }
+  isa32::RiscV32GEncoding* riscv_encoding() const { return riscv_encoding_; }
 
  private:
-  RiscVState *state_;
-  util::MemoryInterface *memory_;
+  RiscVState* state_;
+  util::MemoryInterface* memory_;
   std::unique_ptr<generic::ProgramError> decode_error_;
-  generic::DataBuffer *inst_db_;
-  isa32::RiscV32GEncoding *riscv_encoding_;
-  RV32IsaFactory *riscv_isa_factory_;
-  isa32::RiscV32GInstructionSet *riscv_isa_;
+  generic::DataBuffer* inst_db_;
+  isa32::RiscV32GEncoding* riscv_encoding_;
+  RV32IsaFactory* riscv_isa_factory_;
+  isa32::RiscV32GInstructionSet* riscv_isa_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv32_htif_semihost.cc b/riscv/riscv32_htif_semihost.cc
index 318d2a2..511e9fc 100644
--- a/riscv/riscv32_htif_semihost.cc
+++ b/riscv/riscv32_htif_semihost.cc
@@ -36,13 +36,13 @@
 using AddressRange = mpact::sim::util::MemoryWatcher::AddressRange;
 
 RiscV32HtifSemiHost::RiscV32HtifSemiHost(
-    util::MemoryWatcher *watcher, util::MemoryInterface *memory,
-    const SemiHostAddresses &magic_addresses)
+    util::MemoryWatcher* watcher, util::MemoryInterface* memory,
+    const SemiHostAddresses& magic_addresses)
     : RiscV32HtifSemiHost(watcher, memory, magic_addresses, nullptr, nullptr) {}
 
 RiscV32HtifSemiHost::RiscV32HtifSemiHost(
-    util::MemoryWatcher *watcher, util::MemoryInterface *memory,
-    const SemiHostAddresses &magic_addresses, HaltCallback halt_callback,
+    util::MemoryWatcher* watcher, util::MemoryInterface* memory,
+    const SemiHostAddresses& magic_addresses, HaltCallback halt_callback,
     ErrorCallback error_callback)
     : halt_callback_(std::move(halt_callback)),
       error_callback_(std::move(error_callback)),
@@ -66,7 +66,7 @@
 }
 
 void RiscV32HtifSemiHost::SetMagicAddresses(
-    const SemiHostAddresses &magic_addresses) {
+    const SemiHostAddresses& magic_addresses) {
   // Clear any previous store watchpoint. Ignore any error.
   (void)watcher_->ClearStoreWatchCallback(magic_addresses_.tohost_ready);
   magic_addresses_ = magic_addresses;
@@ -91,7 +91,7 @@
 
   // Read the value of the ready_db, if not 1, then the tohost location
   // does not contain data, and there's nothing to do.
-  auto *ready_db = db_factory_.Allocate<uint8_t>(1);
+  auto* ready_db = db_factory_.Allocate<uint8_t>(1);
   memory_->Load(magic_addresses_.tohost_ready, ready_db, nullptr, nullptr);
   if (ready_db->Get<uint8_t>(0) != 1) {
     ready_db->DecRef();
@@ -99,7 +99,7 @@
   }
 
   // Get the payload double word. Extract the command.
-  auto *payload_db = db_factory_.Allocate<uint64_t>(1);
+  auto* payload_db = db_factory_.Allocate<uint64_t>(1);
   memory_->Load(magic_addresses_.tohost, payload_db, nullptr, nullptr);
   uint64_t payload = payload_db->Get<uint64_t>(0);
   uint8_t device = payload >> 56;
@@ -117,7 +117,7 @@
   }
   // The payload contains a pointer to an 8 double word parameter block. Load
   // that block.
-  auto *parameter_db = db_factory_.Allocate<uint64_t>(8);
+  auto* parameter_db = db_factory_.Allocate<uint64_t>(8);
   memory_->Load(payload, parameter_db, nullptr, nullptr);
   auto parameter_span = parameter_db->Get<uint64_t>();
   int64_t return_value = 0;
@@ -133,10 +133,10 @@
       } else {
         dirfd = iter->second;
       }
-      auto *db = db_factory_.Allocate(parameter_span[3]);
+      auto* db = db_factory_.Allocate(parameter_span[3]);
       auto address = parameter_span[2];
       memory_->Load(address, db, nullptr, nullptr);
-      char *name = static_cast<char *>(db->raw_ptr());
+      char* name = static_cast<char*>(db->raw_ptr());
       return_value = openat(dirfd, name, parameter_span[4], parameter_span[5]);
       db->DecRef();
     } break;
@@ -163,10 +163,10 @@
       auto iter = fd_map_.find(parameter_span[1]);
       int fd = iter == fd_map_.end() ? -1 : iter->second;
       size_t len = static_cast<size_t>(parameter_span[3]);
-      auto *data_db = db_factory_.Allocate<uint8_t>(len);
+      auto* data_db = db_factory_.Allocate<uint8_t>(len);
       int res = read(fd, data_db->raw_ptr(), len);
       if (res > 0) {
-        generic::DataBuffer *db = nullptr;
+        generic::DataBuffer* db = nullptr;
         // Need to see if fewer bytes were read than there was space for. If so
         // need to use a different db for the store.
         if (res == len) {
@@ -185,7 +185,7 @@
     {
       auto iter = fd_map_.find(parameter_span[1]);
       int fd = iter == fd_map_.end() ? -1 : iter->second;
-      auto *data_db = db_factory_.Allocate<uint8_t>(parameter_span[3]);
+      auto* data_db = db_factory_.Allocate<uint8_t>(parameter_span[3]);
       memory_->Load(parameter_span[2], data_db, nullptr, nullptr);
       size_t len = static_cast<size_t>(parameter_span[3]);
       return_value = write(fd, data_db->raw_ptr(), len);
@@ -197,10 +197,10 @@
       int fd = iter == fd_map_.end() ? -1 : iter->second;
       size_t len = static_cast<size_t>(parameter_span[3]);
       off_t offset = static_cast<off_t>(parameter_span[4]);
-      auto *data_db = db_factory_.Allocate<uint8_t>(len);
+      auto* data_db = db_factory_.Allocate<uint8_t>(len);
       int res = pread(fd, data_db->raw_ptr(), len, offset);
       if (res > 0) {
-        generic::DataBuffer *db = nullptr;
+        generic::DataBuffer* db = nullptr;
         // Need to see if fewer bytes were read than there was space for. If so
         // need to use a different db for the store.
         if (res == len) {
@@ -219,7 +219,7 @@
     {
       auto iter = fd_map_.find(parameter_span[1]);
       int fd = iter == fd_map_.end() ? -1 : iter->second;
-      auto *data_db = db_factory_.Allocate<uint8_t>(parameter_span[3]);
+      auto* data_db = db_factory_.Allocate<uint8_t>(parameter_span[3]);
       memory_->Load(parameter_span[2], data_db, nullptr, nullptr);
       size_t len = static_cast<size_t>(parameter_span[3]);
       off_t offset = static_cast<off_t>(parameter_span[4]);
diff --git a/riscv/riscv32_htif_semihost.h b/riscv/riscv32_htif_semihost.h
index 910580f..59430a2 100644
--- a/riscv/riscv32_htif_semihost.h
+++ b/riscv/riscv32_htif_semihost.h
@@ -45,19 +45,19 @@
     uint64_t fromhost;
   };
 
-  RiscV32HtifSemiHost(util::MemoryWatcher *watcher,
-                      util::MemoryInterface *memory,
-                      const SemiHostAddresses &magic_addresses);
+  RiscV32HtifSemiHost(util::MemoryWatcher* watcher,
+                      util::MemoryInterface* memory,
+                      const SemiHostAddresses& magic_addresses);
 
-  RiscV32HtifSemiHost(util::MemoryWatcher *watcher,
-                      util::MemoryInterface *memory,
-                      const SemiHostAddresses &magic_addresses,
+  RiscV32HtifSemiHost(util::MemoryWatcher* watcher,
+                      util::MemoryInterface* memory,
+                      const SemiHostAddresses& magic_addresses,
                       HaltCallback halt_callback, ErrorCallback error_callback);
 
   ~RiscV32HtifSemiHost();
 
   // Set magic addresses.
-  void SetMagicAddresses(const SemiHostAddresses &magic_addresses);
+  void SetMagicAddresses(const SemiHostAddresses& magic_addresses);
   // Set the halt callback.
   void SetHaltCallback(HaltCallback halt_callback);
   // Set the error callback.
@@ -71,9 +71,9 @@
   HaltCallback halt_callback_;
   ErrorCallback error_callback_;
   // Memory watcher.
-  util::MemoryWatcher *watcher_;
+  util::MemoryWatcher* watcher_;
   // Memory interface (bypassing the watchpoints).
-  util::MemoryInterface *memory_;
+  util::MemoryInterface* memory_;
   SemiHostAddresses magic_addresses_;
   // File descriptor map.
   absl::flat_hash_map<int, int> fd_map_;
diff --git a/riscv/riscv32_renode.cc b/riscv/riscv32_renode.cc
index 421dd3a..19f8b1e 100644
--- a/riscv/riscv32_renode.cc
+++ b/riscv/riscv32_renode.cc
@@ -7,10 +7,10 @@
 #include "riscv/riscv_renode.h"
 #include "riscv/riscv_state.h"
 
-::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
+::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
     std::string name, std::string cpu_type,
-    ::mpact::sim::util::MemoryInterface *renode_sysbus) {
-  auto *top = new ::mpact::sim::riscv::RiscVRenode(
+    ::mpact::sim::util::MemoryInterface* renode_sysbus) {
+  auto* top = new ::mpact::sim::riscv::RiscVRenode(
       name, renode_sysbus, ::mpact::sim::riscv::RiscVXlen ::RV32);
   return top;
 }
diff --git a/riscv/riscv32_renode.h b/riscv/riscv32_renode.h
index b068ae7..9bdc731 100644
--- a/riscv/riscv32_renode.h
+++ b/riscv/riscv32_renode.h
@@ -9,8 +9,8 @@
 // This file defines the factory method for creating a RiscV 32 simulator for
 // use with ReNode.
 
-extern ::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
+extern ::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
     std::string name, std::string cpu_type,
-    ::mpact::sim::util::MemoryInterface *renode_sysbus);
+    ::mpact::sim::util::MemoryInterface* renode_sysbus);
 
 #endif  // THIRD_PARTY_MPACT_RISCV_RISCV32_RENODE_H_
diff --git a/riscv/riscv32g_bitmanip_decoder.cc b/riscv/riscv32g_bitmanip_decoder.cc
index 2644ad5..3c2de3f 100644
--- a/riscv/riscv32g_bitmanip_decoder.cc
+++ b/riscv/riscv32g_bitmanip_decoder.cc
@@ -32,8 +32,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV32GBitmanipDecoder::RiscV32GBitmanipDecoder(RiscVState *state,
-                                                 util::MemoryInterface *memory)
+RiscV32GBitmanipDecoder::RiscV32GBitmanipDecoder(RiscVState* state,
+                                                 util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Need a data buffer to load instructions from memory. Allocate a single
   // buffer that can be reused for each instruction word.
@@ -53,17 +53,17 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *RiscV32GBitmanipDecoder::DecodeInstruction(
+generic::Instruction* RiscV32GBitmanipDecoder::DecodeInstruction(
     uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32gzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAddressMisaligned,
                    inst->address() ^ 0x1, inst);
@@ -74,12 +74,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32gzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAccessFault, inst->address(),
                    nullptr);
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_);
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_);
   return instruction;
 }
 
diff --git a/riscv/riscv32g_bitmanip_decoder.h b/riscv/riscv32g_bitmanip_decoder.h
index 1205872..7c66ab1 100644
--- a/riscv/riscv32g_bitmanip_decoder.h
+++ b/riscv/riscv32g_bitmanip_decoder.h
@@ -41,7 +41,7 @@
 class RV32GZBIsaFactory : public isa32gzb::RiscV32GZBInstructionSetFactory {
  public:
   std::unique_ptr<isa32gzb::Riscv32gzbSlot> CreateRiscv32gzbSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32gzb::Riscv32gzbSlot>(state);
   }
 };
@@ -53,33 +53,33 @@
   using SlotEnum = isa32gzb::SlotEnum;
   using OpcodeEnum = isa32gzb::OpcodeEnum;
 
-  RiscV32GBitmanipDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV32GBitmanipDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV32GBitmanipDecoder() = delete;
   ~RiscV32GBitmanipDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32gzb::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32gzb::RiscV32GZBEncoding *riscv_encoding() const {
+  isa32gzb::RiscV32GZBEncoding* riscv_encoding() const {
     return riscv_encoding_;
   }
 
  private:
-  RiscVState *state_;
-  util::MemoryInterface *memory_;
-  generic::DataBuffer *inst_db_;
-  isa32gzb::RiscV32GZBEncoding *riscv_encoding_;
-  RV32GZBIsaFactory *riscv_isa_factory_;
-  isa32gzb::RiscV32GZBInstructionSet *riscv_isa_;
+  RiscVState* state_;
+  util::MemoryInterface* memory_;
+  generic::DataBuffer* inst_db_;
+  isa32gzb::RiscV32GZBEncoding* riscv_encoding_;
+  RV32GZBIsaFactory* riscv_isa_factory_;
+  isa32gzb::RiscV32GZBInstructionSet* riscv_isa_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv32g_encoding.cc b/riscv/riscv32g_encoding.cc
index 34b155f..63a9a55 100644
--- a/riscv/riscv32g_encoding.cc
+++ b/riscv/riscv32g_encoding.cc
@@ -39,51 +39,51 @@
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(RiscVState *state,
+inline DestinationOperandInterface* GetRegisterDestinationOp(RiscVState* state,
                                                              std::string name,
                                                              int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
-RiscV32GEncoding::RiscV32GEncoding(RiscVState *state) : state_(state) {
+RiscV32GEncoding::RiscV32GEncoding(RiscVState* state) : state_(state) {
   InitializeSourceOperandGetters();
   InitializeDestinationOperandGetters();
   InitializeSimpleResourceGetters();
@@ -98,7 +98,7 @@
   // Source operand getters.
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kAAq),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding::inst32_format::ExtractAq(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -106,7 +106,7 @@
                      }));
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kARl),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding::inst32_format::ExtractRl(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -181,7 +181,7 @@
         if (!res.ok()) {
           return new generic::ImmediateOperand<uint32_t>(csr_indx);
         }
-        auto *csr = res.value();
+        auto* csr = res.value();
         return new generic::ImmediateOperand<uint32_t>(csr_indx, csr->name());
       }));
   source_op_getters_.insert(
@@ -311,8 +311,7 @@
             encoding::inst32_format::ExtractPred(inst_word_));
       }));
   source_op_getters_.insert(std::make_pair(
-      static_cast<int>(SourceOpEnum::kRd),
-      [this]() -> SourceOperandInterface * {
+      static_cast<int>(SourceOpEnum::kRd), [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRd(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -320,34 +319,33 @@
             state_, absl::StrCat(RiscVState::kXregPrefix, num),
             xreg_alias_[num]);
       }));
-  source_op_getters_.insert(
-      std::make_pair(static_cast<int>(SourceOpEnum::kRm),
-                     [this]() -> SourceOperandInterface * {
-                       uint32_t rm = (inst_word_ >> 12) & 0x7;
-                       switch (rm) {
-                         case 0:
-                           return new generic::IntLiteralOperand<0>();
-                         case 1:
-                           return new generic::IntLiteralOperand<1>();
-                         case 2:
-                           return new generic::IntLiteralOperand<2>();
-                         case 3:
-                           return new generic::IntLiteralOperand<3>();
-                         case 4:
-                           return new generic::IntLiteralOperand<4>();
-                         case 5:
-                           return new generic::IntLiteralOperand<5>();
-                         case 6:
-                           return new generic::IntLiteralOperand<6>();
-                         case 7:
-                           return new generic::IntLiteralOperand<7>();
-                         default:
-                           return nullptr;
-                       }
-                     }));
+  source_op_getters_.insert(std::make_pair(
+      static_cast<int>(SourceOpEnum::kRm), [this]() -> SourceOperandInterface* {
+        uint32_t rm = (inst_word_ >> 12) & 0x7;
+        switch (rm) {
+          case 0:
+            return new generic::IntLiteralOperand<0>();
+          case 1:
+            return new generic::IntLiteralOperand<1>();
+          case 2:
+            return new generic::IntLiteralOperand<2>();
+          case 3:
+            return new generic::IntLiteralOperand<3>();
+          case 4:
+            return new generic::IntLiteralOperand<4>();
+          case 5:
+            return new generic::IntLiteralOperand<5>();
+          case 6:
+            return new generic::IntLiteralOperand<6>();
+          case 7:
+            return new generic::IntLiteralOperand<7>();
+          default:
+            return nullptr;
+        }
+      }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs1),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRs1(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -357,7 +355,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs2),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRs2(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -444,7 +442,7 @@
       }));
   dest_op_getters_.insert(
       std::make_pair(static_cast<int>(DestOpEnum::kRd),
-                     [this](int latency) -> DestinationOperandInterface * {
+                     [this](int latency) -> DestinationOperandInterface* {
                        int num = encoding::r_type::ExtractRd(inst_word_);
                        if (num == 0) {
                          return GetRegisterDestinationOp<RV32Register>(
@@ -499,7 +497,7 @@
                      [](int begin, int end) { return nullptr; }));
 }
 
-ResourceOperandInterface *RiscV32GEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV32GEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -516,31 +514,31 @@
       static_cast<int>(SimpleResourceEnum::kNone), []() { return nullptr; }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3frd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3frs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -548,7 +546,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -556,7 +554,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -564,19 +562,19 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCdrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCfrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -584,7 +582,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -592,65 +590,65 @@
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kCsr),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("csr");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kNextPc),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("next_pc");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -658,7 +656,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -666,7 +664,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -675,23 +673,23 @@
   // X0 is constant 0, so no resource issue.
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX0),
-                     []() -> generic::SimpleResource * { return nullptr; }));
+                     []() -> generic::SimpleResource* { return nullptr; }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX1),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x1");
                      }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX2),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x2");
                      }));
 }
 
-ResourceOperandInterface *RiscV32GEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV32GEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -699,18 +697,18 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
+  auto* op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV32GEncoding::GetDestination(
+DestinationOperandInterface* RiscV32GEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -724,7 +722,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV32GEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV32GEncoding::GetSource(SlotEnum, int,
                                                     OpcodeEnum opcode,
                                                     SourceOpEnum source_op,
                                                     int source_no) {
diff --git a/riscv/riscv32g_encoding.h b/riscv/riscv32g_encoding.h
index 920e84e..0b2e05e 100644
--- a/riscv/riscv32g_encoding.h
+++ b/riscv/riscv32g_encoding.h
@@ -52,15 +52,15 @@
   static constexpr int kParseGroup16Size = 32;
 
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
   using SimpleResourceGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource*()>>;
   using ComplexResourceGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<ResourceOperandInterface *(int, int)>>;
+      int, absl::AnyInvocable<ResourceOperandInterface*(int, int)>>;
 
-  explicit RiscV32GEncoding(RiscVState *state);
+  explicit RiscV32GEncoding(RiscVState* state);
   ~RiscV32GEncoding() override;
 
   // Parses an instruction and determines the opcode.
@@ -73,7 +73,7 @@
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
@@ -85,22 +85,22 @@
   // where the resource itself is a register bank, and the argument specifies
   // which register (or more precisely) which encoding "field" specifies the
   // register number.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -111,14 +111,14 @@
   }
 
   // Getter.
-  SimpleResourcePool *resource_pool() const { return resource_pool_; }
+  SimpleResourcePool* resource_pool() const { return resource_pool_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
@@ -141,11 +141,11 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
-  SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  SimpleResourcePool *resource_pool_ = nullptr;
+  SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace isa32
diff --git a/riscv/riscv32g_vec_decoder.cc b/riscv/riscv32g_vec_decoder.cc
index b3824f5..49b0da8 100644
--- a/riscv/riscv32g_vec_decoder.cc
+++ b/riscv/riscv32g_vec_decoder.cc
@@ -23,8 +23,8 @@
 namespace sim {
 namespace riscv {
 
-RiscV32GVecDecoder::RiscV32GVecDecoder(RiscVState *state,
-                                       util::MemoryInterface *memory)
+RiscV32GVecDecoder::RiscV32GVecDecoder(RiscVState* state,
+                                       util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Get a handle to the internal error in the program error controller.
   decode_error_ = state->program_error_controller()->GetProgramError(
@@ -49,15 +49,15 @@
   delete riscv_encoding_;
 }
 
-generic::Instruction *RiscV32GVecDecoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* RiscV32GVecDecoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that generates an internal simulator error when
   // executed.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     std::string error =
         absl::StrCat(absl::Hex(address), ": unaligned instruction address");
-    inst->set_semantic_function([error, this](generic::Instruction *inst) {
+    inst->set_semantic_function([error, this](generic::Instruction* inst) {
       decode_error_->Raise(error);
     });
     inst->set_size(1);
@@ -71,7 +71,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_);
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_);
   return instruction;
 }
 
diff --git a/riscv/riscv32g_vec_decoder.h b/riscv/riscv32g_vec_decoder.h
index d1eae1c..f75ede6 100644
--- a/riscv/riscv32g_vec_decoder.h
+++ b/riscv/riscv32g_vec_decoder.h
@@ -41,7 +41,7 @@
 class RV32GVIsaFactory : public isa32v::RiscV32GVInstructionSetFactory {
  public:
   std::unique_ptr<isa32v::Riscv32gvSlot> CreateRiscv32gvSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32v::Riscv32gvSlot>(state);
   }
 };
@@ -53,35 +53,35 @@
   using SlotEnum = isa32v::SlotEnum;
   using OpcodeEnum = isa32v::OpcodeEnum;
 
-  RiscV32GVecDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV32GVecDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV32GVecDecoder() = delete;
   ~RiscV32GVecDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
 
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32v::kOpcodeNames[index];
   }
 
   // Getter.
-  isa32v::RiscV32GVecEncoding *riscv_encoding() const {
+  isa32v::RiscV32GVecEncoding* riscv_encoding() const {
     return riscv_encoding_;
   }
 
  private:
-  RiscVState *state_;
-  util::MemoryInterface *memory_;
+  RiscVState* state_;
+  util::MemoryInterface* memory_;
   std::unique_ptr<generic::ProgramError> decode_error_;
-  generic::DataBuffer *inst_db_;
-  isa32v::RiscV32GVecEncoding *riscv_encoding_;
-  RV32GVIsaFactory *riscv_isa_factory_;
-  isa32v::RiscV32GVInstructionSet *riscv_isa_;
+  generic::DataBuffer* inst_db_;
+  isa32v::RiscV32GVecEncoding* riscv_encoding_;
+  RV32GVIsaFactory* riscv_isa_factory_;
+  isa32v::RiscV32GVInstructionSet* riscv_isa_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv32g_vec_encoding.cc b/riscv/riscv32g_vec_encoding.cc
index 88ba701..679fa5b 100644
--- a/riscv/riscv32g_vec_encoding.cc
+++ b/riscv/riscv32g_vec_encoding.cc
@@ -39,15 +39,15 @@
 namespace isa32v {
 
 template <typename M, typename E, typename G>
-inline void Insert(M &map, E entry, G getter) {
+inline void Insert(M& map, E entry, G getter) {
   map.insert(std::make_pair(static_cast<int>(entry), getter));
 }
 
 constexpr int kNumRegTable[8] = {8, 1, 2, 1, 4, 1, 2, 1};
 
 template <typename RegType>
-inline void GetVRegGroup(RiscVState *state, int reg_num,
-                         std::vector<generic::RegisterBase *> *vreg_group) {
+inline void GetVRegGroup(RiscVState* state, int reg_num,
+                         std::vector<generic::RegisterBase*>* vreg_group) {
   // The number of registers in a vector register group depends on the register
   // index: 0, 8, 16, 24 each have 8 registers, 4, 12, 20, 28 each have 4,
   // 2, 6, 10, 14, 18, 22, 26, 30 each have two, and all odd numbered register
@@ -59,104 +59,104 @@
   }
 }
 template <typename RegType>
-inline SourceOperandInterface *GetVectorRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorRegisterSourceOp(RiscVState* state,
                                                          int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+inline DestinationOperandInterface* GetVectorRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetVectorMaskRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorMaskRegisterSourceOp(RiscVState* state,
                                                              int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorMaskRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
+inline DestinationOperandInterface* GetVectorMaskRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(RiscVState *state,
+inline DestinationOperandInterface* GetRegisterDestinationOp(RiscVState* state,
                                                              std::string name,
                                                              int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
-RiscV32GVecEncoding::RiscV32GVecEncoding(RiscVState *state) : state_(state) {
+RiscV32GVecEncoding::RiscV32GVecEncoding(RiscVState* state) : state_(state) {
   InitializeSourceOperandGetters();
   InitializeDestinationOperandGetters();
   InitializeSimpleResourceGetters();
@@ -171,12 +171,12 @@
 
 void RiscV32GVecEncoding::InitializeVectorSourceOperandGetters() {
   Insert(source_op_getters_, SourceOpEnum::kVd,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding::v_arith::ExtractVd(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVmask,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto vm = encoding::v_arith::ExtractVm(inst_word_);
            if (vm == 1) {
              // Unmasked, return the True mask.
@@ -186,71 +186,71 @@
            return GetVectorMaskRegisterSourceOp<RVVectorRegister>(state_, 0);
          });
   Insert(source_op_getters_, SourceOpEnum::kVmaskTrue,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            return new RV32VectorTrueOperand(state_);
          });
   Insert(source_op_getters_, SourceOpEnum::kVs1,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding::v_arith::ExtractVs1(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVs2,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding::v_arith::ExtractVs2(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVs3,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding::v_mem::ExtractVs3(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kSimm5,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding::inst32_format::ExtractSimm5(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kUimm5,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding::inst32_format::ExtractUimm5(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kZimm10,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding::inst32_format::ExtractZimm10(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kZimm11,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding::inst32_format::ExtractZimm11(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst1,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(1);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst2,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(2);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst4,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(4);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst8,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(8);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kNf,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num_fields = encoding::v_mem::ExtractNf(inst_word_);
            return new generic::ImmediateOperand<uint8_t>(
                num_fields, absl::StrCat(num_fields + 1));
@@ -259,7 +259,7 @@
 
 void RiscV32GVecEncoding::InitializeVectorDestinationOperandGetters() {
   Insert(dest_op_getters_, DestOpEnum::kVd,
-         [this](int latency) -> DestinationOperandInterface * {
+         [this](int latency) -> DestinationOperandInterface* {
            auto num = encoding::v_arith::ExtractVd(inst_word_);
            return GetVectorRegisterDestinationOp<RVVectorRegister>(
                state_, latency, num);
@@ -270,7 +270,7 @@
   // Source operand getters.
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kAAq),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding::inst32_format::ExtractAq(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -278,7 +278,7 @@
                      }));
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kARl),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding::inst32_format::ExtractRl(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -353,7 +353,7 @@
         if (!res.ok()) {
           return new generic::ImmediateOperand<uint32_t>(csr_indx);
         }
-        auto *csr = res.value();
+        auto* csr = res.value();
         return new generic::ImmediateOperand<uint32_t>(csr_indx, csr->name());
       }));
   source_op_getters_.insert(
@@ -488,34 +488,32 @@
         return new generic::ImmediateOperand<uint32_t>(
             encoding::fence::ExtractPred(inst_word_));
       }));
-  source_op_getters_.insert(
-      std::make_pair(static_cast<int>(SourceOpEnum::kRm),
-                     [this]() -> SourceOperandInterface * {
-                       uint32_t rm = (inst_word_ >> 12) & 0x7;
-                       switch (rm) {
-                         case 0:
-                           return new generic::IntLiteralOperand<0>();
-                         case 1:
-                           return new generic::IntLiteralOperand<1>();
-                         case 2:
-                           return new generic::IntLiteralOperand<2>();
-                         case 3:
-                           return new generic::IntLiteralOperand<3>();
-                         case 4:
-                           return new generic::IntLiteralOperand<4>();
-                         case 5:
-                           return new generic::IntLiteralOperand<5>();
-                         case 6:
-                           return new generic::IntLiteralOperand<6>();
-                         case 7:
-                           return new generic::IntLiteralOperand<7>();
-                         default:
-                           return nullptr;
-                       }
-                     }));
   source_op_getters_.insert(std::make_pair(
-      static_cast<int>(SourceOpEnum::kRd),
-      [this]() -> SourceOperandInterface * {
+      static_cast<int>(SourceOpEnum::kRm), [this]() -> SourceOperandInterface* {
+        uint32_t rm = (inst_word_ >> 12) & 0x7;
+        switch (rm) {
+          case 0:
+            return new generic::IntLiteralOperand<0>();
+          case 1:
+            return new generic::IntLiteralOperand<1>();
+          case 2:
+            return new generic::IntLiteralOperand<2>();
+          case 3:
+            return new generic::IntLiteralOperand<3>();
+          case 4:
+            return new generic::IntLiteralOperand<4>();
+          case 5:
+            return new generic::IntLiteralOperand<5>();
+          case 6:
+            return new generic::IntLiteralOperand<6>();
+          case 7:
+            return new generic::IntLiteralOperand<7>();
+          default:
+            return nullptr;
+        }
+      }));
+  source_op_getters_.insert(std::make_pair(
+      static_cast<int>(SourceOpEnum::kRd), [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRd(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -525,7 +523,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs1),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRs1(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -535,7 +533,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs2),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding::r_type::ExtractRs2(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -559,7 +557,7 @@
             encoding::inst32_format::ExtractUImm(inst_word_));
       }));
   Insert(source_op_getters_, SourceOpEnum::kVm,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto vm = encoding::v_arith::ExtractVm(inst_word_);
            return new generic::ImmediateOperand<bool>(
                vm, absl::StrCat("vm.", vm ? "t" : "f"));
@@ -635,7 +633,7 @@
       }));
   dest_op_getters_.insert(
       std::make_pair(static_cast<int>(DestOpEnum::kRd),
-                     [this](int latency) -> DestinationOperandInterface * {
+                     [this](int latency) -> DestinationOperandInterface* {
                        int num = encoding::r_type::ExtractRd(inst_word_);
                        if (num == 0) {
                          return GetRegisterDestinationOp<RV32Register>(
@@ -690,7 +688,7 @@
                      [](int begin, int end) { return nullptr; }));
 }
 
-ResourceOperandInterface *RiscV32GVecEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV32GVecEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -707,31 +705,31 @@
       static_cast<int>(SimpleResourceEnum::kNone), []() { return nullptr; }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3frd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3frs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -739,7 +737,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractClRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -747,7 +745,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding::inst16_format::ExtractCsRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -755,19 +753,19 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCdrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCfrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -775,7 +773,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::c_r::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -783,65 +781,65 @@
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kCsr),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("csr");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kNextPc),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("next_pc");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -849,7 +847,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -857,7 +855,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding::a_type::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -866,23 +864,23 @@
   // X0 is constant 0, so no resource issue.
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX0),
-                     []() -> generic::SimpleResource * { return nullptr; }));
+                     []() -> generic::SimpleResource* { return nullptr; }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX1),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x1");
                      }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX2),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x2");
                      }));
 }
 
-ResourceOperandInterface *RiscV32GVecEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV32GVecEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -890,19 +888,19 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new generic::SimpleResourceOperand(resource_set, end,
+  auto* op = new generic::SimpleResourceOperand(resource_set, end,
                                                 resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV32GVecEncoding::GetDestination(
+DestinationOperandInterface* RiscV32GVecEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -916,7 +914,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV32GVecEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV32GVecEncoding::GetSource(SlotEnum, int,
                                                        OpcodeEnum opcode,
                                                        SourceOpEnum source_op,
                                                        int source_no) {
diff --git a/riscv/riscv32g_vec_encoding.h b/riscv/riscv32g_vec_encoding.h
index 196e8a1..e6d820c 100644
--- a/riscv/riscv32g_vec_encoding.h
+++ b/riscv/riscv32g_vec_encoding.h
@@ -35,18 +35,18 @@
 class RiscV32GVecEncoding : public RiscV32GVEncodingBase {
  public:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
   using SimpleResourceGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource*()>>;
   using ComplexResourceGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<ResourceOperandInterface *(int, int)>>;
+      int, absl::AnyInvocable<ResourceOperandInterface*(int, int)>>;
 
   static constexpr int kParseGroup32Size = 32;
   static constexpr int kParseGroup16Size = 32;
 
-  explicit RiscV32GVecEncoding(RiscVState *state);
+  explicit RiscV32GVecEncoding(RiscVState* state);
   ~RiscV32GVecEncoding() override;
 
   // Parses an instruction and determines the opcode.
@@ -59,7 +59,7 @@
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
@@ -71,22 +71,22 @@
   // where the resource itself is a register bank, and the argument specifies
   // which register (or more precisely) which encoding "field" specifies the
   // register number.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -98,12 +98,12 @@
   }
 
   // Getter.
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
@@ -128,11 +128,11 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace isa32v
diff --git a/riscv/riscv32gzb_encoding.cc b/riscv/riscv32gzb_encoding.cc
index ed26f29..fa29cfa 100644
--- a/riscv/riscv32gzb_encoding.cc
+++ b/riscv/riscv32gzb_encoding.cc
@@ -37,7 +37,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: clang-tidy false positive.
 
-RiscV32GZBEncoding::RiscV32GZBEncoding(RiscVState *state)
+RiscV32GZBEncoding::RiscV32GZBEncoding(RiscVState* state)
     : state_(state),
       inst_word_(0),
       opcode_(OpcodeEnum::kNone),
@@ -105,7 +105,7 @@
   format_ = format;
 }
 
-ResourceOperandInterface *RiscV32GZBEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV32GZBEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -117,10 +117,10 @@
   return (iter->second)(begin, end);
 }
 
-ResourceOperandInterface *RiscV32GZBEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV32GZBEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -128,19 +128,19 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new generic::SimpleResourceOperand(resource_set, end,
+  auto* op = new generic::SimpleResourceOperand(resource_set, end,
                                                 resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV32GZBEncoding::GetDestination(
+DestinationOperandInterface* RiscV32GZBEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -154,7 +154,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV32GZBEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV32GZBEncoding::GetSource(SlotEnum, int,
                                                       OpcodeEnum opcode,
                                                       SourceOpEnum source_op,
                                                       int source_no) {
diff --git a/riscv/riscv32gzb_encoding.h b/riscv/riscv32gzb_encoding.h
index 96a1104..2c5f17d 100644
--- a/riscv/riscv32gzb_encoding.h
+++ b/riscv/riscv32gzb_encoding.h
@@ -38,30 +38,30 @@
 class RiscV32GZBEncoding : public RiscV32GZBEncodingBase,
                            public RiscVEncodingCommon {
  public:
-  explicit RiscV32GZBEncoding(RiscVState *state);
+  explicit RiscV32GZBEncoding(RiscVState* state);
   ~RiscV32GZBEncoding() override;
 
   void ParseInstruction(uint32_t inst_word);
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -70,25 +70,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -96,8 +96,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace mpact::sim::riscv::isa32gzb
diff --git a/riscv/riscv32gzb_vec_decoder.cc b/riscv/riscv32gzb_vec_decoder.cc
index cdef792..3318637 100644
--- a/riscv/riscv32gzb_vec_decoder.cc
+++ b/riscv/riscv32gzb_vec_decoder.cc
@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV32GZBVecDecoder::RiscV32GZBVecDecoder(RiscVState *state,
-                                           util::MemoryInterface *memory)
+RiscV32GZBVecDecoder::RiscV32GZBVecDecoder(RiscVState* state,
+                                           util::MemoryInterface* memory)
     : state_(state),
       memory_(memory),
       inst_db_(state_->db_factory()->Allocate<uint32_t>(1)) {
@@ -55,17 +55,17 @@
 
 RiscV32GZBVecDecoder::~RiscV32GZBVecDecoder() { inst_db_->DecRef(); }
 
-generic::Instruction *RiscV32GZBVecDecoder::DecodeInstruction(
+generic::Instruction* RiscV32GZBVecDecoder::DecodeInstruction(
     uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa32gvzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAddressMisaligned, address ^ 0x1,
                    inst);
@@ -76,12 +76,12 @@
   // If the address is greater than the max address, return an instruction
   // object that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa32gvzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAccessFault, address, nullptr);
     });
@@ -95,7 +95,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
   return instruction;
 }
 
diff --git a/riscv/riscv32gzb_vec_decoder.h b/riscv/riscv32gzb_vec_decoder.h
index 4ecb035..b5cc9e9 100644
--- a/riscv/riscv32gzb_vec_decoder.h
+++ b/riscv/riscv32gzb_vec_decoder.h
@@ -41,7 +41,7 @@
 class RV32GVZBIsaFactory : public isa32gvzb::RiscV32GVZBInstructionSetFactory {
  public:
   std::unique_ptr<isa32gvzb::Riscv32gvzbSlot> CreateRiscv32gvzbSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa32gvzb::Riscv32gvzbSlot>(state);
   }
 };
@@ -54,28 +54,28 @@
   using SlotEnum = isa32gvzb::SlotEnum;
   using OpcodeEnum = isa32gvzb::OpcodeEnum;
 
-  RiscV32GZBVecDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV32GZBVecDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV32GZBVecDecoder() = delete;
   ~RiscV32GZBVecDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa32gvzb::kOpcodeNames[index];
   }
 
  private:
-  RiscVState *const state_;
-  util::MemoryInterface *const memory_;
+  RiscVState* const state_;
+  util::MemoryInterface* const memory_;
 
   // Buffer used to load instructions from memory. Re-used for each instruction
   // word.
-  generic::DataBuffer *const inst_db_;
+  generic::DataBuffer* const inst_db_;
 
   std::unique_ptr<generic::ProgramError> decode_error_;
   std::unique_ptr<isa32gvzb::RiscV32GZBVecEncoding> riscv_encoding_;
diff --git a/riscv/riscv32gzb_vec_encoding.cc b/riscv/riscv32gzb_vec_encoding.cc
index ea62791..99b3b35 100644
--- a/riscv/riscv32gzb_vec_encoding.cc
+++ b/riscv/riscv32gzb_vec_encoding.cc
@@ -37,7 +37,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: clang-tidy false positive.
 
-RiscV32GZBVecEncoding::RiscV32GZBVecEncoding(RiscVState *state)
+RiscV32GZBVecEncoding::RiscV32GZBVecEncoding(RiscVState* state)
     : state_(state),
       inst_word_(0),
       opcode_(OpcodeEnum::kNone),
@@ -114,7 +114,7 @@
   format_ = format;
 }
 
-ResourceOperandInterface *RiscV32GZBVecEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV32GZBVecEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -126,10 +126,10 @@
   return (iter->second)(begin, end);
 }
 
-ResourceOperandInterface *RiscV32GZBVecEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV32GZBVecEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -137,19 +137,19 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new generic::SimpleResourceOperand(resource_set, end,
+  auto* op = new generic::SimpleResourceOperand(resource_set, end,
                                                 resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV32GZBVecEncoding::GetDestination(
+DestinationOperandInterface* RiscV32GZBVecEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -163,7 +163,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV32GZBVecEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV32GZBVecEncoding::GetSource(SlotEnum, int,
                                                          OpcodeEnum opcode,
                                                          SourceOpEnum source_op,
                                                          int source_no) {
diff --git a/riscv/riscv32gzb_vec_encoding.h b/riscv/riscv32gzb_vec_encoding.h
index c166534..becfe0d 100644
--- a/riscv/riscv32gzb_vec_encoding.h
+++ b/riscv/riscv32gzb_vec_encoding.h
@@ -37,30 +37,30 @@
 class RiscV32GZBVecEncoding : public RiscV32GVZBEncodingBase,
                               public RiscVEncodingCommon {
  public:
-  explicit RiscV32GZBVecEncoding(RiscVState *state);
+  explicit RiscV32GZBVecEncoding(RiscVState* state);
   ~RiscV32GZBVecEncoding() override;
 
   void ParseInstruction(uint32_t inst_word);
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -69,25 +69,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -95,8 +95,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace mpact::sim::riscv::isa32gvzb
diff --git a/riscv/riscv64_decoder.cc b/riscv/riscv64_decoder.cc
index eb2b8dd..39da434 100644
--- a/riscv/riscv64_decoder.cc
+++ b/riscv/riscv64_decoder.cc
@@ -33,10 +33,10 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV64Decoder::RiscV64Decoder(RiscVState *state, util::MemoryInterface *memory)
+RiscV64Decoder::RiscV64Decoder(RiscVState* state, util::MemoryInterface* memory)
     : RiscV64Decoder(state, memory, /*use_abi_names*/ true) {}
 
-RiscV64Decoder::RiscV64Decoder(RiscVState *state, util::MemoryInterface *memory,
+RiscV64Decoder::RiscV64Decoder(RiscVState* state, util::MemoryInterface* memory,
                                bool use_abi_names)
     : state_(state), memory_(memory) {
   // Get a handle to the internal error in the program error controller.
@@ -62,16 +62,16 @@
   delete riscv_encoding_;
 }
 
-generic::Instruction *RiscV64Decoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* RiscV64Decoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa64::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAddressMisaligned, address ^ 0x1,
                    inst);
@@ -82,12 +82,12 @@
   // If the address is greater than the max address, return an instruction
   // object that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa64::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAccessFault, address, nullptr);
     });
@@ -101,7 +101,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_);
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_);
   return instruction;
 }
 
diff --git a/riscv/riscv64_decoder.h b/riscv/riscv64_decoder.h
index 19578f7..6d5422f 100644
--- a/riscv/riscv64_decoder.h
+++ b/riscv/riscv64_decoder.h
@@ -41,7 +41,7 @@
 class RV64IsaFactory : public isa64::RiscV64GInstructionSetFactory {
  public:
   std::unique_ptr<isa64::Riscv64gSlot> CreateRiscv64gSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa64::Riscv64gSlot>(state);
   }
 };
@@ -53,8 +53,8 @@
   using SlotEnum = isa64::SlotEnum;
   using OpcodeEnum = isa64::OpcodeEnum;
 
-  RiscV64Decoder(RiscVState *state, util::MemoryInterface *memory);
-  RiscV64Decoder(RiscVState *state, util::MemoryInterface *memory,
+  RiscV64Decoder(RiscVState* state, util::MemoryInterface* memory);
+  RiscV64Decoder(RiscVState* state, util::MemoryInterface* memory,
                  bool use_abi_names);
   RiscV64Decoder() = delete;
   ~RiscV64Decoder() override;
@@ -62,25 +62,25 @@
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa64::kOpcodeNames[index];
   }
 
   // Getter.
-  isa64::RiscV64GEncoding *riscv_encoding() const { return riscv_encoding_; }
+  isa64::RiscV64GEncoding* riscv_encoding() const { return riscv_encoding_; }
 
  private:
-  RiscVState *state_;
-  util::MemoryInterface *memory_;
+  RiscVState* state_;
+  util::MemoryInterface* memory_;
   std::unique_ptr<generic::ProgramError> decode_error_;
-  generic::DataBuffer *inst_db_;
-  isa64::RiscV64GEncoding *riscv_encoding_;
-  RV64IsaFactory *riscv_isa_factory_;
-  isa64::RiscV64GInstructionSet *riscv_isa_;
+  generic::DataBuffer* inst_db_;
+  isa64::RiscV64GEncoding* riscv_encoding_;
+  RV64IsaFactory* riscv_isa_factory_;
+  isa64::RiscV64GInstructionSet* riscv_isa_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv64_renode.cc b/riscv/riscv64_renode.cc
index fbec443..b888771 100644
--- a/riscv/riscv64_renode.cc
+++ b/riscv/riscv64_renode.cc
@@ -7,10 +7,10 @@
 #include "riscv/riscv_renode.h"
 #include "riscv/riscv_state.h"
 
-::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
+::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
     std::string name, std::string cpu_type,
-    ::mpact::sim::util::MemoryInterface *renode_sysbus) {
-  auto *top = new ::mpact::sim::riscv::RiscVRenode(
+    ::mpact::sim::util::MemoryInterface* renode_sysbus) {
+  auto* top = new ::mpact::sim::riscv::RiscVRenode(
       name, renode_sysbus, ::mpact::sim::riscv::RiscVXlen::RV64);
   return top;
 }
diff --git a/riscv/riscv64_renode.h b/riscv/riscv64_renode.h
index b367b98..c75bb8e 100644
--- a/riscv/riscv64_renode.h
+++ b/riscv/riscv64_renode.h
@@ -9,8 +9,8 @@
 // This file defines the factory method for creating a RiscV 64 simulator for
 // use with ReNode.
 
-extern ::mpact::sim::util::renode::RenodeDebugInterface *CreateMpactSim(
+extern ::mpact::sim::util::renode::RenodeDebugInterface* CreateMpactSim(
     std::string name, std::string cpu_type,
-    ::mpact::sim::util::MemoryInterface *renode_sysbus);
+    ::mpact::sim::util::MemoryInterface* renode_sysbus);
 
 #endif  // THIRD_PARTY_MPACT_RISCV_RISCV64_RENODE_H_
diff --git a/riscv/riscv64g_bin_encoder_interface.cc b/riscv/riscv64g_bin_encoder_interface.cc
index 7e02c18..e44d771 100644
--- a/riscv/riscv64g_bin_encoder_interface.cc
+++ b/riscv/riscv64g_bin_encoder_interface.cc
@@ -49,14 +49,14 @@
 absl::StatusOr<std::tuple<uint64_t, int>>
 RiscV64GBinEncoderInterface::GetOpcodeEncoding(SlotEnum slot, int entry,
                                                OpcodeEnum opcode,
-                                               ResolverInterface *resolver) {
+                                               ResolverInterface* resolver) {
   return encoding64::kOpcodeEncodings->at(opcode);
 }
 
 absl::StatusOr<uint64_t> RiscV64GBinEncoderInterface::GetSrcOpEncoding(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, SourceOpEnum source_op, int source_num,
-    ResolverInterface *resolver) {
+    ResolverInterface* resolver) {
   auto iter = source_op_map_.find(*source_op);
   if (iter == source_op_map_.end()) {
     return absl::NotFoundError(absl::StrCat(
@@ -68,7 +68,7 @@
 absl::Status RiscV64GBinEncoderInterface::AppendSrcOpRelocation(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, SourceOpEnum source_op, int source_num,
-    ResolverInterface *resolver, std::vector<RelocationInfo> &relocations) {
+    ResolverInterface* resolver, std::vector<RelocationInfo>& relocations) {
   auto iter = relocation_source_op_map_.find(std::tie(opcode, source_op));
   if (iter == relocation_source_op_map_.end()) return absl::OkStatus();
   return iter->second(address, text, resolver, relocations);
@@ -77,7 +77,7 @@
 absl::StatusOr<uint64_t> RiscV64GBinEncoderInterface::GetDestOpEncoding(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, DestOpEnum dest_op, int dest_num,
-    ResolverInterface *resolver) {
+    ResolverInterface* resolver) {
   auto iter = dest_op_map_.find(*dest_op);
   if (iter == dest_op_map_.end()) {
     return absl::NotFoundError(
@@ -89,7 +89,7 @@
 absl::StatusOr<uint64_t> RiscV64GBinEncoderInterface::GetListDestOpEncoding(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, ListDestOpEnum dest_op, int dest_num,
-    ResolverInterface *resolver) {
+    ResolverInterface* resolver) {
   auto iter = list_dest_op_map_.find(*dest_op);
   if (iter == list_dest_op_map_.end()) {
     return absl::NotFoundError(absl::StrCat(
@@ -101,7 +101,7 @@
 absl::Status RiscV64GBinEncoderInterface::AppendDestOpRelocation(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, DestOpEnum dest_op, int dest_num,
-    ResolverInterface *resolver, std::vector<RelocationInfo> &relocations) {
+    ResolverInterface* resolver, std::vector<RelocationInfo>& relocations) {
   // There are no destination operands that require relocation.
   return absl::OkStatus();
 }
@@ -109,7 +109,7 @@
 absl::StatusOr<uint64_t> RiscV64GBinEncoderInterface::GetListSrcOpEncoding(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
     OpcodeEnum opcode, ListSourceOpEnum source_op, int source_num,
-    ResolverInterface *resolver) {
+    ResolverInterface* resolver) {
   auto iter = list_source_op_map_.find(*source_op);
   if (iter == list_source_op_map_.end()) {
     return absl::NotFoundError(absl::StrCat(
@@ -120,7 +120,7 @@
 
 absl::StatusOr<uint64_t> RiscV64GBinEncoderInterface::GetPredOpEncoding(
     uint64_t address, absl::string_view text, SlotEnum slot, int entry,
-    OpcodeEnum opcode, PredOpEnum pred_op, ResolverInterface *resolver) {
+    OpcodeEnum opcode, PredOpEnum pred_op, ResolverInterface* resolver) {
   auto iter = pred_op_map_.find(*pred_op);
   if (iter == pred_op_map_.end()) {
     return absl::NotFoundError(absl::StrCat(
diff --git a/riscv/riscv64g_bin_encoder_interface.h b/riscv/riscv64g_bin_encoder_interface.h
index f25fe1d..ec8726f 100644
--- a/riscv/riscv64g_bin_encoder_interface.h
+++ b/riscv/riscv64g_bin_encoder_interface.h
@@ -44,55 +44,55 @@
 class RiscV64GBinEncoderInterface : public RiscV64GEncoderInterfaceBase {
  public:
   RiscV64GBinEncoderInterface();
-  RiscV64GBinEncoderInterface(const RiscV64GBinEncoderInterface &) = delete;
-  RiscV64GBinEncoderInterface &operator=(const RiscV64GBinEncoderInterface &) =
+  RiscV64GBinEncoderInterface(const RiscV64GBinEncoderInterface&) = delete;
+  RiscV64GBinEncoderInterface& operator=(const RiscV64GBinEncoderInterface&) =
       delete;
   ~RiscV64GBinEncoderInterface() override = default;
 
   absl::StatusOr<std::tuple<uint64_t, int>> GetOpcodeEncoding(
       SlotEnum slot, int entry, OpcodeEnum opcode,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
   absl::StatusOr<uint64_t> GetSrcOpEncoding(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, SourceOpEnum source_op, int source_num,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
   absl::Status AppendSrcOpRelocation(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, SourceOpEnum source_op, int source_num,
-      ResolverInterface *resolver,
-      std::vector<RelocationInfo> &relocations) override;
+      ResolverInterface* resolver,
+      std::vector<RelocationInfo>& relocations) override;
   absl::StatusOr<uint64_t> GetDestOpEncoding(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, DestOpEnum dest_op, int dest_num,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
   absl::Status AppendDestOpRelocation(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, DestOpEnum dest_op, int dest_num,
-      ResolverInterface *resolver,
-      std::vector<RelocationInfo> &relocations) override;
+      ResolverInterface* resolver,
+      std::vector<RelocationInfo>& relocations) override;
   absl::StatusOr<uint64_t> GetListSrcOpEncoding(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, ListSourceOpEnum source_op, int source_num,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
   absl::StatusOr<uint64_t> GetListDestOpEncoding(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, ListDestOpEnum dest_op, int dest_num,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
   absl::StatusOr<uint64_t> GetPredOpEncoding(
       uint64_t address, absl::string_view text, SlotEnum slot, int entry,
       OpcodeEnum opcode, PredOpEnum pred_op,
-      ResolverInterface *resolver) override;
+      ResolverInterface* resolver) override;
 
  private:
   using OpMap = absl::flat_hash_map<
       int, std::function<absl::StatusOr<uint64_t>(uint64_t, absl::string_view,
-                                                  ResolverInterface *)>>;
+                                                  ResolverInterface*)>>;
 
   using RelocationMap =
       absl::flat_hash_map<std::tuple<OpcodeEnum, SourceOpEnum>,
                           std::function<absl::Status(
-                              uint64_t, absl::string_view, ResolverInterface *,
-                              std::vector<RelocationInfo> &)>>;
+                              uint64_t, absl::string_view, ResolverInterface*,
+                              std::vector<RelocationInfo>&)>>;
 
   OpMap source_op_map_;
   RelocationMap relocation_source_op_map_;
diff --git a/riscv/riscv64g_bitmanip_decoder.cc b/riscv/riscv64g_bitmanip_decoder.cc
index 708d4b2..a69b537 100644
--- a/riscv/riscv64g_bitmanip_decoder.cc
+++ b/riscv/riscv64g_bitmanip_decoder.cc
@@ -32,8 +32,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV64GBitmanipDecoder::RiscV64GBitmanipDecoder(RiscVState *state,
-                                                 util::MemoryInterface *memory)
+RiscV64GBitmanipDecoder::RiscV64GBitmanipDecoder(RiscVState* state,
+                                                 util::MemoryInterface* memory)
     : state_(state), memory_(memory) {
   // Need a data buffer to load instructions from memory. Allocate a single
   // buffer that can be reused for each instruction word.
@@ -53,17 +53,17 @@
   inst_db_->DecRef();
 }
 
-generic::Instruction *RiscV64GBitmanipDecoder::DecodeInstruction(
+generic::Instruction* RiscV64GBitmanipDecoder::DecodeInstruction(
     uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa64gzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAddressMisaligned,
                    inst->address() ^ 0x1, inst);
@@ -74,12 +74,12 @@
   // If the address is greater than the max address, return an instruction
   // that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(0, state_);
+    auto* inst = new generic::Instruction(0, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa64gzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this](generic::Instruction *inst) {
+    inst->set_semantic_function([this](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, inst->address(),
                    *ExceptionCode::kInstructionAccessFault, inst->address(),
                    nullptr);
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_);
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_);
   return instruction;
 }
 
diff --git a/riscv/riscv64g_bitmanip_decoder.h b/riscv/riscv64g_bitmanip_decoder.h
index 52c35a5..683dbde 100644
--- a/riscv/riscv64g_bitmanip_decoder.h
+++ b/riscv/riscv64g_bitmanip_decoder.h
@@ -41,7 +41,7 @@
 class RV64GZBIsaFactory : public isa64gzb::RiscV64GZBInstructionSetFactory {
  public:
   std::unique_ptr<isa64gzb::Riscv64gzbSlot> CreateRiscv64gzbSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa64gzb::Riscv64gzbSlot>(state);
   }
 };
@@ -53,33 +53,33 @@
   using SlotEnum = isa64gzb::SlotEnum;
   using OpcodeEnum = isa64gzb::OpcodeEnum;
 
-  RiscV64GBitmanipDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV64GBitmanipDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV64GBitmanipDecoder() = delete;
   ~RiscV64GBitmanipDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa64gzb::kOpcodeNames[index];
   }
 
   // Getter.
-  isa64gzb::RiscV64GZBEncoding *riscv_encoding() const {
+  isa64gzb::RiscV64GZBEncoding* riscv_encoding() const {
     return riscv_encoding_;
   }
 
  private:
-  RiscVState *state_;
-  util::MemoryInterface *memory_;
-  generic::DataBuffer *inst_db_;
-  isa64gzb::RiscV64GZBEncoding *riscv_encoding_;
-  RV64GZBIsaFactory *riscv_isa_factory_;
-  isa64gzb::RiscV64GZBInstructionSet *riscv_isa_;
+  RiscVState* state_;
+  util::MemoryInterface* memory_;
+  generic::DataBuffer* inst_db_;
+  isa64gzb::RiscV64GZBEncoding* riscv_encoding_;
+  RV64GZBIsaFactory* riscv_isa_factory_;
+  isa64gzb::RiscV64GZBInstructionSet* riscv_isa_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv64g_encoding.cc b/riscv/riscv64g_encoding.cc
index cebbc65..7db0cb4 100644
--- a/riscv/riscv64g_encoding.cc
+++ b/riscv/riscv64g_encoding.cc
@@ -39,54 +39,54 @@
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(RiscVState *state,
+inline DestinationOperandInterface* GetRegisterDestinationOp(RiscVState* state,
                                                              std::string name,
                                                              int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
-RiscV64GEncoding::RiscV64GEncoding(RiscVState *state)
+RiscV64GEncoding::RiscV64GEncoding(RiscVState* state)
     : RiscV64GEncoding(state, true) {}
 
-RiscV64GEncoding::RiscV64GEncoding(RiscVState *state, bool use_abi_names)
+RiscV64GEncoding::RiscV64GEncoding(RiscVState* state, bool use_abi_names)
     : state_(state) {
   if (use_abi_names) {
     xreg_alias_ = xreg_abi_names_;
@@ -107,7 +107,7 @@
   // Source operand getters.
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kAAq),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding64::inst32_format::ExtractAq(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -115,7 +115,7 @@
                      }));
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kARl),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding64::inst32_format::ExtractRl(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -203,7 +203,7 @@
         if (!res.ok()) {
           return new generic::ImmediateOperand<uint32_t>(csr_indx);
         }
-        auto *csr = res.value();
+        auto* csr = res.value();
         return new generic::ImmediateOperand<uint32_t>(csr_indx, csr->name());
       }));
   source_op_getters_.insert(
@@ -332,34 +332,32 @@
         return new generic::ImmediateOperand<uint32_t>(
             encoding64::fence::ExtractPred(inst_word_));
       }));
-  source_op_getters_.insert(
-      std::make_pair(static_cast<int>(SourceOpEnum::kRm),
-                     [this]() -> SourceOperandInterface * {
-                       uint32_t rm = (inst_word_ >> 12) & 0x7;
-                       switch (rm) {
-                         case 0:
-                           return new generic::IntLiteralOperand<0>();
-                         case 1:
-                           return new generic::IntLiteralOperand<1>();
-                         case 2:
-                           return new generic::IntLiteralOperand<2>();
-                         case 3:
-                           return new generic::IntLiteralOperand<3>();
-                         case 4:
-                           return new generic::IntLiteralOperand<4>();
-                         case 5:
-                           return new generic::IntLiteralOperand<5>();
-                         case 6:
-                           return new generic::IntLiteralOperand<6>();
-                         case 7:
-                           return new generic::IntLiteralOperand<7>();
-                         default:
-                           return nullptr;
-                       }
-                     }));
   source_op_getters_.insert(std::make_pair(
-      static_cast<int>(SourceOpEnum::kRd),
-      [this]() -> SourceOperandInterface * {
+      static_cast<int>(SourceOpEnum::kRm), [this]() -> SourceOperandInterface* {
+        uint32_t rm = (inst_word_ >> 12) & 0x7;
+        switch (rm) {
+          case 0:
+            return new generic::IntLiteralOperand<0>();
+          case 1:
+            return new generic::IntLiteralOperand<1>();
+          case 2:
+            return new generic::IntLiteralOperand<2>();
+          case 3:
+            return new generic::IntLiteralOperand<3>();
+          case 4:
+            return new generic::IntLiteralOperand<4>();
+          case 5:
+            return new generic::IntLiteralOperand<5>();
+          case 6:
+            return new generic::IntLiteralOperand<6>();
+          case 7:
+            return new generic::IntLiteralOperand<7>();
+          default:
+            return nullptr;
+        }
+      }));
+  source_op_getters_.insert(std::make_pair(
+      static_cast<int>(SourceOpEnum::kRd), [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRd(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -374,7 +372,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs1),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRs1(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -389,7 +387,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs2),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRs2(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -492,7 +490,7 @@
       }));
   dest_op_getters_.insert(
       std::make_pair(static_cast<int>(DestOpEnum::kRd),
-                     [this](int latency) -> DestinationOperandInterface * {
+                     [this](int latency) -> DestinationOperandInterface* {
                        int num = encoding64::r_type::ExtractRd(inst_word_);
                        if (num == 0) {
                          return GetRegisterDestinationOp<RV64Register>(
@@ -561,7 +559,7 @@
                      [](int begin, int end) { return nullptr; }));
 }
 
-ResourceOperandInterface *RiscV64GEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV64GEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -578,19 +576,19 @@
       static_cast<int>(SimpleResourceEnum::kNone), []() { return nullptr; }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -598,7 +596,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -606,7 +604,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractCsRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -614,13 +612,13 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCdrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -628,7 +626,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -636,65 +634,65 @@
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kCsr),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("csr");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kNextPc),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("next_pc");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -702,7 +700,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -710,7 +708,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -719,23 +717,23 @@
   // X0 is constant 0, so no resource issue.
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX0),
-                     []() -> generic::SimpleResource * { return nullptr; }));
+                     []() -> generic::SimpleResource* { return nullptr; }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX1),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x1");
                      }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX2),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x2");
                      }));
 }
 
-ResourceOperandInterface *RiscV64GEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV64GEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -743,18 +741,18 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
+  auto* op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV64GEncoding::GetDestination(
+DestinationOperandInterface* RiscV64GEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum, DestOpEnum dest_op, int dest_no, int latency) {
   int index = static_cast<int>(dest_op);
   auto iter = dest_op_getters_.find(index);
@@ -765,7 +763,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV64GEncoding::GetSource(SlotEnum, int, OpcodeEnum,
+SourceOperandInterface* RiscV64GEncoding::GetSource(SlotEnum, int, OpcodeEnum,
                                                     SourceOpEnum source_op,
                                                     int source_no) {
   int index = static_cast<int>(source_op);
diff --git a/riscv/riscv64g_encoding.h b/riscv/riscv64g_encoding.h
index 92a96f9..ea1390c 100644
--- a/riscv/riscv64g_encoding.h
+++ b/riscv/riscv64g_encoding.h
@@ -39,13 +39,13 @@
 class RiscV64GEncoding : public RiscV64GEncodingBase {
  public:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
   using SimpleResourceGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource*()>>;
   using ComplexResourceGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<ResourceOperandInterface *(int, int)>>;
+      int, absl::AnyInvocable<ResourceOperandInterface*(int, int)>>;
 
   static constexpr int kParseGroup32Size = 32;
   static constexpr int kParseGroup16Size = 32;
@@ -62,8 +62,8 @@
       "a1",   "a2", "a3", "a4", "a5",  "a6",  "a7", "s2", "s3", "s4", "s5",
       "s6",   "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
 
-  explicit RiscV64GEncoding(RiscVState *state);
-  RiscV64GEncoding(RiscVState *state, bool use_abi_names);
+  explicit RiscV64GEncoding(RiscVState* state);
+  RiscV64GEncoding(RiscVState* state, bool use_abi_names);
   ~RiscV64GEncoding() override;
 
   // Parses an instruction and determines the opcode.
@@ -76,7 +76,7 @@
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
@@ -88,22 +88,22 @@
   // where the resource itself is a register bank, and the argument specifies
   // which register (or more precisely) which encoding "field" specifies the
   // register number.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -114,18 +114,18 @@
   }
 
   // Getter.
-  generic::SimpleResourcePool *resource_pool() const { return resource_pool_; }
+  generic::SimpleResourcePool* resource_pool() const { return resource_pool_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
-  RiscVState *state() const { return state_; }
+  RiscVState* state() const { return state_; }
   OpcodeEnum opcode() const { return opcode_; }
   uint32_t inst_word() const { return inst_word_; }
 
@@ -140,17 +140,17 @@
 
   // Pointer to the register names to be used. This will either point to
   // xreg_names or xreg_abi_names.
-  const std::string *xreg_alias_;
+  const std::string* xreg_alias_;
 
   SourceOpGetterMap source_op_getters_;
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace isa64
diff --git a/riscv/riscv64g_vec_decoder.cc b/riscv/riscv64g_vec_decoder.cc
index d7d3abd..f3fde6e 100644
--- a/riscv/riscv64g_vec_decoder.cc
+++ b/riscv/riscv64g_vec_decoder.cc
@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV64GVecDecoder::RiscV64GVecDecoder(RiscVState *state,
-                                       util::MemoryInterface *memory)
+RiscV64GVecDecoder::RiscV64GVecDecoder(RiscVState* state,
+                                       util::MemoryInterface* memory)
     : state_(state),
       memory_(memory),
       inst_db_(state_->db_factory()->Allocate<uint32_t>(1)) {
@@ -55,16 +55,16 @@
 
 RiscV64GVecDecoder::~RiscV64GVecDecoder() { inst_db_->DecRef(); }
 
-generic::Instruction *RiscV64GVecDecoder::DecodeInstruction(uint64_t address) {
+generic::Instruction* RiscV64GVecDecoder::DecodeInstruction(uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa64v::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAddressMisaligned, address ^ 0x1,
                    inst);
@@ -75,12 +75,12 @@
   // If the address is greater than the max address, return an instruction
   // object that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa64v::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAccessFault, address, nullptr);
     });
@@ -94,7 +94,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
   return instruction;
 }
 
diff --git a/riscv/riscv64g_vec_decoder.h b/riscv/riscv64g_vec_decoder.h
index 0a1a2e3..9a651cf 100644
--- a/riscv/riscv64g_vec_decoder.h
+++ b/riscv/riscv64g_vec_decoder.h
@@ -41,7 +41,7 @@
 class RV64GVIsaFactory : public isa64v::RiscV64GVInstructionSetFactory {
  public:
   std::unique_ptr<isa64v::Riscv64gvSlot> CreateRiscv64gvSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa64v::Riscv64gvSlot>(state);
   }
 };
@@ -54,28 +54,28 @@
   using SlotEnum = isa64v::SlotEnum;
   using OpcodeEnum = isa64v::OpcodeEnum;
 
-  RiscV64GVecDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV64GVecDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV64GVecDecoder() = delete;
   ~RiscV64GVecDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa64v::kOpcodeNames[index];
   }
 
  private:
-  RiscVState *const state_;
-  util::MemoryInterface *const memory_;
+  RiscVState* const state_;
+  util::MemoryInterface* const memory_;
 
   // Buffer used to load instructions from memory. Re-used for each instruction
   // word.
-  generic::DataBuffer *const inst_db_;
+  generic::DataBuffer* const inst_db_;
 
   std::unique_ptr<generic::ProgramError> decode_error_;
   std::unique_ptr<isa64v::RiscV64GVecEncoding> riscv_encoding_;
diff --git a/riscv/riscv64g_vec_encoding.cc b/riscv/riscv64g_vec_encoding.cc
index a7505ed..d235d5a 100644
--- a/riscv/riscv64g_vec_encoding.cc
+++ b/riscv/riscv64g_vec_encoding.cc
@@ -47,13 +47,13 @@
 constexpr int kNumRegTable[8] = {8, 1, 2, 1, 4, 1, 2, 1};
 
 template <typename M, typename E, typename G>
-inline void Insert(M &map, E entry, G getter) {
+inline void Insert(M& map, E entry, G getter) {
   map.insert(std::make_pair(static_cast<int>(entry), getter));
 }
 
 template <typename RegType>
-inline void GetVRegGroup(RiscVState *state, int reg_num,
-                         std::vector<generic::RegisterBase *> *vreg_group) {
+inline void GetVRegGroup(RiscVState* state, int reg_num,
+                         std::vector<generic::RegisterBase*>* vreg_group) {
   // The number of registers in a vector register group depends on the register
   // index: 0, 8, 16, 24 each have 8 registers, 4, 12, 20, 28 each have 4,
   // 2, 6, 10, 14, 18, 22, 26, 30 each have two, and all odd numbered register
@@ -65,109 +65,109 @@
   }
 }
 template <typename RegType>
-inline SourceOperandInterface *GetVectorRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorRegisterSourceOp(RiscVState* state,
                                                          int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+inline DestinationOperandInterface* GetVectorRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetVectorMaskRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorMaskRegisterSourceOp(RiscVState* state,
                                                              int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorMaskRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
+inline DestinationOperandInterface* GetVectorMaskRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(RiscVState *state,
+inline DestinationOperandInterface* GetRegisterDestinationOp(RiscVState* state,
                                                              std::string name,
                                                              int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
 }  // namespace
 
-RiscV64GVecEncoding::RiscV64GVecEncoding(RiscVState *state)
+RiscV64GVecEncoding::RiscV64GVecEncoding(RiscVState* state)
     : RiscV64GVecEncoding(state, true) {}
 
-RiscV64GVecEncoding::RiscV64GVecEncoding(RiscVState *state, bool use_abi_names)
+RiscV64GVecEncoding::RiscV64GVecEncoding(RiscVState* state, bool use_abi_names)
     : state_(state) {
   if (use_abi_names) {
     xreg_alias_ = xreg_abi_names_;
@@ -200,7 +200,7 @@
   // Source operand getters.
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kAAq),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding64::inst32_format::ExtractAq(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -208,7 +208,7 @@
                      }));
   source_op_getters_.insert(
       std::make_pair(static_cast<int>(SourceOpEnum::kARl),
-                     [this]() -> SourceOperandInterface * {
+                     [this]() -> SourceOperandInterface* {
                        if (encoding64::inst32_format::ExtractRl(inst_word_)) {
                          return new generic::IntLiteralOperand<1>();
                        }
@@ -296,7 +296,7 @@
         if (!res.ok()) {
           return new generic::ImmediateOperand<uint32_t>(csr_indx);
         }
-        auto *csr = res.value();
+        auto* csr = res.value();
         return new generic::ImmediateOperand<uint32_t>(csr_indx, csr->name());
       }));
   source_op_getters_.insert(
@@ -425,34 +425,32 @@
         return new generic::ImmediateOperand<uint32_t>(
             encoding64::fence::ExtractPred(inst_word_));
       }));
-  source_op_getters_.insert(
-      std::make_pair(static_cast<int>(SourceOpEnum::kRm),
-                     [this]() -> SourceOperandInterface * {
-                       uint32_t rm = (inst_word_ >> 12) & 0x7;
-                       switch (rm) {
-                         case 0:
-                           return new generic::IntLiteralOperand<0>();
-                         case 1:
-                           return new generic::IntLiteralOperand<1>();
-                         case 2:
-                           return new generic::IntLiteralOperand<2>();
-                         case 3:
-                           return new generic::IntLiteralOperand<3>();
-                         case 4:
-                           return new generic::IntLiteralOperand<4>();
-                         case 5:
-                           return new generic::IntLiteralOperand<5>();
-                         case 6:
-                           return new generic::IntLiteralOperand<6>();
-                         case 7:
-                           return new generic::IntLiteralOperand<7>();
-                         default:
-                           return nullptr;
-                       }
-                     }));
   source_op_getters_.insert(std::make_pair(
-      static_cast<int>(SourceOpEnum::kRd),
-      [this]() -> SourceOperandInterface * {
+      static_cast<int>(SourceOpEnum::kRm), [this]() -> SourceOperandInterface* {
+        uint32_t rm = (inst_word_ >> 12) & 0x7;
+        switch (rm) {
+          case 0:
+            return new generic::IntLiteralOperand<0>();
+          case 1:
+            return new generic::IntLiteralOperand<1>();
+          case 2:
+            return new generic::IntLiteralOperand<2>();
+          case 3:
+            return new generic::IntLiteralOperand<3>();
+          case 4:
+            return new generic::IntLiteralOperand<4>();
+          case 5:
+            return new generic::IntLiteralOperand<5>();
+          case 6:
+            return new generic::IntLiteralOperand<6>();
+          case 7:
+            return new generic::IntLiteralOperand<7>();
+          default:
+            return nullptr;
+        }
+      }));
+  source_op_getters_.insert(std::make_pair(
+      static_cast<int>(SourceOpEnum::kRd), [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRd(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -467,7 +465,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs1),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRs1(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -482,7 +480,7 @@
       }));
   source_op_getters_.insert(std::make_pair(
       static_cast<int>(SourceOpEnum::kRs2),
-      [this]() -> SourceOperandInterface * {
+      [this]() -> SourceOperandInterface* {
         int num = encoding64::r_type::ExtractRs2(inst_word_);
         if (num == 0)
           return new generic::IntLiteralOperand<0>({1}, xreg_alias_[0]);
@@ -592,7 +590,7 @@
       }));
   dest_op_getters_.insert(
       std::make_pair(static_cast<int>(DestOpEnum::kRd),
-                     [this](int latency) -> DestinationOperandInterface * {
+                     [this](int latency) -> DestinationOperandInterface* {
                        int num = encoding64::r_type::ExtractRd(inst_word_);
                        if (num == 0) {
                          return GetRegisterDestinationOp<RV64Register>(
@@ -651,12 +649,12 @@
 
 void RiscV64GVecEncoding::InitializeVectorSourceOperandGetters() {
   Insert(source_op_getters_, SourceOpEnum::kVd,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding64::v_arith::ExtractVd(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVmask,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto vm = encoding64::v_arith::ExtractVm(inst_word_);
            if (vm == 1) {
              // Unmasked, return the True mask.
@@ -666,79 +664,79 @@
            return GetVectorMaskRegisterSourceOp<RVVectorRegister>(state_, 0);
          });
   Insert(source_op_getters_, SourceOpEnum::kVmaskTrue,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            return new RV32VectorTrueOperand(state_);
          });
   Insert(source_op_getters_, SourceOpEnum::kVm,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto vm = encoding64::v_arith::ExtractVm(inst_word_);
            return new generic::ImmediateOperand<bool>(
                vm, absl::StrCat("vm.", vm ? "t" : "f"));
          });
   Insert(source_op_getters_, SourceOpEnum::kVs1,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding64::v_arith::ExtractVs1(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVs2,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding64::v_arith::ExtractVs2(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
   Insert(source_op_getters_, SourceOpEnum::kVs3,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num = encoding64::v_mem::ExtractVs3(inst_word_);
            return GetVectorRegisterSourceOp<RVVectorRegister>(state_, num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kSimm5,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding64::inst32_format::ExtractSimm5(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kUimm5,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num = encoding64::inst32_format::ExtractUimm5(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kZimm10,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num =
                encoding64::inst32_format::ExtractZimm10(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kZimm11,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            const auto num =
                encoding64::inst32_format::ExtractZimm11(inst_word_);
            return new generic::ImmediateOperand<int32_t>(num);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst1,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(1);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst2,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(2);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst4,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(4);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kConst8,
-         []() -> SourceOperandInterface * {
+         []() -> SourceOperandInterface* {
            return new generic::ImmediateOperand<int32_t>(8);
          });
 
   Insert(source_op_getters_, SourceOpEnum::kNf,
-         [this]() -> SourceOperandInterface * {
+         [this]() -> SourceOperandInterface* {
            auto num_fields = encoding64::v_mem::ExtractNf(inst_word_);
            return new generic::ImmediateOperand<uint8_t>(
                num_fields, absl::StrCat(num_fields + 1));
@@ -747,7 +745,7 @@
 
 void RiscV64GVecEncoding::InitializeVectorDestinationOperandGetters() {
   Insert(dest_op_getters_, DestOpEnum::kVd,
-         [this](int latency) -> DestinationOperandInterface * {
+         [this](int latency) -> DestinationOperandInterface* {
            auto num = encoding64::v_arith::ExtractVd(inst_word_);
            return GetVectorRegisterDestinationOp<RVVectorRegister>(
                state_, latency, num);
@@ -772,7 +770,7 @@
                      [](int begin, int end) { return nullptr; }));
 }
 
-ResourceOperandInterface *RiscV64GVecEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV64GVecEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -789,19 +787,19 @@
       static_cast<int>(SimpleResourceEnum::kNone), []() { return nullptr; }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3drs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractCsRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -809,7 +807,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractClRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -817,7 +815,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kC3rs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         int num = encoding64::inst16_format::ExtractCsRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -825,13 +823,13 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCdrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -839,7 +837,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kCrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::c_r::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -847,65 +845,65 @@
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kCsr),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("csr");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kDrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRd(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs1(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs2(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kFrs3),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::r4_type::ExtractRs3(inst_word_);
         return resource_pool_->GetOrAddResource(absl::StrCat("d", num));
       }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kNextPc),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("next_pc");
                      }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRd),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRd(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -913,7 +911,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs1),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs1(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -921,7 +919,7 @@
       }));
   simple_resource_getters_.insert(std::make_pair(
       static_cast<int>(SimpleResourceEnum::kRs2),
-      [this]() -> generic::SimpleResource * {
+      [this]() -> generic::SimpleResource* {
         auto num = encoding64::a_type::ExtractRs2(inst_word_);
         // If num is 0 it refers to the zero register. No resource.
         if (num == 0) return nullptr;
@@ -930,23 +928,23 @@
   // X0 is constant 0, so no resource issue.
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX0),
-                     []() -> generic::SimpleResource * { return nullptr; }));
+                     []() -> generic::SimpleResource* { return nullptr; }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX1),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x1");
                      }));
   simple_resource_getters_.insert(
       std::make_pair(static_cast<int>(SimpleResourceEnum::kX2),
-                     [this]() -> generic::SimpleResource * {
+                     [this]() -> generic::SimpleResource* {
                        return resource_pool_->GetOrAddResource("x2");
                      }));
 }
 
-ResourceOperandInterface *RiscV64GVecEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV64GVecEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -954,18 +952,18 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
+  auto* op = new SimpleResourceOperand(resource_set, end, resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV64GVecEncoding::GetDestination(
+DestinationOperandInterface* RiscV64GVecEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum, DestOpEnum dest_op, int dest_no, int latency) {
   int index = static_cast<int>(dest_op);
   auto iter = dest_op_getters_.find(index);
@@ -976,7 +974,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV64GVecEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV64GVecEncoding::GetSource(SlotEnum, int,
                                                        OpcodeEnum,
                                                        SourceOpEnum source_op,
                                                        int source_no) {
diff --git a/riscv/riscv64g_vec_encoding.h b/riscv/riscv64g_vec_encoding.h
index 4cec413..214e188 100644
--- a/riscv/riscv64g_vec_encoding.h
+++ b/riscv/riscv64g_vec_encoding.h
@@ -38,19 +38,19 @@
 class RiscV64GVecEncoding : public RiscV64GVEncodingBase {
  public:
   using SourceOpGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
   using DestOpGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+      int, absl::AnyInvocable<DestinationOperandInterface*(int)>>;
   using SimpleResourceGetterMap =
-      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource *()>>;
+      absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource*()>>;
   using ComplexResourceGetterMap = absl::flat_hash_map<
-      int, absl::AnyInvocable<ResourceOperandInterface *(int, int)>>;
+      int, absl::AnyInvocable<ResourceOperandInterface*(int, int)>>;
 
   static constexpr int kParseGroup32Size = 32;
   static constexpr int kParseGroup16Size = 32;
 
-  explicit RiscV64GVecEncoding(RiscVState *state);
-  RiscV64GVecEncoding(RiscVState *state, bool use_abi_names);
+  explicit RiscV64GVecEncoding(RiscVState* state);
+  RiscV64GVecEncoding(RiscVState* state, bool use_abi_names);
   ~RiscV64GVecEncoding() override;
 
   // Parses an instruction and determines the opcode.
@@ -63,7 +63,7 @@
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
 
   // There is no predicate, so return nullptr.
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
@@ -75,22 +75,22 @@
   // where the resource itself is a register bank, and the argument specifies
   // which register (or more precisely) which encoding "field" specifies the
   // register number.
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
   // The following method returns a source operand that corresponds to the
   // particular operand field.
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
   // The following method returns a destination operand that corresponds to the
   // particular operand field.
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
   // This method returns latency for any destination operand for which the
@@ -102,12 +102,12 @@
 
   // Getter.
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
@@ -136,10 +136,10 @@
       "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
       "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"};
 
-  RiscVState *state() const { return state_; }
+  RiscVState* state() const { return state_; }
   OpcodeEnum opcode() const { return opcode_; }
   uint32_t inst_word() const { return inst_word_; }
-  generic::SimpleResourcePool *resource_pool() const { return resource_pool_; }
+  generic::SimpleResourcePool* resource_pool() const { return resource_pool_; }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
@@ -154,17 +154,17 @@
 
   // Pointer to the register names to be used. This will either point to
   // xreg_names or xreg_abi_names.
-  const std::string *xreg_alias_;
+  const std::string* xreg_alias_;
 
   SourceOpGetterMap source_op_getters_;
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace isa64v
diff --git a/riscv/riscv64gzb_encoding.cc b/riscv/riscv64gzb_encoding.cc
index 9c9d608..fa356f3 100644
--- a/riscv/riscv64gzb_encoding.cc
+++ b/riscv/riscv64gzb_encoding.cc
@@ -36,7 +36,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: clang-tidy false positive.
 
-RiscV64GZBEncoding::RiscV64GZBEncoding(RiscVState *state)
+RiscV64GZBEncoding::RiscV64GZBEncoding(RiscVState* state)
     : state_(state),
       inst_word_(0),
       opcode_(OpcodeEnum::kNone),
@@ -102,7 +102,7 @@
   format_ = format;
 }
 
-ResourceOperandInterface *RiscV64GZBEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV64GZBEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -114,10 +114,10 @@
   return (iter->second)(begin, end);
 }
 
-ResourceOperandInterface *RiscV64GZBEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV64GZBEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -125,19 +125,19 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new generic::SimpleResourceOperand(resource_set, end,
+  auto* op = new generic::SimpleResourceOperand(resource_set, end,
                                                 resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV64GZBEncoding::GetDestination(
+DestinationOperandInterface* RiscV64GZBEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -151,7 +151,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV64GZBEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV64GZBEncoding::GetSource(SlotEnum, int,
                                                       OpcodeEnum opcode,
                                                       SourceOpEnum source_op,
                                                       int source_no) {
diff --git a/riscv/riscv64gzb_encoding.h b/riscv/riscv64gzb_encoding.h
index 8fc2b3b..651d49d 100644
--- a/riscv/riscv64gzb_encoding.h
+++ b/riscv/riscv64gzb_encoding.h
@@ -37,30 +37,30 @@
 class RiscV64GZBEncoding : public RiscV64GZBEncodingBase,
                            public RiscVEncodingCommon {
  public:
-  explicit RiscV64GZBEncoding(RiscVState *state);
+  explicit RiscV64GZBEncoding(RiscVState* state);
   ~RiscV64GZBEncoding() override;
 
   void ParseInstruction(uint32_t inst_word);
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -69,25 +69,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -95,8 +95,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace mpact::sim::riscv::isa64gzb
diff --git a/riscv/riscv64gzb_vec_decoder.cc b/riscv/riscv64gzb_vec_decoder.cc
index 6805732..a578f89 100644
--- a/riscv/riscv64gzb_vec_decoder.cc
+++ b/riscv/riscv64gzb_vec_decoder.cc
@@ -34,8 +34,8 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
-RiscV64GZBVecDecoder::RiscV64GZBVecDecoder(RiscVState *state,
-                                           util::MemoryInterface *memory)
+RiscV64GZBVecDecoder::RiscV64GZBVecDecoder(RiscVState* state,
+                                           util::MemoryInterface* memory)
     : state_(state),
       memory_(memory),
       inst_db_(state_->db_factory()->Allocate<uint32_t>(1)) {
@@ -55,17 +55,17 @@
 
 RiscV64GZBVecDecoder::~RiscV64GZBVecDecoder() { inst_db_->DecRef(); }
 
-generic::Instruction *RiscV64GZBVecDecoder::DecodeInstruction(
+generic::Instruction* RiscV64GZBVecDecoder::DecodeInstruction(
     uint64_t address) {
   // First check that the address is aligned properly. If not, create and return
   // an instruction object that will raise an exception.
   if (address & 0x1) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(1);
     inst->SetDisassemblyString("Misaligned instruction address");
     inst->set_opcode(*isa64gvzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAddressMisaligned, address ^ 0x1,
                    inst);
@@ -76,12 +76,12 @@
   // If the address is greater than the max address, return an instruction
   // object that will raise an exception.
   if (address > state_->max_physical_address()) {
-    auto *inst = new generic::Instruction(address, state_);
+    auto* inst = new generic::Instruction(address, state_);
     inst->set_size(0);
     inst->SetDisassemblyString("Instruction access fault");
     inst->set_opcode(*isa64gvzb::OpcodeEnum::kNone);
     inst->set_address(address);
-    inst->set_semantic_function([this, address](generic::Instruction *inst) {
+    inst->set_semantic_function([this, address](generic::Instruction* inst) {
       state_->Trap(/*is_interrupt*/ false, address,
                    *ExceptionCode::kInstructionAccessFault, address, nullptr);
     });
@@ -95,7 +95,7 @@
 
   // Call the isa decoder to obtain a new instruction object for the instruction
   // word that was parsed above.
-  auto *instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
+  auto* instruction = riscv_isa_->Decode(address, riscv_encoding_.get());
   return instruction;
 }
 
diff --git a/riscv/riscv64gzb_vec_decoder.h b/riscv/riscv64gzb_vec_decoder.h
index b828271..723defb 100644
--- a/riscv/riscv64gzb_vec_decoder.h
+++ b/riscv/riscv64gzb_vec_decoder.h
@@ -41,7 +41,7 @@
 class RV64GVZBIsaFactory : public isa64gvzb::RiscV64GVZBInstructionSetFactory {
  public:
   std::unique_ptr<isa64gvzb::Riscv64gvzbSlot> CreateRiscv64gvzbSlot(
-      ArchState *state) override {
+      ArchState* state) override {
     return std::make_unique<isa64gvzb::Riscv64gvzbSlot>(state);
   }
 };
@@ -54,28 +54,28 @@
   using SlotEnum = isa64gvzb::SlotEnum;
   using OpcodeEnum = isa64gvzb::OpcodeEnum;
 
-  RiscV64GZBVecDecoder(RiscVState *state, util::MemoryInterface *memory);
+  RiscV64GZBVecDecoder(RiscVState* state, util::MemoryInterface* memory);
   RiscV64GZBVecDecoder() = delete;
   ~RiscV64GZBVecDecoder() override;
 
   // This will always return a valid instruction that can be executed. In the
   // case of a decode error, the semantic function in the instruction object
   // instance will raise an internal simulator error when executed.
-  generic::Instruction *DecodeInstruction(uint64_t address) override;
+  generic::Instruction* DecodeInstruction(uint64_t address) override;
   // Return the number of opcodes supported by this decoder.
   int GetNumOpcodes() const override { return *OpcodeEnum::kPastMaxValue; }
   // Return the name of the opcode at the given index.
-  const char *GetOpcodeName(int index) const override {
+  const char* GetOpcodeName(int index) const override {
     return isa64gvzb::kOpcodeNames[index];
   }
 
  private:
-  RiscVState *const state_;
-  util::MemoryInterface *const memory_;
+  RiscVState* const state_;
+  util::MemoryInterface* const memory_;
 
   // Buffer used to load instructions from memory. Re-used for each instruction
   // word.
-  generic::DataBuffer *const inst_db_;
+  generic::DataBuffer* const inst_db_;
 
   std::unique_ptr<generic::ProgramError> decode_error_;
   std::unique_ptr<isa64gvzb::RiscV64GZBVecEncoding> riscv_encoding_;
diff --git a/riscv/riscv64gzb_vec_encoding.cc b/riscv/riscv64gzb_vec_encoding.cc
index 43e913a..cdcc30b 100644
--- a/riscv/riscv64gzb_vec_encoding.cc
+++ b/riscv/riscv64gzb_vec_encoding.cc
@@ -37,7 +37,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: clang-tidy false positive.
 
-RiscV64GZBVecEncoding::RiscV64GZBVecEncoding(RiscVState *state)
+RiscV64GZBVecEncoding::RiscV64GZBVecEncoding(RiscVState* state)
     : state_(state),
       inst_word_(0),
       opcode_(OpcodeEnum::kNone),
@@ -110,7 +110,7 @@
   format_ = format;
 }
 
-ResourceOperandInterface *RiscV64GZBVecEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* RiscV64GZBVecEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   int index = static_cast<int>(resource);
@@ -122,10 +122,10 @@
   return (iter->second)(begin, end);
 }
 
-ResourceOperandInterface *RiscV64GZBVecEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* RiscV64GZBVecEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   if (resource_vec.empty()) return nullptr;
-  auto *resource_set = resource_pool_->CreateResourceSet();
+  auto* resource_set = resource_pool_->CreateResourceSet();
   for (auto resource_enum : resource_vec) {
     int index = static_cast<int>(resource_enum);
     auto iter = simple_resource_getters_.find(index);
@@ -133,19 +133,19 @@
       LOG(WARNING) << "No getter for simple resource " << index;
       continue;
     }
-    auto *resource = (iter->second)();
+    auto* resource = (iter->second)();
     auto status = resource_set->AddResource(resource);
     if (!status.ok()) {
       LOG(ERROR) << "Unable to add resource to resource set ("
                  << static_cast<int>(resource_enum) << ")";
     }
   }
-  auto *op = new generic::SimpleResourceOperand(resource_set, end,
+  auto* op = new generic::SimpleResourceOperand(resource_set, end,
                                                 resource_delay_line_);
   return op;
 }
 
-DestinationOperandInterface *RiscV64GZBVecEncoding::GetDestination(
+DestinationOperandInterface* RiscV64GZBVecEncoding::GetDestination(
     SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no,
     int latency) {
   int index = static_cast<int>(dest_op);
@@ -159,7 +159,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *RiscV64GZBVecEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* RiscV64GZBVecEncoding::GetSource(SlotEnum, int,
                                                          OpcodeEnum opcode,
                                                          SourceOpEnum source_op,
                                                          int source_no) {
diff --git a/riscv/riscv64gzb_vec_encoding.h b/riscv/riscv64gzb_vec_encoding.h
index 8966e99..9dc5c26 100644
--- a/riscv/riscv64gzb_vec_encoding.h
+++ b/riscv/riscv64gzb_vec_encoding.h
@@ -37,30 +37,30 @@
 class RiscV64GZBVecEncoding : public RiscV64GVZBEncodingBase,
                               public RiscVEncodingCommon {
  public:
-  explicit RiscV64GZBVecEncoding(RiscVState *state);
+  explicit RiscV64GZBVecEncoding(RiscVState* state);
   ~RiscV64GZBVecEncoding() override;
 
   void ParseInstruction(uint32_t inst_word);
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -69,25 +69,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -95,8 +95,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace mpact::sim::riscv::isa64gvzb
diff --git a/riscv/riscv_a_instructions.cc b/riscv/riscv_a_instructions.cc
index f11dab2..f03565c 100644
--- a/riscv/riscv_a_instructions.cc
+++ b/riscv/riscv_a_instructions.cc
@@ -36,10 +36,10 @@
 
 // Helper function for the atomic memory operation semantic functions.
 template <typename T>
-static inline void AInstructionHelper(Instruction *inst, Operation op,
+static inline void AInstructionHelper(Instruction* inst, Operation op,
                                       bool has_store_value) {
-  auto *state = static_cast<RiscVState *>(inst->state());
-  auto *atomic = state->atomic_memory();
+  auto* state = static_cast<RiscVState*>(inst->state());
+  auto* atomic = state->atomic_memory();
   // If the atomic memory operation interface is nullptr, this is an illegal
   // instruction.
   if (atomic == nullptr) {
@@ -49,14 +49,14 @@
   }
   // Submit the memory operation.
   auto address = generic::GetInstructionSource<uint64_t>(inst, 0);
-  auto *db = inst->state()->db_factory()->Allocate<T>(1);
+  auto* db = inst->state()->db_factory()->Allocate<T>(1);
   db->set_latency(0);
   // Only access the operand if there is a value to be read.
   if (has_store_value) {
     db->template Set<T>(0, generic::GetInstructionSource<T>(inst, 1));
   }
   // This transfers ownership of db to context. Don't DecRef.
-  auto *context = new LoadContext(db);
+  auto* context = new LoadContext(db);
   auto status = state->atomic_memory()->PerformMemoryOp(address, op, db,
                                                         inst->child(), context);
   // If the operation is unimplemented, this is an illegal instruction.
@@ -68,112 +68,112 @@
   context->DecRef();
 }
 
-void ALrw(Instruction *instruction) {
+void ALrw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kLoadLinked,
                                /*has_store_value*/ false);
 }
 
-void AScw(Instruction *instruction) {
+void AScw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kStoreConditional,
                                /*has_store_value*/ true);
 }
 
-void AAmoswapw(Instruction *instruction) {
+void AAmoswapw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicSwap,
                                /*has_store_value*/ true);
 }
 
-void AAmoaddw(Instruction *instruction) {
+void AAmoaddw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicAdd,
                                /*has_store_value*/ true);
 }
 
-void AAmoandw(Instruction *instruction) {
+void AAmoandw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicAnd,
                                /*has_store_value*/ true);
 }
 
-void AAmoorw(Instruction *instruction) {
+void AAmoorw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicOr,
                                /*has_store_value*/ true);
 }
 
-void AAmoxorw(Instruction *instruction) {
+void AAmoxorw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicXor,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxw(Instruction *instruction) {
+void AAmomaxw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMax,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxuw(Instruction *instruction) {
+void AAmomaxuw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMaxu,
                                /*has_store_value*/ true);
 }
 
-void AAmominw(Instruction *instruction) {
+void AAmominw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMin,
                                /*has_store_value*/ true);
 }
 
-void AAmominuw(Instruction *instruction) {
+void AAmominuw(Instruction* instruction) {
   AInstructionHelper<uint32_t>(instruction, Operation::kAtomicMinu,
                                /*has_store_value*/ true);
 }
 
-void ALrd(Instruction *instruction) {
+void ALrd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kLoadLinked,
                                /*has_store_value*/ false);
 }
 
-void AScd(Instruction *instruction) {
+void AScd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kStoreConditional,
                                /*has_store_value*/ true);
 }
 
-void AAmoswapd(Instruction *instruction) {
+void AAmoswapd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicSwap,
                                /*has_store_value*/ true);
 }
 
-void AAmoaddd(Instruction *instruction) {
+void AAmoaddd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicAdd,
                                /*has_store_value*/ true);
 }
 
-void AAmoandd(Instruction *instruction) {
+void AAmoandd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicAnd,
                                /*has_store_value*/ true);
 }
 
-void AAmoord(Instruction *instruction) {
+void AAmoord(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicOr,
                                /*has_store_value*/ true);
 }
 
-void AAmoxord(Instruction *instruction) {
+void AAmoxord(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicXor,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxd(Instruction *instruction) {
+void AAmomaxd(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicMax,
                                /*has_store_value*/ true);
 }
 
-void AAmomaxud(Instruction *instruction) {
+void AAmomaxud(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicMaxu,
                                /*has_store_value*/ true);
 }
 
-void AAmomind(Instruction *instruction) {
+void AAmomind(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicMin,
                                /*has_store_value*/ true);
 }
 
-void AAmominud(Instruction *instruction) {
+void AAmominud(Instruction* instruction) {
   AInstructionHelper<uint64_t>(instruction, Operation::kAtomicMinu,
                                /*has_store_value*/ true);
 }
diff --git a/riscv/riscv_a_instructions.h b/riscv/riscv_a_instructions.h
index 79b7888..90ef309 100644
--- a/riscv/riscv_a_instructions.h
+++ b/riscv/riscv_a_instructions.h
@@ -32,46 +32,46 @@
 // memory to access, the second is the acquire bit, and the third, the release
 // bit. The instruction has a single destination operand which is the register
 // to write the result to.
-void ALrw(Instruction *instruction);
+void ALrw(Instruction* instruction);
 // The following instructions take 4 source operands and one destination
 // operand. The first source is the register holding the address of the
 // memory to access, the second is the register value used in the memory
 // operation (to store, swap, etc), the third is the acquire bit, and the
 // fourth, the release bit. The instruction has a single destination operand
 // which is the register to write the result to.
-void AScw(Instruction *instruction);
-void AAmoswapw(Instruction *instruction);
-void AAmoaddw(Instruction *instruction);
-void AAmoandw(Instruction *instruction);
-void AAmoorw(Instruction *instruction);
-void AAmoxorw(Instruction *instruction);
-void AAmomaxw(Instruction *instruction);
-void AAmomaxuw(Instruction *instruction);
-void AAmominw(Instruction *instruction);
-void AAmominuw(Instruction *instruction);
+void AScw(Instruction* instruction);
+void AAmoswapw(Instruction* instruction);
+void AAmoaddw(Instruction* instruction);
+void AAmoandw(Instruction* instruction);
+void AAmoorw(Instruction* instruction);
+void AAmoxorw(Instruction* instruction);
+void AAmomaxw(Instruction* instruction);
+void AAmomaxuw(Instruction* instruction);
+void AAmominw(Instruction* instruction);
+void AAmominuw(Instruction* instruction);
 
 // The following instruction takes 3 source operands and one destination
 // operand. The first source is the register holding the address of the
 // memory to access, the second is the acquire bit, and the third, the release
 // bit. The instruction has a single destination operand which is the register
 // to write the result to.
-void ALrd(Instruction *instruction);
+void ALrd(Instruction* instruction);
 // The following instructions take 4 source operands and one destination
 // operand. The first source is the register holding the address of the
 // memory to access, the second is the register value used in the memory
 // operation (to store, swap, etc), the third is the acquire bit, and the
 // fourth, the release bit. The instruction has a single destination operand
 // which is the register to write the result to.
-void AScd(Instruction *instruction);
-void AAmoswapd(Instruction *instruction);
-void AAmoaddd(Instruction *instruction);
-void AAmoandd(Instruction *instruction);
-void AAmoord(Instruction *instruction);
-void AAmoxord(Instruction *instruction);
-void AAmomaxd(Instruction *instruction);
-void AAmomaxud(Instruction *instruction);
-void AAmomind(Instruction *instruction);
-void AAmominud(Instruction *instruction);
+void AScd(Instruction* instruction);
+void AAmoswapd(Instruction* instruction);
+void AAmoaddd(Instruction* instruction);
+void AAmoandd(Instruction* instruction);
+void AAmoord(Instruction* instruction);
+void AAmoxord(Instruction* instruction);
+void AAmomaxd(Instruction* instruction);
+void AAmomaxud(Instruction* instruction);
+void AAmomind(Instruction* instruction);
+void AAmominud(Instruction* instruction);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_action_point_memory_interface.cc b/riscv/riscv_action_point_memory_interface.cc
index 01d9aa3..f85c93e 100644
--- a/riscv/riscv_action_point_memory_interface.cc
+++ b/riscv/riscv_action_point_memory_interface.cc
@@ -23,7 +23,7 @@
 namespace mpact::sim::riscv {
 
 RiscVActionPointMemoryInterface::RiscVActionPointMemoryInterface(
-    MemoryInterface *memory, InvalidateFcn invalidate_fcn)
+    MemoryInterface* memory, InvalidateFcn invalidate_fcn)
     : memory_(memory), invalidate_fcn_(std::move(invalidate_fcn)) {
   // Allocate two data buffers (32 and 16 bit) once, so we don't have to
   // do it every time we access breakpoint instructions.
@@ -34,7 +34,7 @@
 RiscVActionPointMemoryInterface::~RiscVActionPointMemoryInterface() {
   if (db4_ != nullptr) db4_->DecRef();
   if (db2_ != nullptr) db2_->DecRef();
-  for (auto &[unused, inst_info_ptr] : instruction_map_) {
+  for (auto& [unused, inst_info_ptr] : instruction_map_) {
     delete inst_info_ptr;
   }
   instruction_map_.clear();
@@ -74,7 +74,7 @@
           "Invalid instruction size: ", size, " at ", absl::Hex(address)));
     }
     if (size == 2) instruction_word &= 0xffff;
-    auto *inst_info = new InstructionInfo;
+    auto* inst_info = new InstructionInfo;
     inst_info->og_instruction_word = instruction_word;
     inst_info->size = size;
     it = instruction_map_.insert(std::make_pair(address, inst_info)).first;
diff --git a/riscv/riscv_action_point_memory_interface.h b/riscv/riscv_action_point_memory_interface.h
index 78bbdfe..87ca22c 100644
--- a/riscv/riscv_action_point_memory_interface.h
+++ b/riscv/riscv_action_point_memory_interface.h
@@ -46,7 +46,7 @@
   // The constructor takes a pointer to the memory interface through which
   // instructions can be read and written,and a function to invalidate the
   // decoding of an instruction.
-  RiscVActionPointMemoryInterface(MemoryInterface *memory,
+  RiscVActionPointMemoryInterface(MemoryInterface* memory,
                                   InvalidateFcn invalidate_fcn);
   ~RiscVActionPointMemoryInterface() override;
 
@@ -70,12 +70,12 @@
   // Data buffer factory and two data buffer pointers to use for reading and
   // writing instructions.
   DataBufferFactory db_factory_;
-  DataBuffer *db4_ = nullptr;
-  DataBuffer *db2_ = nullptr;
+  DataBuffer* db4_ = nullptr;
+  DataBuffer* db2_ = nullptr;
   // Maps from address to information about the instruction.
-  absl::flat_hash_map<uint64_t, InstructionInfo *> instruction_map_;
+  absl::flat_hash_map<uint64_t, InstructionInfo*> instruction_map_;
   // Interface to program memory.
-  MemoryInterface *memory_;
+  MemoryInterface* memory_;
   // Function to be called to invalidate any stored decoding of an instruction.
   InvalidateFcn invalidate_fcn_;
 };
diff --git a/riscv/riscv_arm_semihost.cc b/riscv/riscv_arm_semihost.cc
index 1d1523e..d950652 100644
--- a/riscv/riscv_arm_semihost.cc
+++ b/riscv/riscv_arm_semihost.cc
@@ -38,8 +38,8 @@
 namespace riscv {
 
 RiscVArmSemihost::RiscVArmSemihost(BitWidth bit_width,
-                                   util::MemoryInterface *i_memory_if,
-                                   util::MemoryInterface *d_memory_if)
+                                   util::MemoryInterface* i_memory_if,
+                                   util::MemoryInterface* d_memory_if)
     : i_memory_if_(i_memory_if),
       d_memory_if_(d_memory_if),
       // Put the functions that implement the different semihosting operations
@@ -102,7 +102,7 @@
   db4_->DecRef();
 }
 
-bool RiscVArmSemihost::IsSemihostingCall(const Instruction *inst) {
+bool RiscVArmSemihost::IsSemihostingCall(const Instruction* inst) {
   if (inst == nullptr) return false;
   // Load the instruction words on either side of the ebreak instruction.
   uint64_t address = inst->address() - 4;
@@ -116,15 +116,15 @@
   return true;
 }
 
-void RiscVArmSemihost::OnEBreak(const Instruction *inst) {
+void RiscVArmSemihost::OnEBreak(const Instruction* inst) {
   if (!IsSemihostingCall(inst)) return;
 
   // Handle the semihosting call.
   auto registers = inst->state()->registers();
   auto iter = registers->find(kA0Name);
-  auto *a0 = iter == registers->end() ? nullptr : iter->second;
+  auto* a0 = iter == registers->end() ? nullptr : iter->second;
   iter = registers->find(kA1Name);
-  auto *a1 = iter == registers->end() ? nullptr : iter->second;
+  auto* a1 = iter == registers->end() ? nullptr : iter->second;
   if ((a0 == nullptr) || (a1 == nullptr)) {
     LOG(ERROR) << "Failed to fetch semihost argument registers";
   }
@@ -170,7 +170,7 @@
   }
 }
 
-absl::Status RiscVArmSemihost::SysClose(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysClose(uint64_t parameter, uint64_t* ret_val) {
   // Load the file descriptor from the parameter block.
   d_memory_if_->Load(parameter, db1_, nullptr, nullptr);
   int target_fd = is_32_bit_ ? static_cast<int>(db1_->Get<uint32_t>(0))
@@ -201,26 +201,26 @@
 }
 
 // Currently not implemented, will implement once there is need for it.
-absl::Status RiscVArmSemihost::SysClock(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysClock(uint64_t parameter, uint64_t* ret_val) {
   return absl::UnimplementedError("SysClock not implemented");
   // TODO: Complete implementation.
 }
 
 // Currently not implemented, will implement once there is need for it.
 absl::Status RiscVArmSemihost::SysElapsed(uint64_t parameter,
-                                          uint64_t *ret_val) {
+                                          uint64_t* ret_val) {
   return absl::UnimplementedError("SysElapsed not implemented");
   // TODO: Complete implementation.
 }
 
 // Return the value of the simulated errno.
-absl::Status RiscVArmSemihost::SysErrno(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysErrno(uint64_t parameter, uint64_t* ret_val) {
   *ret_val = sys_errno_;
   return absl::OkStatus();
 }
 
 // Exception notification. The program should be terminated.
-absl::Status RiscVArmSemihost::SysException(uint64_t parameter, uint64_t *) {
+absl::Status RiscVArmSemihost::SysException(uint64_t parameter, uint64_t*) {
   // In gcc it seems like the parameter value is passed in the parameter
   // register for RV32, but stored in memory, and then a pointer passed in the
   // parameter register for RV64. A bit odd...
@@ -247,7 +247,7 @@
 }
 
 // Return the length of a file given by the file descriptor.
-absl::Status RiscVArmSemihost::SysFlen(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysFlen(uint64_t parameter, uint64_t* ret_val) {
   // Load the targeted file descriptor.
   d_memory_if_->Load(parameter, db1_, nullptr, nullptr);
   int target_fd = is_32_bit_ ? static_cast<int>(db1_->Get<uint32_t>(0))
@@ -273,7 +273,7 @@
 
 // Currently unimplemented. Will implement if there is a demand.
 absl::Status RiscVArmSemihost::SysGetCmdline(uint64_t parameter,
-                                             uint64_t *ret_val) {
+                                             uint64_t* ret_val) {
   d_memory_if_->Load(parameter, db2_, nullptr, nullptr);
   uint64_t buffer_address = is_32_bit_
                                 ? static_cast<uint64_t>(db2_->Get<uint32_t>(0))
@@ -284,7 +284,7 @@
     *ret_val = -1ULL;
     return absl::OkStatus();
   }
-  auto *db = db_factory_.Allocate<uint8_t>(cmd_line_.size() + 1);
+  auto* db = db_factory_.Allocate<uint8_t>(cmd_line_.size() + 1);
   std::memcpy(db->raw_ptr(), cmd_line_.c_str(), cmd_line_.size());
   db->Set<uint8_t>(cmd_line_.size(), 0);
   d_memory_if_->Store(buffer_address, db);
@@ -301,13 +301,13 @@
 
 // Returns 0 information indicating that the call doesn't provide this info.
 absl::Status RiscVArmSemihost::SysHeapInfo(uint64_t parameter,
-                                           uint64_t *ret_val) {
+                                           uint64_t* ret_val) {
   d_memory_if_->Load(parameter, db1_, nullptr, nullptr);
   uint64_t block_address = is_32_bit_
                                ? static_cast<int>(db1_->Get<uint32_t>(0))
                                : static_cast<int>(db1_->Get<uint64_t>(0));
   // Return all zeros.
-  auto *db = db_factory_.Allocate<uint32_t>(4);
+  auto* db = db_factory_.Allocate<uint32_t>(4);
   d_memory_if_->Load(block_address, db, nullptr, nullptr);
   db->Set<uint32_t>(0, 0);
   db->Set<uint32_t>(1, 0);
@@ -321,13 +321,13 @@
 // This function is not implemented for now. Will look into it if there is
 // demand.
 absl::Status RiscVArmSemihost::SysIsError(uint64_t parameter,
-                                          uint64_t *ret_val) {
+                                          uint64_t* ret_val) {
   return absl::UnimplementedError("SysGetCmdline not implemented");
   // TODO: Complete implementation.
 }
 
 // Check if the fd is a tty.
-absl::Status RiscVArmSemihost::SysIsTty(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysIsTty(uint64_t parameter, uint64_t* ret_val) {
   // Load the target file descriptor.
   d_memory_if_->Load(parameter, db1_, nullptr, nullptr);
   int target_fd = is_32_bit_ ? static_cast<int>(db1_->Get<uint32_t>(0))
@@ -349,7 +349,7 @@
 }
 
 // Open a file, return the file descriptor if successful.
-absl::Status RiscVArmSemihost::SysOpen(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysOpen(uint64_t parameter, uint64_t* ret_val) {
   // Load the parameter block consisiting of pointer to a string, the file open
   // mode, and the length of the string.
   d_memory_if_->Load(parameter, db3_, nullptr, nullptr);
@@ -365,10 +365,9 @@
   // a string variable with it.
   std::string file_name;
   if (file_name_len > 0) {
-    auto *db_c = db_factory_.Allocate<uint8_t>(file_name_len);
+    auto* db_c = db_factory_.Allocate<uint8_t>(file_name_len);
     d_memory_if_->Load(string_address, db_c, nullptr, nullptr);
-    file_name =
-        std::string(static_cast<char *>(db_c->raw_ptr()), file_name_len);
+    file_name = std::string(static_cast<char*>(db_c->raw_ptr()), file_name_len);
     db_c->DecRef();
   }
   // If the name is ":tt" then it's either cin or cout depending on the mode.
@@ -402,7 +401,7 @@
   return absl::OkStatus();
 }
 
-absl::Status RiscVArmSemihost::SysRead(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysRead(uint64_t parameter, uint64_t* ret_val) {
   // Load the parameter block, consisting of the target file descriptor, the
   // target buffer address, and buffer length.
   d_memory_if_->Load(parameter, db3_, nullptr, nullptr);
@@ -421,7 +420,7 @@
   }
   auto host_fd = iter->second;
   // Allocate a data buffer sufficient for the target buffer length.
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   // Read from the file/
   int res = read(host_fd, db->raw_ptr(), length);
   *ret_val = static_cast<uint64_t>(res);
@@ -436,25 +435,25 @@
 }
 
 // Read a byte from the debug console. This is not implemented for now.
-absl::Status RiscVArmSemihost::SysReadc(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysReadc(uint64_t parameter, uint64_t* ret_val) {
   return absl::UnimplementedError("SysReadc not implemented");
   // TODO: Complete implementation.
 }
 
 // Remove a file from the host file system. This will not be implemented.
 absl::Status RiscVArmSemihost::SysRemove(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   return absl::UnimplementedError("SysRemove not implemented");
 }
 
 // Rename a file in the host file system. This will not be implemented.
 absl::Status RiscVArmSemihost::SysRename(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   return absl::UnimplementedError("SysRename not implemented");
 }
 
 // Seek in the file specified by the target file descriptor.
-absl::Status RiscVArmSemihost::SysSeek(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysSeek(uint64_t parameter, uint64_t* ret_val) {
   // Load the parameters consisting of the target fd and the desired seek
   // offset.
   d_memory_if_->Load(parameter, db2_, nullptr, nullptr);
@@ -483,27 +482,27 @@
 
 // Execute a command in the shell of the host. This will not be implemented.
 absl::Status RiscVArmSemihost::SysSystem(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   return absl::UnimplementedError("SysSystem not implemented");
 }
 
 // Return the system tick frequency. For now just return -1 to indicate that
 // this call is not fully supported.
 absl::Status RiscVArmSemihost::SysTickFreq(uint64_t parameter,
-                                           uint64_t *ret_val) {
+                                           uint64_t* ret_val) {
   *ret_val = -1ULL;
   return absl::OkStatus();
 }
 
 // Return unix time in seconds.
-absl::Status RiscVArmSemihost::SysTime(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysTime(uint64_t parameter, uint64_t* ret_val) {
   *ret_val = time(nullptr);
   return absl::OkStatus();
 }
 
 // Return a temporary file name.
 absl::Status RiscVArmSemihost::SysTmpnam(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   // Load parameters consisting of a pointer to a buffer, an int (0-255) that
   // is a target identifier for this filename, and the length of the buffer.
   d_memory_if_->Load(parameter, db3_, nullptr, nullptr);
@@ -526,14 +525,14 @@
   }
   // Allocate a data buffer and call tmpnam, then write the name to the buffer.
   auto tmpnam_db = db_factory_.Allocate<uint8_t>(length);
-  tmpnam(static_cast<char *>(tmpnam_db->raw_ptr()));
+  tmpnam(static_cast<char*>(tmpnam_db->raw_ptr()));
   d_memory_if_->Store(buffer_address, tmpnam_db);
   tmpnam_db->DecRef();
   return absl::OkStatus();
 }
 
 // Write data to a file.
-absl::Status RiscVArmSemihost::SysWrite(uint64_t parameter, uint64_t *ret_val) {
+absl::Status RiscVArmSemihost::SysWrite(uint64_t parameter, uint64_t* ret_val) {
   // Load parameters consisting of target fd, target buffer address, and
   // length.
   d_memory_if_->Load(parameter, db3_, nullptr, nullptr);
@@ -553,7 +552,7 @@
   auto host_fd = iter->second;
   // Allocate the data buffer necessary to read the data to be written to the
   // file.
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   d_memory_if_->Load(buffer_address, db, nullptr, nullptr);
   // Write the data to the file.
   int res = write(host_fd, db->raw_ptr(), length);
@@ -568,14 +567,14 @@
 
 // Write a byte to the degbug console. This is not implemented for now.
 absl::Status RiscVArmSemihost::SysWritec(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   return absl::UnimplementedError("SysWritec not implemented");
 }
 
 // Write a null terminated string to the debug console. This is not implemented
 // for now.
 absl::Status RiscVArmSemihost::SysWrite0(uint64_t parameter,
-                                         uint64_t *ret_val) {
+                                         uint64_t* ret_val) {
   return absl::UnimplementedError("SysWrite0 not implemented");
 }
 
diff --git a/riscv/riscv_arm_semihost.h b/riscv/riscv_arm_semihost.h
index 39c3bc0..cbe30fd 100644
--- a/riscv/riscv_arm_semihost.h
+++ b/riscv/riscv_arm_semihost.h
@@ -61,21 +61,21 @@
   static constexpr char kA1Name[] = "x11";  // Also known as "a1".
 
   // Constructor/destructor.
-  RiscVArmSemihost(BitWidth bit_width, util::MemoryInterface *i_memory_if,
-                   util::MemoryInterface *d_memory_if);
+  RiscVArmSemihost(BitWidth bit_width, util::MemoryInterface* i_memory_if,
+                   util::MemoryInterface* d_memory_if);
   RiscVArmSemihost() = delete;
-  RiscVArmSemihost(const RiscVArmSemihost &) = delete;
+  RiscVArmSemihost(const RiscVArmSemihost&) = delete;
   ~RiscVArmSemihost();
 
   // If the instruction is a semihosting call, execute the requested function.
-  void OnEBreak(const Instruction *inst);
+  void OnEBreak(const Instruction* inst);
   // Return true if the instruction is a semihosting call.
-  bool IsSemihostingCall(const Instruction *inst);
+  bool IsSemihostingCall(const Instruction* inst);
   // Set the command line string.
-  void SetCmdLine(const std::vector<char *> &argv) {
+  void SetCmdLine(const std::vector<char*>& argv) {
     cmd_line_.clear();
     std::string sep;
-    for (const auto &arg : argv) {
+    for (const auto& arg : argv) {
       absl::StrAppend(&cmd_line_, sep, arg);
       sep = " ";
     }
@@ -88,7 +88,7 @@
   }
 
  private:
-  using SemihostOperation = std::function<absl::Status(uint64_t, uint64_t *)>;
+  using SemihostOperation = std::function<absl::Status(uint64_t, uint64_t*)>;
 
   std::function<void()> exit_callback_;
   std::function<void(uint64_t)> exception_callback_;
@@ -122,29 +122,29 @@
   static constexpr int kSysWrite0 = 0x04;
 
   // Functions that implement the semihosting operations.
-  absl::Status SysClose(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysClock(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysElapsed(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysErrno(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysException(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysFlen(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysGetCmdline(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysHeapInfo(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysIsError(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysIsTty(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysOpen(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysRead(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysReadc(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysRemove(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysRename(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysSeek(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysSystem(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysTickFreq(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysTime(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysTmpnam(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysWrite(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysWritec(uint64_t parameter, uint64_t *ret_val);
-  absl::Status SysWrite0(uint64_t parameter, uint64_t *ret_val);
+  absl::Status SysClose(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysClock(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysElapsed(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysErrno(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysException(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysFlen(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysGetCmdline(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysHeapInfo(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysIsError(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysIsTty(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysOpen(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysRead(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysReadc(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysRemove(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysRename(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysSeek(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysSystem(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysTickFreq(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysTime(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysTmpnam(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysWrite(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysWritec(uint64_t parameter, uint64_t* ret_val);
+  absl::Status SysWrite0(uint64_t parameter, uint64_t* ret_val);
 
   bool is_32_bit_;
   int sys_errno_ = 0;
@@ -152,14 +152,14 @@
   // Data buffers used by some of the operations. Giving them lifetime of the
   // semihosting instance saves some on allocating and freeing them for each
   // operation.
-  generic::DataBuffer *db_inst_;  // Instruction word(s) data buffer.
-  generic::DataBuffer *db1_;      // 1 word data buffer.
-  generic::DataBuffer *db2_;      // 2 word data buffer.
-  generic::DataBuffer *db3_;      // 3 word data buffer.
-  generic::DataBuffer *db4_;      // 4 word data buffer.
+  generic::DataBuffer* db_inst_;  // Instruction word(s) data buffer.
+  generic::DataBuffer* db1_;      // 1 word data buffer.
+  generic::DataBuffer* db2_;      // 2 word data buffer.
+  generic::DataBuffer* db3_;      // 3 word data buffer.
+  generic::DataBuffer* db4_;      // 4 word data buffer.
   // Memory interfaces to use to access instruction and data memory.
-  util::MemoryInterface *i_memory_if_;
-  util::MemoryInterface *d_memory_if_;
+  util::MemoryInterface* i_memory_if_;
+  util::MemoryInterface* d_memory_if_;
   // Map from opcode to semihosting function.
   absl::flat_hash_map<uint64_t, SemihostOperation> semihost_operations_;
   // Map of target file descriptors to host file descriptors.
diff --git a/riscv/riscv_bin_setters.cc b/riscv/riscv_bin_setters.cc
index 6d6684d..721c345 100644
--- a/riscv/riscv_bin_setters.cc
+++ b/riscv/riscv_bin_setters.cc
@@ -53,8 +53,8 @@
     "^\\s*(%[a-zA-Z0-9_]+)?\\s*\\(?([a-zA-Z_][^)]+)\\)?\\s*$");
 
 absl::Status RelocateAddiIImm12(uint64_t address, absl::string_view text,
-                                ResolverInterface *resolver,
-                                std::vector<RelocationInfo> &relocations) {
+                                ResolverInterface* resolver,
+                                std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
@@ -74,8 +74,8 @@
 }
 
 absl::Status RelocateJJImm20(uint64_t address, absl::string_view text,
-                             ResolverInterface *resolver,
-                             std::vector<RelocationInfo> &relocations) {
+                             ResolverInterface* resolver,
+                             std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
@@ -84,8 +84,8 @@
 }
 
 absl::Status RelocateJrJImm12(uint64_t address, absl::string_view text,
-                              ResolverInterface *resolver,
-                              std::vector<RelocationInfo> &relocations) {
+                              ResolverInterface* resolver,
+                              std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
@@ -96,8 +96,8 @@
 }
 
 absl::Status RelocateLuiUImm20(uint64_t address, absl::string_view text,
-                               ResolverInterface *resolver,
-                               std::vector<RelocationInfo> &relocations) {
+                               ResolverInterface* resolver,
+                               std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
@@ -106,8 +106,8 @@
 }
 
 absl::Status RelocateSdSImm12(uint64_t address, absl::string_view text,
-                              ResolverInterface *resolver,
-                              std::vector<RelocationInfo> &relocations) {
+                              ResolverInterface* resolver,
+                              std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
@@ -127,8 +127,8 @@
 }
 
 absl::Status RelocateAuipcUImm20(uint64_t address, absl::string_view text,
-                                 ResolverInterface *resolver,
-                                 std::vector<RelocationInfo> &relocations) {
+                                 ResolverInterface* resolver,
+                                 std::vector<RelocationInfo>& relocations) {
   std::string relo;
   std::string sym;
   if (!RE2::FullMatch(text, *kSymRe, &relo, &sym)) return absl::OkStatus();
diff --git a/riscv/riscv_bin_setters.h b/riscv/riscv_bin_setters.h
index 4eb312c..7c4eae7 100644
--- a/riscv/riscv_bin_setters.h
+++ b/riscv/riscv_bin_setters.h
@@ -476,7 +476,7 @@
 // functions, e.g., %hi(<symbol name>).
 template <typename T>
 absl::StatusOr<T> SimpleTextToInt(absl::string_view op_text,
-                                  ResolverInterface *resolver) {
+                                  ResolverInterface* resolver) {
   T value;
   static RE2 hex_re("^\\s*0x([0-9a-fA-F]+)\\s*$");
   static RE2 dec_re("^\\s*(-?[0-9]+)\\s*$");
@@ -518,10 +518,10 @@
 
 // This function adds the bin setters for the source operands to the given map.
 template <typename Enum, typename Map, typename Encoder>
-void AddRiscvSourceOpBinSetters(Map &map) {
+void AddRiscvSourceOpBinSetters(Map& map) {
   Insert(map, *Enum::kAAq,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map = {{"", 0}, {".aq", 1}};
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -532,7 +532,7 @@
          });
   Insert(map, *Enum::kARl,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map = {{"", 0}, {".rl", 1}};
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -543,7 +543,7 @@
          });
   Insert(map, *Enum::kBImm12,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            uint32_t delta = res.value() - address;
@@ -551,7 +551,7 @@
          });
   Insert(map, *Enum::kC3drs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -562,7 +562,7 @@
          });
   Insert(map, *Enum::kC3rs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -573,7 +573,7 @@
          });
   Insert(map, *Enum::kC3rs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -584,14 +584,14 @@
          });
   Insert(map, *Enum::kCSRUimm5,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::IType::InsertIUimm5(res.value(), 0ULL);
          });
   Insert(map, *Enum::kCdrs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -602,7 +602,7 @@
          });
   Insert(map, *Enum::kCrs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -613,7 +613,7 @@
          });
   Insert(map, *Enum::kCrs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -624,7 +624,7 @@
          });
   Insert(map, *Enum::kCsr,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCsrRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -635,7 +635,7 @@
          });
   Insert(map, *Enum::kDrs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -646,7 +646,7 @@
          });
   Insert(map, *Enum::kDrs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -657,7 +657,7 @@
          });
   Insert(map, *Enum::kDrs3,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -668,7 +668,7 @@
          });
   Insert(map, *Enum::kFrs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kFRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -679,7 +679,7 @@
          });
   Insert(map, *Enum::kFrs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kFRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -690,7 +690,7 @@
          });
   Insert(map, *Enum::kFrs3,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kFRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -701,7 +701,7 @@
          });
   Insert(map, *Enum::kICbImm8,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            uint32_t delta = res.value() - address;
@@ -709,56 +709,56 @@
          });
   Insert(map, *Enum::kICiImm6,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertImm6(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiImm612,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertImm18(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiImm6x16,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertCiImm10(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiUimm6,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertUimm6(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiUimm6x4,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertCiImmW(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiUimm6x8,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CI::InsertCiImmD(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICiwUimm8x4,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CIW::InsertCiwImm10(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICjImm11,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            auto delta = res.value() - address;
@@ -766,63 +766,63 @@
          });
   Insert(map, *Enum::kIClUimm5x4,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CL::InsertClImmW(res.value(), 0ULL);
          });
   Insert(map, *Enum::kIClUimm5x8,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CL::InsertClImmD(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICssUimm6x4,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CS::InsertCsImmW(res.value(), 0ULL);
          });
   Insert(map, *Enum::kICssUimm6x8,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::CS::InsertCsImmD(res.value(), 0ULL);
          });
   Insert(map, *Enum::kIImm12,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::IType::InsertImm12(res.value(), 0ULL);
          });
   Insert(map, *Enum::kIUimm5,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::RType::InsertRUimm5(res.value(), 0ULL);
          });
   Insert(map, *Enum::kIUimm6,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::RSType::InsertRUimm6(res.value(), 0ULL);
          });
   Insert(map, *Enum::kJImm12,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::IType::InsertImm12(res.value(), 0ULL);
          });
   Insert(map, *Enum::kJImm20,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<int32_t>(text, resolver);
            if (!res.ok()) return res.status();
            uint32_t delta = res.value() - address;
@@ -831,14 +831,14 @@
          });
   Insert(map, *Enum::kPred,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::Fence::InsertPred(res.value(), 0ULL);
          });
   Insert(map, *Enum::kRd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -849,7 +849,7 @@
          });
   Insert(map, *Enum::kRm,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -860,7 +860,7 @@
          });
   Insert(map, *Enum::kRs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -871,7 +871,7 @@
          });
   Insert(map, *Enum::kRs2,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -882,21 +882,21 @@
          });
   Insert(map, *Enum::kSImm12,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::SType::InsertSImm(res.value(), 0ULL);
          });
   Insert(map, *Enum::kSucc,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::Fence::InsertSucc(res.value(), 0ULL);
          });
   Insert(map, *Enum::kUImm20,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            auto res = SimpleTextToInt<uint32_t>(text, resolver);
            if (!res.ok()) return res.status();
            return Encoder::UType::InsertUImm(res.value(), 0ULL);
@@ -906,10 +906,10 @@
 // This function adds the destination operand setters for the RiscV ISA to the
 // given map.
 template <typename Enum, typename Map, typename Encoder>
-void AddRiscvDestOpBinSetters(Map &map) {
+void AddRiscvDestOpBinSetters(Map& map) {
   Insert(map, *Enum::kC3drd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -920,7 +920,7 @@
          });
   Insert(map, *Enum::kC3rd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -931,7 +931,7 @@
          });
   Insert(map, *Enum::kC3rs1,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -942,7 +942,7 @@
          });
   Insert(map, *Enum::kCsr,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kCsrRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -953,7 +953,7 @@
          });
   Insert(map, *Enum::kDrd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kDRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -964,7 +964,7 @@
          });
   Insert(map, *Enum::kFrd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kFRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -975,7 +975,7 @@
          });
   Insert(map, *Enum::kRd,
          [](uint64_t address, absl::string_view text,
-            ResolverInterface *resolver) -> absl::StatusOr<uint64_t> {
+            ResolverInterface* resolver) -> absl::StatusOr<uint64_t> {
            static ValueMap map(kRegisterList);
            auto iter = map.find(text);
            if (iter == map.end()) {
@@ -991,23 +991,23 @@
 namespace internal {
 
 absl::Status RelocateAddiIImm12(uint64_t address, absl::string_view text,
-                                ResolverInterface *resolver,
-                                std::vector<RelocationInfo> &relocations);
+                                ResolverInterface* resolver,
+                                std::vector<RelocationInfo>& relocations);
 absl::Status RelocateJJImm20(uint64_t address, absl::string_view text,
-                             ResolverInterface *resolver,
-                             std::vector<RelocationInfo> &relocations);
+                             ResolverInterface* resolver,
+                             std::vector<RelocationInfo>& relocations);
 absl::Status RelocateJrJImm12(uint64_t address, absl::string_view text,
-                              ResolverInterface *resolver,
-                              std::vector<RelocationInfo> &relocations);
+                              ResolverInterface* resolver,
+                              std::vector<RelocationInfo>& relocations);
 absl::Status RelocateLuiUImm20(uint64_t address, absl::string_view text,
-                               ResolverInterface *resolver,
-                               std::vector<RelocationInfo> &relocations);
+                               ResolverInterface* resolver,
+                               std::vector<RelocationInfo>& relocations);
 absl::Status RelocateSdSImm12(uint64_t address, absl::string_view text,
-                              ResolverInterface *resolver,
-                              std::vector<RelocationInfo> &relocations);
+                              ResolverInterface* resolver,
+                              std::vector<RelocationInfo>& relocations);
 absl::Status RelocateAuipcUImm20(uint64_t address, absl::string_view text,
-                                 ResolverInterface *resolver,
-                                 std::vector<RelocationInfo> &relocations);
+                                 ResolverInterface* resolver,
+                                 std::vector<RelocationInfo>& relocations);
 
 }  // namespace internal
 
@@ -1015,7 +1015,7 @@
 // the given map. Notice that the key in the map is the tuple consisting of the
 // opcode and the source operand enum values.
 template <typename OpcodeEnum, typename SourceOpEnum, typename Map>
-void AddRiscvSourceOpRelocationSetters(Map &map) {
+void AddRiscvSourceOpRelocationSetters(Map& map) {
   Insert(map, OpcodeEnum::kAddi, SourceOpEnum::kIImm12,
          internal::RelocateAddiIImm12);
   Insert(map, OpcodeEnum::kJal, SourceOpEnum::kJImm20,
diff --git a/riscv/riscv_bitmanip_instructions.cc b/riscv/riscv_bitmanip_instructions.cc
index dda17c2..5fe0fa0 100644
--- a/riscv/riscv_bitmanip_instructions.cc
+++ b/riscv/riscv_bitmanip_instructions.cc
@@ -39,105 +39,105 @@
 constexpr int kXlen = sizeof(UIntReg) * 8;
 
 // Add with shift.
-void RiscVShAdd(const Instruction *instruction) {
+void RiscVShAdd(const Instruction* instruction) {
   auto shift = generic::GetInstructionSource<UIntReg>(instruction, 2);
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [shift](UIntReg a, UIntReg b) { return b + (a << shift); });
 }
 
 // And not.
-void RiscVAndn(const Instruction *instruction) {
+void RiscVAndn(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a & ~b; });
 }
 
 // Or not.
-void RiscVOrn(const Instruction *instruction) {
+void RiscVOrn(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | ~b; });
 }
 
 // Xnor.
-void RiscVXnor(const Instruction *instruction) {
+void RiscVXnor(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return ~(a ^ b); });
 }
 
-void RiscVNot(const generic::Instruction *instruction) {
+void RiscVNot(const generic::Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction,
                                                [](UIntReg a) { return ~a; });
 }
 
 // Count leading zeros.
-void RiscVClz(const Instruction *instruction) {
+void RiscVClz(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::countl_zero(a); });
 }
 
 // Count trailing zeros.
-void RiscVCtz(const Instruction *instruction) {
+void RiscVCtz(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::countr_zero(a); });
 }
 
 // Bit population count.
-void RiscVCpop(const Instruction *instruction) {
+void RiscVCpop(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::popcount(a); });
 }
 
 // Signed max.
-void RiscVMax(const Instruction *instruction) {
+void RiscVMax(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return std::max(a, b); });
 }
 
 // Unsigned max.
-void RiscVMaxu(const Instruction *instruction) {
+void RiscVMaxu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return std::max(a, b); });
 }
 
 // Signed min.
-void RiscVMin(const Instruction *instruction) {
+void RiscVMin(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return std::min(a, b); });
 }
 
 // Unsigned min.
-void RiscVMinu(const Instruction *instruction) {
+void RiscVMinu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return std::min(a, b); });
 }
 
 // Sign extend byte.
-void RiscVSextB(const Instruction *instruction) {
+void RiscVSextB(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, IntReg, int8_t>(
       instruction, [](int8_t a) -> IntReg { return static_cast<IntReg>(a); });
 }
 
 // Sign extend half word.
-void RiscVSextH(const Instruction *instruction) {
+void RiscVSextH(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, IntReg, int16_t>(
       instruction, [](int16_t a) -> IntReg { return static_cast<IntReg>(a); });
 }
 
 // Zero extend half word.
-void RiscVZextH(const Instruction *instruction) {
+void RiscVZextH(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint16_t>(
       instruction,
       [](uint16_t a) -> UIntReg { return static_cast<UIntReg>(a); });
 }
 
 // Zero extend byte.
-void RiscVZextB(const Instruction *instruction) {
+void RiscVZextB(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint8_t>(
       instruction,
       [](uint8_t a) -> UIntReg { return static_cast<UIntReg>(a); });
 }
 
 // Rotate left.
-void RiscVRol(const Instruction *instruction) {
+void RiscVRol(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         int shamt = b & 0x1f;
@@ -147,7 +147,7 @@
 }
 
 // Rotate right.
-void RiscVRor(const Instruction *instruction) {
+void RiscVRor(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         int shamt = b & 0x1f;
@@ -157,7 +157,7 @@
 }
 
 // Or combine (byte wise).
-void RiscVOrcb(const Instruction *instruction) {
+void RiscVOrcb(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction, [](UIntReg a) {
     UIntReg mask = 0xff;
     UIntReg result = 0;
@@ -172,7 +172,7 @@
 }
 
 // Byte reverse.
-void RiscVRev8(const Instruction *instruction) {
+void RiscVRev8(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction, [](UIntReg a) {
     UIntReg result = 0;
     for (int i = 0; i < sizeof(UIntReg); i++) {
@@ -185,7 +185,7 @@
 }
 
 // Carry-less multiplication (using xor) - low 32 bits.
-void RiscVClmul(const Instruction *instruction) {
+void RiscVClmul(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -197,7 +197,7 @@
 }
 
 // Carry-less multiplication (using xor) - high 32 bits.
-void RiscVClmulh(const Instruction *instruction) {
+void RiscVClmulh(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -209,7 +209,7 @@
 }
 
 // Reverse carry-less multiplication (using xor).
-void RiscVClmulr(const Instruction *instruction) {
+void RiscVClmulr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -221,27 +221,27 @@
 }
 
 // Clear bit.
-void RiscVBclr(const Instruction *instruction) {
+void RiscVBclr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return a & ~(1U << (b & 0x1f)); });
 }
 
 // Extract bit.
-void RiscVBext(const Instruction *instruction) {
+void RiscVBext(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return (a >> (b & 0x1f)) & 0x1; });
 }
 
 // Invert bit.
-void RiscVBinv(const Instruction *instruction) {
+void RiscVBinv(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a ^ (1U << (b & 0x1f)); });
 }
 
 // Set bit.
-void RiscVBset(const Instruction *instruction) {
+void RiscVBset(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | (1U << (b & 0x1f)); });
 }
@@ -256,20 +256,20 @@
 constexpr int kXlen = sizeof(UIntReg) * 8;
 
 // 64 + 32 bit unsigned addition.
-void RiscVAddUw(const Instruction *instruction) {
+void RiscVAddUw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return b + (a & 0xffff'ffffULL); });
 }
 
 // Add with shift.
-void RiscVShAdd(const Instruction *instruction) {
+void RiscVShAdd(const Instruction* instruction) {
   auto shift = generic::GetInstructionSource<UIntReg>(instruction, 2);
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [shift](UIntReg a, UIntReg b) { return b + (a << shift); });
 }
 
-void RiscVShAddUw(const Instruction *instruction) {
+void RiscVShAddUw(const Instruction* instruction) {
   auto shift = generic::GetInstructionSource<UIntReg>(instruction, 2);
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [shift](UIntReg a, UIntReg b) {
@@ -277,7 +277,7 @@
       });
 }
 
-void RiscVSlliUw(const Instruction *instruction) {
+void RiscVSlliUw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, uint32_t>(
       instruction, [](UIntReg a, uint32_t shift) -> UIntReg {
         return (a & 0xffff'ffffULL) << shift;
@@ -285,113 +285,113 @@
 }
 
 // And not.
-void RiscVAndn(const Instruction *instruction) {
+void RiscVAndn(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a & ~b; });
 }
 
 // Or not.
-void RiscVOrn(const Instruction *instruction) {
+void RiscVOrn(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | ~b; });
 }
 
 // Xnor.
-void RiscVXnor(const Instruction *instruction) {  // hmm
+void RiscVXnor(const Instruction* instruction) {  // hmm
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return ~(a ^ b); });
 }
 
-void RiscVNot(const generic::Instruction *instruction) {
+void RiscVNot(const generic::Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction,
                                                [](UIntReg a) { return ~a; });
 }
 
 // Count leading zeros.
-void RiscVClz(const Instruction *instruction) {
+void RiscVClz(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::countl_zero(a); });
 }
 
-void RiscVClzw(const Instruction *instruction) {
+void RiscVClzw(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint32_t>(
       instruction, [](uint32_t a) -> UIntReg { return absl::countl_zero(a); });
 }
 
 // Count trailing zeros.
-void RiscVCtz(const Instruction *instruction) {
+void RiscVCtz(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::countr_zero(a); });
 }
 
-void RiscVCtzw(const Instruction *instruction) {
+void RiscVCtzw(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint32_t>(
       instruction, [](uint32_t a) -> UIntReg { return absl::countr_zero(a); });
 }
 
 // Bit population count.
-void RiscVCpop(const Instruction *instruction) {
+void RiscVCpop(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a) -> UIntReg { return absl::popcount(a); });
 }
 
-void RiscVCpopw(const Instruction *instruction) {
+void RiscVCpopw(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, uint32_t, uint32_t>(
       instruction, [](uint32_t a) -> UIntReg { return absl::popcount(a); });
 }
 
 // Signed max.
-void RiscVMax(const Instruction *instruction) {
+void RiscVMax(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return std::max(a, b); });
 }
 
 // Unsigned max.
-void RiscVMaxu(const Instruction *instruction) {
+void RiscVMaxu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return std::max(a, b); });
 }
 
 // Signed min.
-void RiscVMin(const Instruction *instruction) {
+void RiscVMin(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return std::min(a, b); });
 }
 
 // Unsigned min.
-void RiscVMinu(const Instruction *instruction) {
+void RiscVMinu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return std::min(a, b); });
 }
 
 // Sign extend byte.
-void RiscVSextB(const Instruction *instruction) {
+void RiscVSextB(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, IntReg, int8_t>(
       instruction, [](int8_t a) -> IntReg { return static_cast<IntReg>(a); });
 }
 
 // Sign extend half word.
-void RiscVSextH(const Instruction *instruction) {
+void RiscVSextH(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, IntReg, int16_t>(
       instruction, [](int16_t a) -> IntReg { return static_cast<IntReg>(a); });
 }
 
 // Zero extend half word.
-void RiscVZextH(const Instruction *instruction) {
+void RiscVZextH(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint16_t>(
       instruction,
       [](uint16_t a) -> UIntReg { return static_cast<UIntReg>(a); });
 }
 
 // Zero extend byte.
-void RiscVZextB(const Instruction *instruction) {
+void RiscVZextB(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, uint8_t>(
       instruction,
       [](uint8_t a) -> UIntReg { return static_cast<UIntReg>(a); });
 }
 
 // Rotate left.
-void RiscVRol(const Instruction *instruction) {
+void RiscVRol(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         int shamt = b & 0x3f;
@@ -400,7 +400,7 @@
       });
 }
 
-void RiscVRolw(const Instruction *instruction) {  // hmm
+void RiscVRolw(const Instruction* instruction) {  // hmm
   RiscVBinaryOp<RegisterType, IntReg, uint32_t>(
       instruction, [](uint32_t a, uint32_t b) {
         int shamt = b & 0x1f;
@@ -413,7 +413,7 @@
 }
 
 // Rotate right.
-void RiscVRor(const Instruction *instruction) {
+void RiscVRor(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         int shamt = b & 0x3f;
@@ -422,7 +422,7 @@
       });
 }
 
-void RiscVRorw(const Instruction *instruction) {
+void RiscVRorw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, uint32_t>(
       instruction, [](uint32_t a, uint32_t b) {
         int shamt = b & 0x1f;
@@ -435,7 +435,7 @@
 }
 
 // Or combine (byte wise).
-void RiscVOrcb(const Instruction *instruction) {
+void RiscVOrcb(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction, [](UIntReg a) {
     UIntReg mask = 0xffULL;
     UIntReg result = 0;
@@ -450,7 +450,7 @@
 }
 
 // Byte reverse.
-void RiscVRev8(const Instruction *instruction) {
+void RiscVRev8(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, UIntReg, UIntReg>(instruction, [](UIntReg a) {
     UIntReg result = 0;
     for (int i = 0; i < sizeof(UIntReg); i++) {
@@ -463,7 +463,7 @@
 }
 
 // Carry-less multiplication (using xor) - low 32 bits.
-void RiscVClmul(const Instruction *instruction) {
+void RiscVClmul(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -475,7 +475,7 @@
 }
 
 // Carry-less multiplication (using xor) - high 32 bits.
-void RiscVClmulh(const Instruction *instruction) {
+void RiscVClmulh(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -487,7 +487,7 @@
 }
 
 // Reverse carry-less multiplication (using xor).
-void RiscVClmulr(const Instruction *instruction) {
+void RiscVClmulr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) {
         UIntReg result = 0;
@@ -499,28 +499,28 @@
 }
 
 // Clear bit.
-void RiscVBclr(const Instruction *instruction) {
+void RiscVBclr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return a & ~(1ULL << (b & 0x3f)); });
 }
 
 // Extract bit.
-void RiscVBext(const Instruction *instruction) {
+void RiscVBext(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return (a >> (b & 0x3f)) & 0x1; });
 }
 
 // Invert bit.
-void RiscVBinv(const Instruction *instruction) {
+void RiscVBinv(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return a ^ (1ULL << (b & 0x3f)); });
 }
 
 // Set bit.
-void RiscVBset(const Instruction *instruction) {
+void RiscVBset(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction,
       [](UIntReg a, UIntReg b) { return a | (1ULL << (b & 0x3f)); });
diff --git a/riscv/riscv_bitmanip_instructions.h b/riscv/riscv_bitmanip_instructions.h
index 65d2d34..ea8dcf2 100644
--- a/riscv/riscv_bitmanip_instructions.h
+++ b/riscv/riscv_bitmanip_instructions.h
@@ -28,101 +28,101 @@
 
 // This function takes 3 source operands, rs1, rs2, a shift amount, and one
 // destination operand rd.
-void RiscVShAdd(const Instruction *instruction);
+void RiscVShAdd(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVAndn(const Instruction *instruction);
-void RiscVOrn(const Instruction *instruction);
-void RiscVXnor(const Instruction *instruction);
+void RiscVAndn(const Instruction* instruction);
+void RiscVOrn(const Instruction* instruction);
+void RiscVXnor(const Instruction* instruction);
 // Performs the bitwise negation of rs1 (this instruction is strictly not part
 // of Zbb, but part of the 16 bit Zcb extension). It is implemented here because
 // it fits with the other bitwise instructions.
-void RiscVNot(const generic::Instruction *instruction);
+void RiscVNot(const generic::Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVClz(const Instruction *instruction);
-void RiscVCtz(const Instruction *instruction);
-void RiscVCpop(const Instruction *instruction);
+void RiscVClz(const Instruction* instruction);
+void RiscVCtz(const Instruction* instruction);
+void RiscVCpop(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVMax(const Instruction *instruction);
-void RiscVMaxu(const Instruction *instruction);
-void RiscVMin(const Instruction *instruction);
-void RiscVMinu(const Instruction *instruction);
+void RiscVMax(const Instruction* instruction);
+void RiscVMaxu(const Instruction* instruction);
+void RiscVMin(const Instruction* instruction);
+void RiscVMinu(const Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVSextB(const Instruction *instruction);
-void RiscVSextH(const Instruction *instruction);
-void RiscVZextB(const Instruction *instruction);
-void RiscVZextH(const Instruction *instruction);
+void RiscVSextB(const Instruction* instruction);
+void RiscVSextH(const Instruction* instruction);
+void RiscVZextB(const Instruction* instruction);
+void RiscVZextH(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVRol(const Instruction *instruction);
-void RiscVRor(const Instruction *instruction);
+void RiscVRol(const Instruction* instruction);
+void RiscVRor(const Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVOrcb(const Instruction *instruction);
-void RiscVRev8(const Instruction *instruction);
+void RiscVOrcb(const Instruction* instruction);
+void RiscVRev8(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVClmul(const Instruction *instruction);
-void RiscVClmulh(const Instruction *instruction);
-void RiscVClmulr(const Instruction *instruction);
+void RiscVClmul(const Instruction* instruction);
+void RiscVClmulh(const Instruction* instruction);
+void RiscVClmulr(const Instruction* instruction);
 // The following functions take 2 source operands, rs1, rs2/imm, and one
 // destination operand rd.
-void RiscVBclr(const Instruction *instruction);
-void RiscVBext(const Instruction *instruction);
-void RiscVBinv(const Instruction *instruction);
-void RiscVBset(const Instruction *instruction);
+void RiscVBclr(const Instruction* instruction);
+void RiscVBext(const Instruction* instruction);
+void RiscVBinv(const Instruction* instruction);
+void RiscVBset(const Instruction* instruction);
 
 }  // namespace RV32
 
 namespace RV64 {
 // These functions take 3 source operands, rs1, rs2, a shift amount, and one
 // one destination operand rd.
-void RiscVAddUw(const Instruction *instruction);
-void RiscVShAdd(const Instruction *instruction);
-void RiscVShAddUw(const Instruction *instruction);
-void RiscVSlliUw(const Instruction *instruction);
+void RiscVAddUw(const Instruction* instruction);
+void RiscVShAdd(const Instruction* instruction);
+void RiscVShAddUw(const Instruction* instruction);
+void RiscVSlliUw(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination
 // operand rd.
-void RiscVAndn(const Instruction *instruction);
-void RiscVOrn(const Instruction *instruction);
-void RiscVXnor(const Instruction *instruction);
+void RiscVAndn(const Instruction* instruction);
+void RiscVOrn(const Instruction* instruction);
+void RiscVXnor(const Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVClz(const Instruction *instruction);
-void RiscVClzw(const Instruction *instruction);
-void RiscVCtz(const Instruction *instruction);
-void RiscVCtzw(const Instruction *instruction);
-void RiscVCpop(const Instruction *instruction);
-void RiscVCpopw(const Instruction *instruction);
+void RiscVClz(const Instruction* instruction);
+void RiscVClzw(const Instruction* instruction);
+void RiscVCtz(const Instruction* instruction);
+void RiscVCtzw(const Instruction* instruction);
+void RiscVCpop(const Instruction* instruction);
+void RiscVCpopw(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVMax(const Instruction *instruction);
-void RiscVMaxu(const Instruction *instruction);
-void RiscVMin(const Instruction *instruction);
-void RiscVMinu(const Instruction *instruction);
+void RiscVMax(const Instruction* instruction);
+void RiscVMaxu(const Instruction* instruction);
+void RiscVMin(const Instruction* instruction);
+void RiscVMinu(const Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVSextB(const Instruction *instruction);
-void RiscVSextH(const Instruction *instruction);
-void RiscVZextH(const Instruction *instruction);
+void RiscVSextB(const Instruction* instruction);
+void RiscVSextH(const Instruction* instruction);
+void RiscVZextH(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVRol(const Instruction *instruction);
-void RiscVRor(const Instruction *instruction);
-void RiscVRolw(const Instruction *instruction);
-void RiscVRorw(const Instruction *instruction);
+void RiscVRol(const Instruction* instruction);
+void RiscVRor(const Instruction* instruction);
+void RiscVRolw(const Instruction* instruction);
+void RiscVRorw(const Instruction* instruction);
 // These functions take 1 source operands, rs1, and one destination operand rd.
-void RiscVOrcb(const Instruction *instruction);
-void RiscVRev8(const Instruction *instruction);
+void RiscVOrcb(const Instruction* instruction);
+void RiscVRev8(const Instruction* instruction);
 // These function takes 2 source operands, rs1, rs2, and one destination operand
 // rd.
-void RiscVClmul(const Instruction *instruction);
-void RiscVClmulh(const Instruction *instruction);
-void RiscVClmulr(const Instruction *instruction);
+void RiscVClmul(const Instruction* instruction);
+void RiscVClmulh(const Instruction* instruction);
+void RiscVClmulr(const Instruction* instruction);
 // These functions take 2 source operands, rs1, rs2/imm, and one destination
 // operand rd.
-void RiscVBclr(const Instruction *instruction);
-void RiscVBext(const Instruction *instruction);
-void RiscVBinv(const Instruction *instruction);
-void RiscVBset(const Instruction *instruction);
+void RiscVBclr(const Instruction* instruction);
+void RiscVBext(const Instruction* instruction);
+void RiscVBinv(const Instruction* instruction);
+void RiscVBset(const Instruction* instruction);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_cli_forwarder.cc b/riscv/riscv_cli_forwarder.cc
index fd3708f..8b36ff0 100644
--- a/riscv/riscv_cli_forwarder.cc
+++ b/riscv/riscv_cli_forwarder.cc
@@ -35,7 +35,7 @@
 using HaltReasonValueType =
     ::mpact::sim::generic::CoreDebugInterface::HaltReasonValueType;
 
-RiscVCLIForwarder::RiscVCLIForwarder(RiscVRenodeCLITop *riscv_cli_top)
+RiscVCLIForwarder::RiscVCLIForwarder(RiscVRenodeCLITop* riscv_cli_top)
     : riscv_cli_top_(riscv_cli_top) {}
 
 // Forward the calls to the RiscVRenodeCLITop class - CLI methods.
@@ -100,28 +100,28 @@
 
 // Read/write the named registers.
 absl::StatusOr<uint64_t> RiscVCLIForwarder::ReadRegister(
-    const std::string &name) {
+    const std::string& name) {
   return riscv_cli_top_->CLIReadRegister(name);
 }
 
-absl::Status RiscVCLIForwarder::WriteRegister(const std::string &name,
+absl::Status RiscVCLIForwarder::WriteRegister(const std::string& name,
                                               uint64_t value) {
   return riscv_cli_top_->CLIWriteRegister(name, value);
 }
 
-absl::StatusOr<DataBuffer *> RiscVCLIForwarder::GetRegisterDataBuffer(
-    const std::string &name) {
+absl::StatusOr<DataBuffer*> RiscVCLIForwarder::GetRegisterDataBuffer(
+    const std::string& name) {
   return riscv_cli_top_->CLIGetRegisterDataBuffer(name);
 }
 
 // Read/write the buffers to memory.
 absl::StatusOr<size_t> RiscVCLIForwarder::ReadMemory(uint64_t address,
-                                                     void *buf, size_t length) {
+                                                     void* buf, size_t length) {
   return riscv_cli_top_->CLIReadMemory(address, buf, length);
 }
 
 absl::StatusOr<size_t> RiscVCLIForwarder::WriteMemory(uint64_t address,
-                                                      const void *buf,
+                                                      const void* buf,
                                                       size_t length) {
   return riscv_cli_top_->CLIWriteMemory(address, buf, length);
 }
@@ -142,7 +142,7 @@
   return riscv_cli_top_->CLIClearAllSwBreakpoints();
 }
 
-absl::StatusOr<Instruction *> RiscVCLIForwarder::GetInstruction(
+absl::StatusOr<Instruction*> RiscVCLIForwarder::GetInstruction(
     uint64_t address) {
   return riscv_cli_top_->CLIGetInstruction(address);
 }
diff --git a/riscv/riscv_cli_forwarder.h b/riscv/riscv_cli_forwarder.h
index eb934ed..0e4e7ce 100644
--- a/riscv/riscv_cli_forwarder.h
+++ b/riscv/riscv_cli_forwarder.h
@@ -42,10 +42,10 @@
 
 class RiscVCLIForwarder : public RiscVDebugInterface {
  public:
-  explicit RiscVCLIForwarder(RiscVRenodeCLITop *top);
+  explicit RiscVCLIForwarder(RiscVRenodeCLITop* top);
   RiscVCLIForwarder() = delete;
-  RiscVCLIForwarder(const CLIForwarder &) = delete;
-  RiscVCLIForwarder &operator=(const CLIForwarder &) = delete;
+  RiscVCLIForwarder(const CLIForwarder&) = delete;
+  RiscVCLIForwarder& operator=(const CLIForwarder&) = delete;
 
   // Set a data watchpoint for the given memory range. Any access matching the
   // given access type (load/store) will halt execution following the completion
@@ -84,8 +84,8 @@
   // Returns the reason for the most recent halt.
   absl::StatusOr<HaltReasonValueType> GetLastHaltReason() override;
 
-  absl::StatusOr<uint64_t> ReadRegister(const std::string &name) override;
-  absl::Status WriteRegister(const std::string &name, uint64_t value) override;
+  absl::StatusOr<uint64_t> ReadRegister(const std::string& name) override;
+  absl::Status WriteRegister(const std::string& name, uint64_t value) override;
 
   // Some registers, including vector registers, have values that exceed the
   // 64 bits supported in the Read/Write register API calls. This function
@@ -97,13 +97,13 @@
   // Note (2): In some cases, a register write may replace the DataBuffer
   // instance within a register so that any stored references to it become
   // stale.
-  absl::StatusOr<DataBuffer *> GetRegisterDataBuffer(
-      const std::string &name) override;
+  absl::StatusOr<DataBuffer*> GetRegisterDataBuffer(
+      const std::string& name) override;
 
   // Read/write the buffers to memory.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
 
   // Test to see if there's a breakpoint at the given address.
@@ -115,12 +115,12 @@
   absl::Status ClearAllSwBreakpoints() override;
 
   // Return the instruction object for the instruction at the given address.
-  absl::StatusOr<Instruction *> GetInstruction(uint64_t address) override;
+  absl::StatusOr<Instruction*> GetInstruction(uint64_t address) override;
   // Return the string representation for the instruction at the given address.
   absl::StatusOr<std::string> GetDisassembly(uint64_t address) override;
 
  private:
-  RiscVRenodeCLITop *riscv_cli_top_;
+  RiscVRenodeCLITop* riscv_cli_top_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv_clint.cc b/riscv/riscv_clint.cc
index 258428a..5c68132 100644
--- a/riscv/riscv_clint.cc
+++ b/riscv/riscv_clint.cc
@@ -33,7 +33,7 @@
 using ::mpact::sim::generic::ReferenceCount;
 using EC = ::mpact::sim::riscv::ExceptionCode;
 
-RiscVClint::RiscVClint(int period, MipExternalWriteInterface *mip_interface)
+RiscVClint::RiscVClint(int period, MipExternalWriteInterface* mip_interface)
     : mip_interface_(mip_interface), period_(period) {
   // Set the initial values.
   SetValue(0);
@@ -54,7 +54,7 @@
 }
 
 // Called by the counter whenever its value is changed.
-void RiscVClint::SetValue(const uint64_t &val) {
+void RiscVClint::SetValue(const uint64_t& val) {
   update_counter_++;
   if (update_counter_ >= period_) {
     update_counter_ = 0;
@@ -68,8 +68,8 @@
 
 // Implementation of the memory load interface for reading memory mapped
 // registers.
-void RiscVClint::Load(uint64_t address, DataBuffer *db, Instruction *inst,
-                      ReferenceCount *context) {
+void RiscVClint::Load(uint64_t address, DataBuffer* db, Instruction* inst,
+                      ReferenceCount* context) {
   uint32_t offset = address & 0xffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -108,15 +108,15 @@
 }
 
 // No support for vector loads.
-void RiscVClint::Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-                      DataBuffer *db, Instruction *inst,
-                      ReferenceCount *context) {
+void RiscVClint::Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+                      DataBuffer* db, Instruction* inst,
+                      ReferenceCount* context) {
   LOG(FATAL) << "RiscVClint does not support vector loads";
 }
 
 // Implementation of memory store interface to support writes to memory mapped
 // registers.
-void RiscVClint::Store(uint64_t address, DataBuffer *db) {
+void RiscVClint::Store(uint64_t address, DataBuffer* db) {
   uint32_t offset = address & 0xffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -134,8 +134,8 @@
 }
 
 // No support for vector stores.
-void RiscVClint::Store(DataBuffer *address, DataBuffer *mask, int el_size,
-                       DataBuffer *db) {
+void RiscVClint::Store(DataBuffer* address, DataBuffer* mask, int el_size,
+                       DataBuffer* db) {
   LOG(FATAL) << "RiscVClint does not support vector stores";
 }
 
diff --git a/riscv/riscv_clint.h b/riscv/riscv_clint.h
index 9226c0b..a892e71 100644
--- a/riscv/riscv_clint.h
+++ b/riscv/riscv_clint.h
@@ -64,30 +64,30 @@
 class RiscVClint : public CounterValueSetInterface<uint64_t>,
                    public MemoryInterface {
  public:
-  RiscVClint(int period, MipExternalWriteInterface *mip_interface);
+  RiscVClint(int period, MipExternalWriteInterface* mip_interface);
   RiscVClint() = delete;
-  RiscVClint(const RiscVClint &) = delete;
-  RiscVClint &operator=(const RiscVClint &) = delete;
+  RiscVClint(const RiscVClint&) = delete;
+  RiscVClint& operator=(const RiscVClint&) = delete;
   ~RiscVClint() override = default;
   // Resets the interrupt controller.
   void Reset();
   // CounterValueSetInterface override. This is called when the value of the
   // bound counter is modified.
-  void SetValue(const uint64_t &val) override;
+  void SetValue(const uint64_t& val) override;
 
   // MemoryInterface overrides.
   // Non-vector load method.
-  void Load(uint64_t address, DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(uint64_t address, DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Vector load method - this is stubbed out.
-  void Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-            DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+            DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Non-vector store method.
-  void Store(uint64_t address, DataBuffer *db) override;
+  void Store(uint64_t address, DataBuffer* db) override;
   // Vector store method - this is stubbed out.
-  void Store(DataBuffer *address, DataBuffer *mask, int el_size,
-             DataBuffer *db) override;
+  void Store(DataBuffer* address, DataBuffer* mask, int el_size,
+             DataBuffer* db) override;
 
  private:
   // Helpers.
@@ -108,7 +108,7 @@
   uint64_t mtimecmp_ = 0;
   int mtip_ = 0;
   // mip write interface.
-  MipExternalWriteInterface *mip_interface_;
+  MipExternalWriteInterface* mip_interface_;
   // Counter for how many updates there have been in current period.
   int update_counter_ = 0;
   int period_ = 0;
diff --git a/riscv/riscv_csr.cc b/riscv/riscv_csr.cc
index b6c02de..92f7c03 100644
--- a/riscv/riscv_csr.cc
+++ b/riscv/riscv_csr.cc
@@ -28,7 +28,7 @@
 namespace sim {
 namespace riscv {
 
-void RiscVCsrWriteDb::SetDataBuffer(generic::DataBuffer *db) {
+void RiscVCsrWriteDb::SetDataBuffer(generic::DataBuffer* db) {
   auto db_size = db->size<uint8_t>();
   if (db_size == 4) {
     csr_->Write(db->Get<uint32_t>(0));
@@ -41,7 +41,7 @@
   LOG(ERROR) << "Attempted to write CSR with width != 32 or 64";
 }
 
-void RiscVCsrClearBitsDb::SetDataBuffer(generic::DataBuffer *db) {
+void RiscVCsrClearBitsDb::SetDataBuffer(generic::DataBuffer* db) {
   auto db_size = db->size<uint8_t>();
   if (db_size == 4) {
     csr_->ClearBits(db->Get<uint32_t>(0));
@@ -54,7 +54,7 @@
   LOG(ERROR) << "Attempted to clear CSR with width != 32 or 64";
 }
 
-void RiscVCsrSetBitsDb::SetDataBuffer(generic::DataBuffer *db) {
+void RiscVCsrSetBitsDb::SetDataBuffer(generic::DataBuffer* db) {
   auto db_size = db->size<uint8_t>();
   if (db_size == 4) {
     csr_->SetBits(db->Get<uint32_t>(0));
@@ -67,7 +67,7 @@
   LOG(ERROR) << "Attempted to set CSR with width != 32 or 64";
 }
 
-absl::Status RiscVCsrSet::AddCsr(RiscVCsrInterface *csr) {
+absl::Status RiscVCsrSet::AddCsr(RiscVCsrInterface* csr) {
   if (csr == nullptr) {
     return absl::InvalidArgumentError("csr is nullptr");
   }
@@ -87,8 +87,7 @@
   return absl::OkStatus();
 }
 
-absl::StatusOr<RiscVCsrInterface *> RiscVCsrSet::GetCsr(
-    absl::string_view name) {
+absl::StatusOr<RiscVCsrInterface*> RiscVCsrSet::GetCsr(absl::string_view name) {
   auto name_ptr = csr_name_map_.find(name);
   if (name_ptr == csr_name_map_.end()) {
     return absl::NotFoundError(absl::StrCat("No such CSR: '", name, "'"));
@@ -96,7 +95,7 @@
   return name_ptr->second;
 }
 
-absl::StatusOr<RiscVCsrInterface *> RiscVCsrSet::GetCsr(uint64_t index) {
+absl::StatusOr<RiscVCsrInterface*> RiscVCsrSet::GetCsr(uint64_t index) {
   auto index_ptr = csr_index_map_.find(index);
   if (index_ptr == csr_index_map_.end()) {
     return absl::NotFoundError(absl::StrCat("No such CSR index: ", index));
@@ -116,11 +115,11 @@
   return absl::OkStatus();
 }
 
-RiscVCsrSourceOperand::RiscVCsrSourceOperand(RiscVCsrInterface *csr,
+RiscVCsrSourceOperand::RiscVCsrSourceOperand(RiscVCsrInterface* csr,
                                              std::string op_name)
     : csr_(csr), op_name_(op_name) {}
 
-RiscVCsrSourceOperand::RiscVCsrSourceOperand(RiscVCsrInterface *csr)
+RiscVCsrSourceOperand::RiscVCsrSourceOperand(RiscVCsrInterface* csr)
     : RiscVCsrSourceOperand(csr, csr->name()) {}
 
 bool RiscVCsrSourceOperand::AsBool(int i) {
@@ -153,7 +152,7 @@
 
 // Implementation of the destination op templated class methods.
 RiscVCsrDestinationOperand::RiscVCsrDestinationOperand(
-    RiscVCsrInterface *csr, generic::DataBufferDestination *db_dest,
+    RiscVCsrInterface* csr, generic::DataBufferDestination* db_dest,
     int latency, std::string op_name)
     : csr_(csr),
       db_dest_(db_dest),
@@ -163,18 +162,18 @@
       op_name_(op_name) {}
 
 RiscVCsrDestinationOperand::RiscVCsrDestinationOperand(
-    RiscVCsrInterface *csr, generic::DataBufferDestination *db_dest,
+    RiscVCsrInterface* csr, generic::DataBufferDestination* db_dest,
     int latency)
     : RiscVCsrDestinationOperand(csr, db_dest, latency, csr->name()) {}
 
-void RiscVCsrDestinationOperand::InitializeDataBuffer(generic::DataBuffer *db) {
+void RiscVCsrDestinationOperand::InitializeDataBuffer(generic::DataBuffer* db) {
   db->set_destination(db_dest_);
   db->set_latency(latency_);
   db->set_delay_line(delay_line_);
 }
 
-generic::DataBuffer *RiscVCsrDestinationOperand::CopyDataBuffer() {
-  generic::DataBuffer *db = db_factory_->Allocate(csr_->size());
+generic::DataBuffer* RiscVCsrDestinationOperand::CopyDataBuffer() {
+  generic::DataBuffer* db = db_factory_->Allocate(csr_->size());
   if (csr_->size() == 4) {
     db->Set<uint32_t>(0, csr_->AsUint32());
   } else if (csr_->size() == 8) {
@@ -184,8 +183,8 @@
   return db;
 }
 
-generic::DataBuffer *RiscVCsrDestinationOperand::AllocateDataBuffer() {
-  generic::DataBuffer *db = db_factory_->Allocate(csr_->size());
+generic::DataBuffer* RiscVCsrDestinationOperand::AllocateDataBuffer() {
+  generic::DataBuffer* db = db_factory_->Allocate(csr_->size());
   InitializeDataBuffer(db);
   return db;
 }
diff --git a/riscv/riscv_csr.h b/riscv/riscv_csr.h
index b3b9480..53e40b8 100644
--- a/riscv/riscv_csr.h
+++ b/riscv/riscv_csr.h
@@ -170,34 +170,34 @@
 // the index.
 class RiscVCsrBase {
  public:
-  RiscVCsrBase(std::string name, uint64_t index, ArchState *state)
+  RiscVCsrBase(std::string name, uint64_t index, ArchState* state)
       : name_(name), index_(index), state_(state) {}
   RiscVCsrBase() = delete;
   virtual ~RiscVCsrBase() = default;
 
   // Source and destination creation interface.
-  virtual generic::SourceOperandInterface *CreateSourceOperand() = 0;
-  virtual generic::DestinationOperandInterface *CreateSetDestinationOperand(
+  virtual generic::SourceOperandInterface* CreateSourceOperand() = 0;
+  virtual generic::DestinationOperandInterface* CreateSetDestinationOperand(
       int latency, std::string op_name) = 0;
-  virtual generic::DestinationOperandInterface *CreateClearDestinationOperand(
+  virtual generic::DestinationOperandInterface* CreateClearDestinationOperand(
       int latency, std::string op_name) = 0;
-  virtual generic::DestinationOperandInterface *CreateWriteDestinationOperand(
+  virtual generic::DestinationOperandInterface* CreateWriteDestinationOperand(
       int latency, std::string op_name) = 0;
 
   // Three getters: name, index, and state
-  const std::string &name() { return name_; }
+  const std::string& name() { return name_; }
   uint64_t index() const { return index_; }
-  ArchState *state() { return state_; }
+  ArchState* state() { return state_; }
 
  private:
   std::string name_;
   uint64_t index_ = 0;
-  ArchState *state_;
+  ArchState* state_;
 };
 
 class RiscVCsrInterface : public RiscVCsrBase {
  public:
-  RiscVCsrInterface(std::string name, uint64_t index, ArchState *state)
+  RiscVCsrInterface(std::string name, uint64_t index, ArchState* state)
       : RiscVCsrBase(name, index, state) {}
   RiscVCsrInterface() = delete;
   ~RiscVCsrInterface() override = default;
@@ -228,34 +228,34 @@
 class RiscVCsrWriteDb : public generic::DataBufferDestination {
  public:
   RiscVCsrWriteDb() = delete;
-  explicit RiscVCsrWriteDb(RiscVCsrInterface *csr) : csr_(csr) {}
+  explicit RiscVCsrWriteDb(RiscVCsrInterface* csr) : csr_(csr) {}
 
-  void SetDataBuffer(generic::DataBuffer *db) override;
+  void SetDataBuffer(generic::DataBuffer* db) override;
 
  private:
-  RiscVCsrInterface *csr_;
+  RiscVCsrInterface* csr_;
 };
 
 class RiscVCsrClearBitsDb : public generic::DataBufferDestination {
  public:
   RiscVCsrClearBitsDb() = delete;
-  explicit RiscVCsrClearBitsDb(RiscVCsrInterface *csr) : csr_(csr) {}
+  explicit RiscVCsrClearBitsDb(RiscVCsrInterface* csr) : csr_(csr) {}
 
-  void SetDataBuffer(generic::DataBuffer *db) override;
+  void SetDataBuffer(generic::DataBuffer* db) override;
 
  private:
-  RiscVCsrInterface *csr_;
+  RiscVCsrInterface* csr_;
 };
 
 class RiscVCsrSetBitsDb : public generic::DataBufferDestination {
  public:
   RiscVCsrSetBitsDb() = delete;
-  explicit RiscVCsrSetBitsDb(RiscVCsrInterface *csr) : csr_(csr) {}
+  explicit RiscVCsrSetBitsDb(RiscVCsrInterface* csr) : csr_(csr) {}
 
-  void SetDataBuffer(generic::DataBuffer *db) override;
+  void SetDataBuffer(generic::DataBuffer* db) override;
 
  private:
-  RiscVCsrInterface *csr_;
+  RiscVCsrInterface* csr_;
 };
 
 // RiscV CSR class.
@@ -263,47 +263,47 @@
 class RiscVSimpleCsr : public RiscVCsrInterface {
  public:
   // Enum index.
-  RiscVSimpleCsr(std::string name, RiscVCsrEnum index, ArchState *state)
+  RiscVSimpleCsr(std::string name, RiscVCsrEnum index, ArchState* state)
       : RiscVSimpleCsr(
             name, index, 0,
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             state) {}
   RiscVSimpleCsr(std::string name, RiscVCsrEnum index, T initial_value,
-                 ArchState *state)
+                 ArchState* state)
       : RiscVSimpleCsr(
             name, index, initial_value,
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             state) {}
   RiscVSimpleCsr(std::string name, RiscVCsrEnum index, T read_mask,
-                 T write_mask, ArchState *state)
+                 T write_mask, ArchState* state)
       : RiscVSimpleCsr(name, index, 0, read_mask, write_mask, state) {}
   // Uint64_t valued index. These are useful for other RiscV architecture
   // variants that add custom CSRs.
-  RiscVSimpleCsr(std::string name, uint64_t index, ArchState *state)
+  RiscVSimpleCsr(std::string name, uint64_t index, ArchState* state)
       : RiscVSimpleCsr(
             name, index, 0,
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             state) {}
   RiscVSimpleCsr(std::string name, uint64_t index, T initial_value,
-                 ArchState *state)
+                 ArchState* state)
       : RiscVSimpleCsr(
             name, index, initial_value,
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             std::numeric_limits<typename std::make_unsigned<T>::type>::max(),
             state) {}
   RiscVSimpleCsr(std::string name, uint64_t index, T read_mask, T write_mask,
-                 ArchState *state)
+                 ArchState* state)
       : RiscVSimpleCsr(name, index, 0, read_mask, write_mask, state) {}
 
   RiscVSimpleCsr(std::string name, RiscVCsrEnum index, T initial_value,
-                 T read_mask, T write_mask, ArchState *state)
+                 T read_mask, T write_mask, ArchState* state)
       : RiscVSimpleCsr(name, static_cast<uint64_t>(index), initial_value,
                        read_mask, write_mask, state) {}
   RiscVSimpleCsr(std::string name, uint64_t index, T initial_value, T read_mask,
-                 T write_mask, ArchState *state)
+                 T write_mask, ArchState* state)
       : RiscVCsrInterface(name, index, state),
         value_(initial_value),
         read_mask_(read_mask),
@@ -320,8 +320,8 @@
 
   // Disable default and copy constructor, as well as assignment.
   RiscVSimpleCsr() = delete;
-  RiscVSimpleCsr(const RiscVSimpleCsr &) = delete;
-  RiscVSimpleCsr &operator=(const RiscVSimpleCsr &) = delete;
+  RiscVSimpleCsr(const RiscVSimpleCsr&) = delete;
+  RiscVSimpleCsr& operator=(const RiscVSimpleCsr&) = delete;
 
   // Return the value, modified as per read mask.
   uint32_t AsUint32() override {
@@ -353,12 +353,12 @@
   void Set(uint64_t value) override { value_ = static_cast<T>(value); }
 
   // Operand creation interface.
-  generic::SourceOperandInterface *CreateSourceOperand() override;
-  generic::DestinationOperandInterface *CreateSetDestinationOperand(
+  generic::SourceOperandInterface* CreateSourceOperand() override;
+  generic::DestinationOperandInterface* CreateSetDestinationOperand(
       int latency, std::string op_name) override;
-  generic::DestinationOperandInterface *CreateClearDestinationOperand(
+  generic::DestinationOperandInterface* CreateClearDestinationOperand(
       int latency, std::string op_name) override;
-  generic::DestinationOperandInterface *CreateWriteDestinationOperand(
+  generic::DestinationOperandInterface* CreateWriteDestinationOperand(
       int latency, std::string op_name) override;
 
   // Getters and setters.
@@ -367,9 +367,9 @@
   T write_mask() const { return write_mask_; }
   void set_write_mask(T value) { write_mask_ = value; }
 
-  RiscVCsrWriteDb *write_target() const { return write_target_; }
-  RiscVCsrSetBitsDb *set_bits_target() const { return set_bits_target_; }
-  RiscVCsrClearBitsDb *clear_bits_target() const { return clear_bits_target_; }
+  RiscVCsrWriteDb* write_target() const { return write_target_; }
+  RiscVCsrSetBitsDb* set_bits_target() const { return set_bits_target_; }
+  RiscVCsrClearBitsDb* clear_bits_target() const { return clear_bits_target_; }
 
   size_t size() const override { return sizeof(T); }
 
@@ -383,9 +383,9 @@
       std::numeric_limits<typename std::make_unsigned<T>::type>::max();
   T write_mask_ =
       std::numeric_limits<typename std::make_unsigned<T>::type>::max();
-  RiscVCsrWriteDb *write_target_;
-  RiscVCsrSetBitsDb *set_bits_target_;
-  RiscVCsrClearBitsDb *clear_bits_target_;
+  RiscVCsrWriteDb* write_target_;
+  RiscVCsrSetBitsDb* set_bits_target_;
+  RiscVCsrClearBitsDb* clear_bits_target_;
 };
 
 // The shadow csr class is used to implement a more restricted view of another
@@ -395,7 +395,7 @@
 class RiscVShadowCsr : public RiscVCsrInterface {
  public:
   RiscVShadowCsr(std::string name, RiscVCsrEnum index, T read_mask,
-                 T write_mask, ArchState *state, RiscVCsrInterface *csr)
+                 T write_mask, ArchState* state, RiscVCsrInterface* csr)
       : RiscVCsrInterface(name, static_cast<uint64_t>(index), state),
         csr_(csr),
         read_mask_(read_mask),
@@ -404,8 +404,8 @@
         set_bits_target_(new RiscVCsrSetBitsDb(this)),
         clear_bits_target_(new RiscVCsrClearBitsDb(this)) {}
   RiscVShadowCsr() = delete;
-  RiscVShadowCsr(const RiscVShadowCsr &) = delete;
-  RiscVShadowCsr &operator=(const RiscVShadowCsr &) = delete;
+  RiscVShadowCsr(const RiscVShadowCsr&) = delete;
+  RiscVShadowCsr& operator=(const RiscVShadowCsr&) = delete;
 
   ~RiscVShadowCsr() override {
     delete write_target_;
@@ -451,29 +451,29 @@
   // Set to reset value.
   void Reset() override { /* Empty. */ }
   // Operand creation interface.
-  generic::SourceOperandInterface *CreateSourceOperand() override;
-  generic::DestinationOperandInterface *CreateSetDestinationOperand(
+  generic::SourceOperandInterface* CreateSourceOperand() override;
+  generic::DestinationOperandInterface* CreateSetDestinationOperand(
       int latency, std::string op_name) override;
-  generic::DestinationOperandInterface *CreateClearDestinationOperand(
+  generic::DestinationOperandInterface* CreateClearDestinationOperand(
       int latency, std::string op_name) override;
-  generic::DestinationOperandInterface *CreateWriteDestinationOperand(
+  generic::DestinationOperandInterface* CreateWriteDestinationOperand(
       int latency, std::string op_name) override;
 
-  RiscVCsrWriteDb *write_target() const { return write_target_; }
-  RiscVCsrSetBitsDb *set_bits_target() const { return set_bits_target_; }
-  RiscVCsrClearBitsDb *clear_bits_target() const { return clear_bits_target_; }
+  RiscVCsrWriteDb* write_target() const { return write_target_; }
+  RiscVCsrSetBitsDb* set_bits_target() const { return set_bits_target_; }
+  RiscVCsrClearBitsDb* clear_bits_target() const { return clear_bits_target_; }
 
-  RiscVCsrInterface *csr() const { return csr_; }
+  RiscVCsrInterface* csr() const { return csr_; }
   T read_mask() const { return read_mask_; }
   T write_mask() const { return write_mask_; }
 
  private:
-  RiscVCsrInterface *csr_;
+  RiscVCsrInterface* csr_;
   T read_mask_;
   T write_mask_;
-  RiscVCsrWriteDb *write_target_;
-  RiscVCsrSetBitsDb *set_bits_target_;
-  RiscVCsrClearBitsDb *clear_bits_target_;
+  RiscVCsrWriteDb* write_target_;
+  RiscVCsrSetBitsDb* set_bits_target_;
+  RiscVCsrClearBitsDb* clear_bits_target_;
 };
 
 using RiscV32SimpleCsr = RiscVSimpleCsr<uint32_t>;
@@ -483,30 +483,30 @@
  public:
   // Constructor.
   RiscVCsrSet() = default;
-  RiscVCsrSet(const RiscVCsrSet &) = delete;
-  RiscVCsrSet &operator=(const RiscVCsrSet &) = delete;
+  RiscVCsrSet(const RiscVCsrSet&) = delete;
+  RiscVCsrSet& operator=(const RiscVCsrSet&) = delete;
 
   // Add the CSR to the CsrSet. Return error if it already exists. The storage
   // is owned by the caller, and must remain valid for the duration of
   // the lifetime of the CsrSet instance, or explicitly removed.
-  absl::Status AddCsr(RiscVCsrInterface *csr);
+  absl::Status AddCsr(RiscVCsrInterface* csr);
   // Methods to get a handle to the CSR.
-  absl::StatusOr<RiscVCsrInterface *> GetCsr(absl::string_view name);
-  absl::StatusOr<RiscVCsrInterface *> GetCsr(uint64_t index);
+  absl::StatusOr<RiscVCsrInterface*> GetCsr(absl::string_view name);
+  absl::StatusOr<RiscVCsrInterface*> GetCsr(uint64_t index);
   // Remove the CSR from the CsrSet.
   absl::Status RemoveCsr(uint64_t csr_index);
 
  private:
-  absl::flat_hash_map<std::string, RiscVCsrInterface *> csr_name_map_;
-  absl::flat_hash_map<uint64_t, RiscVCsrInterface *> csr_index_map_;
+  absl::flat_hash_map<std::string, RiscVCsrInterface*> csr_name_map_;
+  absl::flat_hash_map<uint64_t, RiscVCsrInterface*> csr_index_map_;
 };
 
 // Source operand type for CSR.
 class RiscVCsrSourceOperand : public generic::SourceOperandInterface {
  public:
   // Constructor. Note, default constructor is deleted.
-  RiscVCsrSourceOperand(RiscVCsrInterface *csr, std::string op_name);
-  explicit RiscVCsrSourceOperand(RiscVCsrInterface *csr);
+  RiscVCsrSourceOperand(RiscVCsrInterface* csr, std::string op_name);
+  explicit RiscVCsrSourceOperand(RiscVCsrInterface* csr);
   RiscVCsrSourceOperand() = delete;
 
   // Methods to read the value of the CSR.
@@ -522,14 +522,14 @@
   // Returns the RiscVCsrInterface<T> object wrapped in absl::any.
   std::any GetObject() const final { return std::any(csr_); }
   // Non-inherited method to get the register object.
-  RiscVCsrInterface *GetCsr() const { return csr_; }
+  RiscVCsrInterface* GetCsr() const { return csr_; }
 
   std::vector<int> shape() const final { return {1}; }
 
   std::string AsString() const final { return op_name_; }
 
  private:
-  RiscVCsrInterface *csr_;
+  RiscVCsrInterface* csr_;
   std::string op_name_;
 };
 
@@ -537,26 +537,26 @@
 class RiscVCsrDestinationOperand : public generic::DestinationOperandInterface {
  public:
   // Constructor and Destructor
-  RiscVCsrDestinationOperand(RiscVCsrInterface *csr,
-                             generic::DataBufferDestination *db_dest,
+  RiscVCsrDestinationOperand(RiscVCsrInterface* csr,
+                             generic::DataBufferDestination* db_dest,
                              int latency);
-  RiscVCsrDestinationOperand(RiscVCsrInterface *csr,
-                             generic::DataBufferDestination *db_dest,
+  RiscVCsrDestinationOperand(RiscVCsrInterface* csr,
+                             generic::DataBufferDestination* db_dest,
                              int latency, std::string op_name);
   RiscVCsrDestinationOperand() = delete;
 
   // Initializes the DataBuffer instance so that when Submit is called, it can
   // be entered into the correct delay line, with the correct latency, targeting
   // the correct csr.
-  void InitializeDataBuffer(generic::DataBuffer *db) override;
+  void InitializeDataBuffer(generic::DataBuffer* db) override;
 
   // Allocates and returns an initialized DataBuffer instance that contains a
   // copy of the current value of the csr. This is useful when only part
   // of the destination register will be modified.
-  generic::DataBuffer *CopyDataBuffer() override;
+  generic::DataBuffer* CopyDataBuffer() override;
 
   // Allocates and returns an initialized DataBuffer instance.
-  generic::DataBuffer *AllocateDataBuffer() final;
+  generic::DataBuffer* AllocateDataBuffer() final;
 
   // Returns the latency associated with writes to this csr operand.
   int latency() const override { return latency_; }
@@ -567,21 +567,21 @@
   std::vector<int> shape() const override { return {1}; }
 
   // Non-inherited method to get the register object.
-  RiscVCsrInterface *GetRiscVCsr() const { return csr_; }
+  RiscVCsrInterface* GetRiscVCsr() const { return csr_; }
 
   std::string AsString() const override { return op_name_; }
 
  private:
-  RiscVCsrInterface *csr_;
-  generic::DataBufferDestination *db_dest_;
-  generic::DataBufferFactory *db_factory_;
+  RiscVCsrInterface* csr_;
+  generic::DataBufferDestination* db_dest_;
+  generic::DataBufferFactory* db_factory_;
   int latency_;
-  generic::DataBufferDelayLine *delay_line_;
+  generic::DataBufferDelayLine* delay_line_;
   std::string op_name_;
 };
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVSimpleCsr<T>::CreateSetDestinationOperand(int latency,
                                                std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->set_bits_target(), latency,
@@ -589,7 +589,7 @@
 }
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVSimpleCsr<T>::CreateClearDestinationOperand(int latency,
                                                  std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->clear_bits_target(),
@@ -597,7 +597,7 @@
 }
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVSimpleCsr<T>::CreateWriteDestinationOperand(int latency,
                                                  std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->write_target(), latency,
@@ -605,12 +605,12 @@
 }
 
 template <typename T>
-generic::SourceOperandInterface *RiscVSimpleCsr<T>::CreateSourceOperand() {
+generic::SourceOperandInterface* RiscVSimpleCsr<T>::CreateSourceOperand() {
   return new RiscVCsrSourceOperand(this);
 }
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVShadowCsr<T>::CreateSetDestinationOperand(int latency,
                                                std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->set_bits_target(), latency,
@@ -618,7 +618,7 @@
 }
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVShadowCsr<T>::CreateClearDestinationOperand(int latency,
                                                  std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->clear_bits_target(),
@@ -626,7 +626,7 @@
 }
 
 template <typename T>
-generic::DestinationOperandInterface *
+generic::DestinationOperandInterface*
 RiscVShadowCsr<T>::CreateWriteDestinationOperand(int latency,
                                                  std::string op_name) {
   return new RiscVCsrDestinationOperand(this, this->write_target(), latency,
@@ -634,7 +634,7 @@
 }
 
 template <typename T>
-generic::SourceOperandInterface *RiscVShadowCsr<T>::CreateSourceOperand() {
+generic::SourceOperandInterface* RiscVShadowCsr<T>::CreateSourceOperand() {
   return new RiscVCsrSourceOperand(this);
 }
 
diff --git a/riscv/riscv_d_instructions.cc b/riscv/riscv_d_instructions.cc
index 690c5a2..51f4c03 100644
--- a/riscv/riscv_d_instructions.cc
+++ b/riscv/riscv_d_instructions.cc
@@ -54,44 +54,44 @@
 static inline T CanonicalizeNaN(T value) {
   if (!std::isnan(value)) return value;
   auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-  return *reinterpret_cast<T *>(&nan_value);
+  return *reinterpret_cast<T*>(&nan_value);
 }
 
 }  // namespace internal
 
 // Basic arithmetic operations.
-void RiscVDAdd(const Instruction *instruction) {
+void RiscVDAdd(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, double, double>(
       instruction, [](double a, double b) { return a + b; });
 }
 
-void RiscVDSub(const Instruction *instruction) {
+void RiscVDSub(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, double, double>(
       instruction, [](double a, double b) { return a - b; });
 }
 
-void RiscVDMul(const Instruction *instruction) {
+void RiscVDMul(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, double, double>(
       instruction, [](double a, double b) { return a * b; });
 }
 
-void RiscVDDiv(const Instruction *instruction) {
+void RiscVDDiv(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, double, double>(
       instruction, [](double a, double b) { return a / b; });
 }
 
 // Square root uses the library square root.
-void RiscVDSqrt(const Instruction *instruction) {
+void RiscVDSqrt(const Instruction* instruction) {
   RiscVUnaryNaNBoxOp<FPRegister::ValueType, FPRegister::ValueType, double,
                      double>(instruction, [instruction](double a) -> double {
     // If the input value is NaN or less than zero, set the invalid op flag.
     if (FPTypeInfo<double>::IsNaN(a) || (a < 0.0)) {
       if (!FPTypeInfo<double>::IsQNaN(a)) {
-        auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+        auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
         flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
         flag_db->Submit();
       }
-      return *reinterpret_cast<const double *>(
+      return *reinterpret_cast<const double*>(
           &FPTypeInfo<double>::kCanonicalNaN);
     }
 
@@ -102,12 +102,12 @@
     // Get the rounding mode.
     int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-    auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+    auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
     // If the rounding mode is dynamic, read it from the current state.
     if (rm_value == *FPRoundingMode::kDynamic) {
       if (!rv_fp->rounding_mode_valid()) {
         LOG(ERROR) << "Invalid rounding mode";
-        return *reinterpret_cast<const double *>(
+        return *reinterpret_cast<const double*>(
             &FPTypeInfo<double>::kCanonicalNaN);
       }
       rm_value = *rv_fp->GetRoundingMode();
@@ -122,18 +122,18 @@
 }
 
 // If either operand is NaN return the other.
-void RiscVDMin(const Instruction *instruction) {
+void RiscVDMin(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, double, double>(
       instruction, [instruction](double a, double b) -> double {
         if (FPTypeInfo<double>::IsSNaN(a) || FPTypeInfo<double>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
         if (FPTypeInfo<double>::IsNaN(a)) {
           if (FPTypeInfo<double>::IsNaN(b)) {
             UInt not_a_number = FPTypeInfo<double>::kCanonicalNaN;
-            return *reinterpret_cast<double *>(&not_a_number);
+            return *reinterpret_cast<double*>(&not_a_number);
           }
           return b;
         }
@@ -145,18 +145,18 @@
 }
 
 // If either operand is NaN return the other.
-void RiscVDMax(const Instruction *instruction) {
+void RiscVDMax(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, double, double>(
       instruction, [instruction](double a, double b) {
         if (FPTypeInfo<double>::IsSNaN(a) || FPTypeInfo<double>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
         if (FPTypeInfo<double>::IsNaN(a)) {
           if (FPTypeInfo<double>::IsNaN(b)) {
             UInt not_a_number = FPTypeInfo<double>::kCanonicalNaN;
-            return *reinterpret_cast<double *>(&not_a_number);
+            return *reinterpret_cast<double*>(&not_a_number);
           }
           return b;
         }
@@ -173,14 +173,14 @@
 // Negated multiply-add -((a * b) + c)
 // Negated multiply-subtract -((a * b) - c)
 
-void RiscVDMadd(const Instruction *instruction) {
+void RiscVDMadd(const Instruction* instruction) {
   using T = double;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if (FPTypeInfo<T>::IsNaN(a)) return internal::CanonicalizeNaN(a);
         if (FPTypeInfo<T>::IsNaN(b)) return internal::CanonicalizeNaN(b);
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -189,9 +189,9 @@
         if (c == 0.0) {
           if ((a == 0.0 && !std::isinf(b)) || (b == 0.0 && !std::isinf(a))) {
             UInt c_sign =
-                *reinterpret_cast<UInt *>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
-            UInt ua = *reinterpret_cast<UInt *>(&a);
-            UInt ub = *reinterpret_cast<UInt *>(&b);
+                *reinterpret_cast<UInt*>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
+            UInt ua = *reinterpret_cast<UInt*>(&a);
+            UInt ub = *reinterpret_cast<UInt*>(&b);
             UInt prod_sign = (ua ^ ub) >> (FPTypeInfo<T>::kBitSize - 1);
             if (prod_sign != c_sign) return 0.0;
             return c;
@@ -202,14 +202,14 @@
       });
 }
 
-void RiscVDMsub(const Instruction *instruction) {
+void RiscVDMsub(const Instruction* instruction) {
   using T = double;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if (FPTypeInfo<T>::IsNaN(a)) return internal::CanonicalizeNaN(a);
         if (FPTypeInfo<T>::IsNaN(b)) return internal::CanonicalizeNaN(b);
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -218,9 +218,9 @@
         if (c == 0.0) {
           if ((a == 0.0 && !std::isinf(b)) || (b == 0.0 && !std::isinf(a))) {
             UInt c_sign =
-                -*reinterpret_cast<UInt *>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
-            UInt ua = *reinterpret_cast<UInt *>(&a);
-            UInt ub = *reinterpret_cast<UInt *>(&b);
+                -*reinterpret_cast<UInt*>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
+            UInt ua = *reinterpret_cast<UInt*>(&a);
+            UInt ub = *reinterpret_cast<UInt*>(&b);
             UInt prod_sign = (ua ^ ub) >> (FPTypeInfo<T>::kBitSize - 1);
             if (prod_sign == c_sign) return 0.0;
             return -c;
@@ -231,14 +231,14 @@
       });
 }
 
-void RiscVDNmadd(const Instruction *instruction) {
+void RiscVDNmadd(const Instruction* instruction) {
   using T = double;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if (FPTypeInfo<T>::IsNaN(a)) return internal::CanonicalizeNaN(a);
         if (FPTypeInfo<T>::IsNaN(b)) return internal::CanonicalizeNaN(b);
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -247,9 +247,9 @@
         if (c == 0.0) {
           if ((a == 0.0 && !std::isinf(b)) || (b == 0.0 && !std::isinf(a))) {
             UInt c_sign =
-                *reinterpret_cast<UInt *>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
-            UInt ua = *reinterpret_cast<UInt *>(&a);
-            UInt ub = *reinterpret_cast<UInt *>(&b);
+                *reinterpret_cast<UInt*>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
+            UInt ua = *reinterpret_cast<UInt*>(&a);
+            UInt ub = *reinterpret_cast<UInt*>(&b);
             UInt prod_sign = (ua ^ ub) >> (FPTypeInfo<T>::kBitSize - 1);
             if (prod_sign != c_sign) return 0.0;
             return -c;
@@ -260,7 +260,7 @@
       });
 }
 
-void RiscVDNmsub(const Instruction *instruction) {
+void RiscVDNmsub(const Instruction* instruction) {
   using T = double;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
@@ -269,7 +269,7 @@
         // Illegal operation flag set if either a or b are infinite, and
         // the other is zero.
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -278,9 +278,9 @@
         if (c == 0.0) {
           if ((a == 0.0 && !std::isinf(b)) || (b == 0.0 && !std::isinf(a))) {
             UInt c_sign =
-                -*reinterpret_cast<UInt *>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
-            UInt ua = *reinterpret_cast<UInt *>(&a);
-            UInt ub = *reinterpret_cast<UInt *>(&b);
+                -*reinterpret_cast<UInt*>(&c) >> (FPTypeInfo<T>::kBitSize - 1);
+            UInt ua = *reinterpret_cast<UInt*>(&a);
+            UInt ub = *reinterpret_cast<UInt*>(&b);
             UInt prod_sign = (ua ^ ub) >> (FPTypeInfo<T>::kBitSize - 1);
             if (prod_sign != c_sign) return 0.0;
             return c;
@@ -294,44 +294,44 @@
 // Conversion instructions.
 
 // Convert int to double.
-void RiscVDCvtDw(const Instruction *instruction) {
+void RiscVDCvtDw(const Instruction* instruction) {
   RiscVUnaryFloatOp<double, int32_t>(
       instruction, [](int32_t a) -> double { return static_cast<double>(a); });
 }
 
 // Convert unsigned word to double.
-void RiscVDCvtDwu(const Instruction *instruction) {
+void RiscVDCvtDwu(const Instruction* instruction) {
   RiscVUnaryFloatOp<double, uint32_t>(
       instruction, [](uint32_t a) -> double { return static_cast<double>(a); });
 }
 
 // Convert double to float.
-void RiscVDCvtSd(const Instruction *instruction) {
+void RiscVDCvtSd(const Instruction* instruction) {
   RiscVUnaryFloatNaNBoxOp<RVFpRegister::ValueType, RVFpRegister::ValueType,
                           float, double>(instruction, [](double a) -> float {
     if (FPTypeInfo<double>::IsNaN(a)) {
       typename FPTypeInfo<float>::UIntType uint_value;
       uint_value = FPTypeInfo<float>::kCanonicalNaN;
-      return *reinterpret_cast<float *>(&uint_value);
+      return *reinterpret_cast<float*>(&uint_value);
     }
     return static_cast<float>(a);
   });
 }
 
 // Convert float to double.
-void RiscVDCvtDs(const Instruction *instruction) {
+void RiscVDCvtDs(const Instruction* instruction) {
   RiscVUnaryFloatOp<double, float>(instruction, [](float a) -> double {
     if (FPTypeInfo<float>::IsNaN(a)) {
       typename FPTypeInfo<double>::UIntType uint_value;
       uint_value = FPTypeInfo<double>::kCanonicalNaN;
-      return *reinterpret_cast<double *>(&uint_value);
+      return *reinterpret_cast<double*>(&uint_value);
     }
     return static_cast<double>(a);
   });
 }
 
 // Use sign of the second operand as the sign in the first.
-void RiscVDSgnj(const Instruction *instruction) {
+void RiscVDSgnj(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, UInt, UInt>(
       instruction, [](UInt a, UInt b) -> UInt {
         return (a & 0x7fff'ffff'ffff'ffff) | (b & 0x8000'0000'0000'0000);
@@ -339,7 +339,7 @@
 }
 
 // Use negation of the sign of the second operand as the sign in the first.
-void RiscVDSgnjn(const Instruction *instruction) {
+void RiscVDSgnjn(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, UInt, UInt>(
       instruction, [](UInt a, UInt b) -> UInt {
         return (a & 0x7fff'ffff'ffff'ffff) | (~b & 0x8000'0000'0000'0000);
@@ -347,7 +347,7 @@
 }
 
 // Use the xor of the signs of the two operands as the sign in the first.
-void RiscVDSgnjx(const Instruction *instruction) {
+void RiscVDSgnjx(const Instruction* instruction) {
   RiscVBinaryOp<FPRegister, UInt, UInt>(
       instruction, [](UInt a, UInt b) -> UInt {
         return (a & 0x7fff'ffff'ffff'ffff) | ((a ^ b) & 0x8000'0000'0000'0000);
@@ -360,35 +360,35 @@
 using XInt = std::make_signed<RV32Register::ValueType>::type;
 using XUInt = std::make_unsigned<RV32Register::ValueType>::type;
 
-void RiscVDSd(const Instruction *instruction) {
+void RiscVDSd(const Instruction* instruction) {
   using T = uint64_t;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   if (state->mstatus()->fs() == 0) return;
   XUInt base = generic::GetInstructionSource<XUInt>(instruction, 0);
   XInt offset = generic::GetInstructionSource<XInt>(instruction, 1);
   XUInt address = base + offset;
   T value = generic::GetInstructionSource<T>(instruction, 2);
-  auto *db = state->db_factory()->Allocate(sizeof(T));
+  auto* db = state->db_factory()->Allocate(sizeof(T));
   db->Set<T>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
 }
 
 // Convert double to int.
-void RiscVDCvtWd(const Instruction *instruction) {
+void RiscVDCvtWd(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, double, int32_t>(instruction);
 }
 // Convert double to unsigned word.
-void RiscVDCvtWud(const Instruction *instruction) {
+void RiscVDCvtWud(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XUInt, double, uint32_t>(instruction);
 }
 
 // Double precision floating point compare equal.
-void RiscVDCmpeq(const Instruction *instruction) {
+void RiscVDCmpeq(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, uint32_t, double>(
       instruction, [instruction](double a, double b) -> uint32_t {
         if (FPTypeInfo<double>::IsSNaN(a) || FPTypeInfo<double>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -397,11 +397,11 @@
 }
 
 // Double precision floating point compare less.
-void RiscVDCmplt(const Instruction *instruction) {
+void RiscVDCmplt(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, uint32_t, double>(
       instruction, [instruction](double a, double b) -> uint32_t {
         if (FPTypeInfo<double>::IsNaN(a) || FPTypeInfo<double>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -410,11 +410,11 @@
 }
 
 // Double precision floating point compare less than or equal.
-void RiscVDCmple(const Instruction *instruction) {
+void RiscVDCmple(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, uint32_t, double>(
       instruction, [instruction](double a, double b) -> uint32_t {
         if (FPTypeInfo<double>::IsNaN(a) || FPTypeInfo<double>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -423,7 +423,7 @@
 }
 
 // Return the class attribute of the source operand.
-void RiscVDClass(const Instruction *instruction) {
+void RiscVDClass(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, XUInt, double>(instruction, [](double a) -> XUInt {
     auto res = static_cast<XUInt>(ClassifyFP(a));
     return res;
@@ -438,35 +438,35 @@
 using XInt = std::make_signed<RV64Register::ValueType>::type;
 using XUInt = std::make_unsigned<RV64Register::ValueType>::type;
 
-void RiscVDSd(const Instruction *instruction) {
+void RiscVDSd(const Instruction* instruction) {
   using T = uint64_t;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   if (state->mstatus()->fs() == 0) return;
   XUInt base = generic::GetInstructionSource<XUInt>(instruction, 0);
   XInt offset = generic::GetInstructionSource<XInt>(instruction, 1);
   XUInt address = base + offset;
   T value = generic::GetInstructionSource<T>(instruction, 2);
-  auto *db = state->db_factory()->Allocate(sizeof(T));
+  auto* db = state->db_factory()->Allocate(sizeof(T));
   db->Set<T>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
 }
 
 // Convert double to int.
-void RiscVDCvtWd(const Instruction *instruction) {
+void RiscVDCvtWd(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, double, int32_t>(instruction);
 }
 // Convert double to unsigned word.
-void RiscVDCvtWud(const Instruction *instruction) {
+void RiscVDCvtWud(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XUInt, double, uint32_t>(instruction);
 }
 
 // Double precision floating point compare equal.
-void RiscVDCmpeq(const Instruction *instruction) {
+void RiscVDCmpeq(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, XUInt, double>(
       instruction, [instruction](double a, double b) -> XUInt {
         if (FPTypeInfo<double>::IsSNaN(a) || FPTypeInfo<double>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -475,11 +475,11 @@
 }
 
 // Double precision floating point compare less.
-void RiscVDCmplt(const Instruction *instruction) {
+void RiscVDCmplt(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, XUInt, double>(
       instruction, [instruction](double a, double b) -> XUInt {
         if (FPTypeInfo<double>::IsNaN(a) || FPTypeInfo<double>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -488,11 +488,11 @@
 }
 
 // Double precision floating point compare less than or equal.
-void RiscVDCmple(const Instruction *instruction) {
+void RiscVDCmple(const Instruction* instruction) {
   RiscVBinaryOp<XRegister, XUInt, double>(
       instruction, [instruction](double a, double b) -> XUInt {
         if (FPTypeInfo<double>::IsNaN(a) || FPTypeInfo<double>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -501,7 +501,7 @@
 }
 
 // Return the class attribute of the source operand.
-void RiscVDClass(const Instruction *instruction) {
+void RiscVDClass(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, UInt, double>(instruction, [](double a) -> UInt {
     auto res = static_cast<UInt>(ClassifyFP(a));
     return res;
@@ -509,33 +509,33 @@
 }
 
 // Convert double to 64 bit signed integer.
-void RiscVDCvtLd(const Instruction *instruction) {
+void RiscVDCvtLd(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, double, int64_t>(instruction);
 }
 
 // Convert double to 64 bit unsigned integer.
-void RiscVDCvtLud(const Instruction *instruction) {
+void RiscVDCvtLud(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, double, uint64_t>(instruction);
 }
 
 // Convert signed 64 bit integer to double.
-void RiscVDCvtDl(const Instruction *instruction) {
+void RiscVDCvtDl(const Instruction* instruction) {
   RiscVUnaryFloatOp<double, int64_t>(
       instruction, [](int64_t a) -> double { return static_cast<double>(a); });
 }
 
 // Convert unsigned 64 bit integer to double.
-void RiscVDCvtDlu(const Instruction *instruction) {
+void RiscVDCvtDlu(const Instruction* instruction) {
   RiscVUnaryFloatOp<double, uint64_t>(
       instruction, [](uint64_t a) -> double { return static_cast<double>(a); });
 }
 
-void RiscVDMvxd(const Instruction *instruction) {
+void RiscVDMvxd(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, uint64_t, uint64_t>(
       instruction, [](uint64_t a) -> uint64_t { return a; });
 }
 
-void RiscVDMvdx(const Instruction *instruction) {
+void RiscVDMvdx(const Instruction* instruction) {
   RiscVUnaryOp<FPRegister, uint64_t, uint64_t>(
       instruction, [](uint64_t a) -> uint64_t { return a; });
 }
diff --git a/riscv/riscv_d_instructions.h b/riscv/riscv_d_instructions.h
index 81419a9..7d944f4 100644
--- a/riscv/riscv_d_instructions.h
+++ b/riscv/riscv_d_instructions.h
@@ -29,54 +29,54 @@
 // Double precision arithmetic instructions each take 3 source operands and
 // 1 destination register operand. Source 0 and 1 are the data sources to the
 // operation, source 2 is the rounding mode specifier in the instruction.
-void RiscVDAdd(const Instruction *instruction);
-void RiscVDSub(const Instruction *instruction);
-void RiscVDMul(const Instruction *instruction);
-void RiscVDDiv(const Instruction *instruction);
+void RiscVDAdd(const Instruction* instruction);
+void RiscVDSub(const Instruction* instruction);
+void RiscVDMul(const Instruction* instruction);
+void RiscVDDiv(const Instruction* instruction);
 // Double precision square root takes 2 source operands, the source register
 // and the rounding mode, and 1 destination register operand.
-void RiscVDSqrt(const Instruction *instruction);
+void RiscVDSqrt(const Instruction* instruction);
 // The double precision Min and Max instructions each take 2 source register
 // operands and 1 destination register operand.
-void RiscVDMin(const Instruction *instruction);
-void RiscVDMax(const Instruction *instruction);
+void RiscVDMin(const Instruction* instruction);
+void RiscVDMax(const Instruction* instruction);
 // The following four multiply-accumulate instruction each take 3 source
 // register operands (0, 1, 2) and the rounding mode (3), and one destination
 // register operand.
-void RiscVDMadd(const Instruction *instruction);
-void RiscVDMsub(const Instruction *instruction);
-void RiscVDNmadd(const Instruction *instruction);
-void RiscVDNmsub(const Instruction *instruction);
+void RiscVDMadd(const Instruction* instruction);
+void RiscVDMsub(const Instruction* instruction);
+void RiscVDNmadd(const Instruction* instruction);
+void RiscVDNmsub(const Instruction* instruction);
 // The double precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVDCvtDw(const Instruction *instruction);
-void RiscVDCvtDwu(const Instruction *instruction);
-void RiscVDCvtSd(const Instruction *instruction);
-void RiscVDCvtDs(const Instruction *instruction);
+void RiscVDCvtDw(const Instruction* instruction);
+void RiscVDCvtDwu(const Instruction* instruction);
+void RiscVDCvtSd(const Instruction* instruction);
+void RiscVDCvtDs(const Instruction* instruction);
 // The double precision sign manipulation instructions take 2 source register
 // operands and a single destination register operand.
-void RiscVDSgnj(const Instruction *instruction);
-void RiscVDSgnjn(const Instruction *instruction);
-void RiscVDSgnjx(const Instruction *instruction);
+void RiscVDSgnj(const Instruction* instruction);
+void RiscVDSgnjn(const Instruction* instruction);
+void RiscVDSgnjx(const Instruction* instruction);
 
 namespace RV32 {
 
 // Store float instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVDSd(const Instruction *instruction);
+void RiscVDSd(const Instruction* instruction);
 // The double precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVDCvtWd(const Instruction *instruction);
-void RiscVDCvtWud(const Instruction *instruction);
+void RiscVDCvtWd(const Instruction* instruction);
+void RiscVDCvtWud(const Instruction* instruction);
 // The double precision compare instructions take 2 source register operands
 // and a single destination register operand.
-void RiscVDCmpeq(const Instruction *instruction);
-void RiscVDCmplt(const Instruction *instruction);
-void RiscVDCmple(const Instruction *instruction);
+void RiscVDCmpeq(const Instruction* instruction);
+void RiscVDCmplt(const Instruction* instruction);
+void RiscVDCmple(const Instruction* instruction);
 // The double precision class instruction takes a single source register operand
 // and a single destination register operand.
-void RiscVDClass(const Instruction *instruction);
+void RiscVDClass(const Instruction* instruction);
 
 }  // namespace RV32
 
@@ -86,30 +86,30 @@
 // Store float instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVDSd(const Instruction *instruction);
+void RiscVDSd(const Instruction* instruction);
 // The double precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVDCvtWd(const Instruction *instruction);
-void RiscVDCvtWud(const Instruction *instruction);
+void RiscVDCvtWd(const Instruction* instruction);
+void RiscVDCvtWud(const Instruction* instruction);
 // The double precision compare instructions take 2 source register operands
 // and a single destination register operand.
-void RiscVDCmpeq(const Instruction *instruction);
-void RiscVDCmplt(const Instruction *instruction);
-void RiscVDCmple(const Instruction *instruction);
+void RiscVDCmpeq(const Instruction* instruction);
+void RiscVDCmplt(const Instruction* instruction);
+void RiscVDCmple(const Instruction* instruction);
 // The double precision class instruction takes a single source register operand
 // and a single destination register operand.
-void RiscVDClass(const Instruction *instruction);
+void RiscVDClass(const Instruction* instruction);
 
 // The double precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVDCvtLd(const Instruction *instruction);
-void RiscVDCvtLud(const Instruction *instruction);
-void RiscVDCvtDl(const Instruction *instruction);
-void RiscVDCvtDlu(const Instruction *instruction);
+void RiscVDCvtLd(const Instruction* instruction);
+void RiscVDCvtLud(const Instruction* instruction);
+void RiscVDCvtDl(const Instruction* instruction);
+void RiscVDCvtDlu(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
 // destination register operand.
-void RiscVDMvxd(const Instruction *instruction);
-void RiscVDMvdx(const Instruction *instruction);
+void RiscVDMvxd(const Instruction* instruction);
+void RiscVDMvdx(const Instruction* instruction);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_debug_info.cc b/riscv/riscv_debug_info.cc
index 798b8b7..b7bbc87 100644
--- a/riscv/riscv_debug_info.cc
+++ b/riscv/riscv_debug_info.cc
@@ -222,8 +222,8 @@
                            {*DebugRegisterEnum::kV30, kV30Name},
                            {*DebugRegisterEnum::kV31, kV31Name}}) {}
 
-RiscVDebugInfo *RiscVDebugInfo::Instance() {
-  static RiscVDebugInfo *instance_ = nullptr;
+RiscVDebugInfo* RiscVDebugInfo::Instance() {
+  static RiscVDebugInfo* instance_ = nullptr;
   if (instance_ == nullptr) {
     instance_ = new RiscVDebugInfo();
   }
diff --git a/riscv/riscv_encoding_common.h b/riscv/riscv_encoding_common.h
index c578361..8e99e9b 100644
--- a/riscv/riscv_encoding_common.h
+++ b/riscv/riscv_encoding_common.h
@@ -34,8 +34,8 @@
   virtual ~RiscVEncodingCommon() = default;
 
   // Accessors.
-  virtual RiscVState *state() const = 0;
-  virtual generic::SimpleResourcePool *resource_pool() = 0;
+  virtual RiscVState* state() const = 0;
+  virtual generic::SimpleResourcePool* resource_pool() = 0;
   virtual uint32_t inst_word() const = 0;
 };
 
diff --git a/riscv/riscv_f_instructions.cc b/riscv/riscv_f_instructions.cc
index 34b572a..8f4257c 100644
--- a/riscv/riscv_f_instructions.cc
+++ b/riscv/riscv_f_instructions.cc
@@ -58,37 +58,37 @@
 
 // Convert float to signed 32 bit integer.
 template <typename XInt>
-static inline void RVFCvtWs(const Instruction *instruction) {
+static inline void RVFCvtWs(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, float, int32_t>(instruction);
 }
 
 // Convert float to unsigned 32 bit integer.
 template <typename XUint>
-static inline void RVFCvtWus(const Instruction *instruction) {
+static inline void RVFCvtWus(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XUint, float, uint32_t>(instruction);
 }
 
 // Convert float to signed 64 bit integer.
 template <typename XInt>
-static inline void RVFCvtLs(const Instruction *instruction) {
+static inline void RVFCvtLs(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XInt, float, int64_t>(instruction);
 }
 
 // Convert float to unsigned 64 bit integer.
 template <typename XUint>
-static inline void RVFCvtLus(const Instruction *instruction) {
+static inline void RVFCvtLus(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<XUint, float, uint64_t>(instruction);
 }
 
 // Single precision compare equal.
 template <typename XRegister>
-static inline void RVFCmpeq(const Instruction *instruction) {
+static inline void RVFCmpeq(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<typename XRegister::ValueType,
                       typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -98,13 +98,13 @@
 
 // Single precicion compare less than.
 template <typename XRegister>
-static inline void RVFCmplt(const Instruction *instruction) {
+static inline void RVFCmplt(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<typename XRegister::ValueType,
                       typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsNaN(a) || FPTypeInfo<float>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -114,13 +114,13 @@
 
 // Single precision compare less than or equal.
 template <typename XRegister>
-static inline void RVFCmple(const Instruction *instruction) {
+static inline void RVFCmple(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<typename XRegister::ValueType,
                       typename XRegister::ValueType, float>(
       instruction,
       [instruction](float a, float b) -> typename XRegister::ValueType {
         if (FPTypeInfo<float>::IsNaN(a) || FPTypeInfo<float>::IsNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -132,17 +132,17 @@
 static inline T CanonicalizeNaN(T value) {
   if (!std::isnan(value)) return value;
   auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-  return *reinterpret_cast<T *>(&nan_value);
+  return *reinterpret_cast<T*>(&nan_value);
 }
 
 }  // namespace internal
 
 // Load child instruction.
-void RiscVIFlwChild(const Instruction *instruction) {
-  LoadContext *context = static_cast<LoadContext *>(instruction->context());
+void RiscVIFlwChild(const Instruction* instruction) {
+  LoadContext* context = static_cast<LoadContext*>(instruction->context());
   auto value = context->value_db->Get<FPUInt>(0);
-  auto *reg =
-      static_cast<generic::RegisterDestinationOperand<FPRegister::ValueType> *>(
+  auto* reg =
+      static_cast<generic::RegisterDestinationOperand<FPRegister::ValueType>*>(
           instruction->Destination(0))
           ->GetRegister();
   if (sizeof(FPRegister::ValueType) > sizeof(FPUInt)) {
@@ -157,40 +157,39 @@
 }
 
 // Basic arithmetic instructions.
-void RiscVFAdd(const Instruction *instruction) {
+void RiscVFAdd(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a + b; });
 }
 
-void RiscVFSub(const Instruction *instruction) {
+void RiscVFSub(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a - b; });
 }
 
-void RiscVFMul(const Instruction *instruction) {
+void RiscVFMul(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a * b; });
 }
 
-void RiscVFDiv(const Instruction *instruction) {
+void RiscVFDiv(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [](float a, float b) { return a / b; });
 }
 
 // Square root uses the library square root, but check for special conditions
 // to set flags that may not be set correctly with the library version.
-void RiscVFSqrt(const Instruction *instruction) {
+void RiscVFSqrt(const Instruction* instruction) {
   RiscVUnaryNaNBoxOp<FPRegister::ValueType, FPRegister::ValueType, float,
                      float>(instruction, [instruction](float a) -> float {
     // If the input value is NaN or less than zero, set the invalid op flag.
     if (FPTypeInfo<float>::IsNaN(a) || (a < 0.0)) {
       if (!FPTypeInfo<float>::IsQNaN(a)) {
-        auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+        auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
         flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
         flag_db->Submit();
       }
-      return *reinterpret_cast<const float *>(
-          &FPTypeInfo<float>::kCanonicalNaN);
+      return *reinterpret_cast<const float*>(&FPTypeInfo<float>::kCanonicalNaN);
     }
 
     // Square root of 0 returns 0, and of -0.0 returns -0.0.
@@ -200,12 +199,12 @@
     // Get the rounding mode.
     int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-    auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+    auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
     // If the rounding mode is dynamic, read it from the current state.
     if (rm_value == *FPRoundingMode::kDynamic) {
       if (!rv_fp->rounding_mode_valid()) {
         LOG(ERROR) << "Invalid rounding mode";
-        return *reinterpret_cast<const float *>(
+        return *reinterpret_cast<const float*>(
             &FPTypeInfo<float>::kCanonicalNaN);
       }
       rm_value = *rv_fp->GetRoundingMode();
@@ -220,11 +219,11 @@
 }
 
 // If either operand is NaN return the other.
-void RiscVFMin(const Instruction *instruction) {
+void RiscVFMin(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [instruction](float a, float b) -> float {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -232,7 +231,7 @@
           if (FPTypeInfo<float>::IsNaN(b)) {
             FPTypeInfo<float>::UIntType not_a_number =
                 FPTypeInfo<float>::kCanonicalNaN;
-            return *reinterpret_cast<float *>(&not_a_number);
+            return *reinterpret_cast<float*>(&not_a_number);
           }
           return b;
         }
@@ -246,11 +245,11 @@
 }
 
 // If either operand is NaN return the other.
-void RiscVFMax(const Instruction *instruction) {
+void RiscVFMax(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<FPRegister::ValueType, float, float>(
       instruction, [instruction](float a, float b) -> float {
         if (FPTypeInfo<float>::IsSNaN(a) || FPTypeInfo<float>::IsSNaN(b)) {
-          auto *db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* db = instruction->Destination(1)->AllocateDataBuffer();
           db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           db->Submit();
         }
@@ -258,7 +257,7 @@
           if (FPTypeInfo<float>::IsNaN(b)) {
             FPTypeInfo<float>::UIntType not_a_number =
                 FPTypeInfo<float>::kCanonicalNaN;
-            return *reinterpret_cast<float *>(&not_a_number);
+            return *reinterpret_cast<float*>(&not_a_number);
           }
           return b;
         }
@@ -275,13 +274,13 @@
 // Negated multiply-add -((a * b) + c)
 // Negated multiply-subtract -((a * b) - c)
 
-void RiscVFMadd(const Instruction *instruction) {
+void RiscVFMadd(const Instruction* instruction) {
   using T = float;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         // Propagate any NaNs.
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -289,12 +288,12 @@
       });
 }
 
-void RiscVFMsub(const Instruction *instruction) {
+void RiscVFMsub(const Instruction* instruction) {
   using T = float;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -302,12 +301,12 @@
       });
 }
 
-void RiscVFNmadd(const Instruction *instruction) {
+void RiscVFNmadd(const Instruction* instruction) {
   using T = float;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -315,12 +314,12 @@
       });
 }
 
-void RiscVFNmsub(const Instruction *instruction) {
+void RiscVFNmsub(const Instruction* instruction) {
   using T = float;
   RiscVTernaryFloatNaNBoxOp<FPRegister::ValueType, T, T>(
       instruction, [instruction](T a, T b, T c) -> T {
         if ((std::isinf(a) && (b == 0.0)) || ((std::isinf(b) && (a == 0.0)))) {
-          auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+          auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
           flag_db->Set<uint32_t>(0, *FPExceptions::kInvalidOp);
           flag_db->Submit();
         }
@@ -329,14 +328,14 @@
 }
 
 // Set sign of the first operand to that of the second.
-void RiscVFSgnj(const Instruction *instruction) {
+void RiscVFSgnj(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction,
       [](FPUInt a, FPUInt b) { return (a & 0x7fff'ffff) | (b & 0x8000'0000); });
 }
 
 // Set the sign of the first operand to the opposite of the second.
-void RiscVFSgnjn(const Instruction *instruction) {
+void RiscVFSgnjn(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction, [](FPUInt a, FPUInt b) {
         return (a & 0x7fff'ffff) | (~b & 0x8000'0000);
@@ -345,7 +344,7 @@
 
 // Set the sign of the first operand to the xor of the signs of the two
 // operands.
-void RiscVFSgnjx(const Instruction *instruction) {
+void RiscVFSgnjx(const Instruction* instruction) {
   RiscVBinaryNaNBoxOp<FPRegister::ValueType, FPUInt, FPUInt>(
       instruction, [](FPUInt a, FPUInt b) {
         return (a & 0x7fff'ffff) | ((a ^ b) & 0x8000'0000);
@@ -353,31 +352,31 @@
 }
 
 // Convert signed 32 bit integer to float.
-void RiscVFCvtSw(const Instruction *instruction) {
+void RiscVFCvtSw(const Instruction* instruction) {
   RiscVUnaryFloatNaNBoxOp<FPRegister::ValueType, uint32_t, float, int32_t>(
       instruction, [](int32_t a) -> float { return static_cast<float>(a); });
 }
 
 // Convert unsigned 32 bit integer to float.
-void RiscVFCvtSwu(const Instruction *instruction) {
+void RiscVFCvtSwu(const Instruction* instruction) {
   RiscVUnaryFloatNaNBoxOp<FPRegister::ValueType, uint32_t, float, uint32_t>(
       instruction, [](uint32_t a) -> float { return static_cast<float>(a); });
 }
 
 // Convert signed 64 bit integer to float.
-void RiscVFCvtSl(const Instruction *instruction) {
+void RiscVFCvtSl(const Instruction* instruction) {
   RiscVUnaryFloatNaNBoxOp<FPRegister::ValueType, uint64_t, float, int64_t>(
       instruction, [](int64_t a) -> float { return static_cast<float>(a); });
 }
 
 // Convert unsigned 64 bit integer to float.
-void RiscVFCvtSlu(const Instruction *instruction) {
+void RiscVFCvtSlu(const Instruction* instruction) {
   RiscVUnaryFloatNaNBoxOp<FPRegister::ValueType, uint64_t, float, uint64_t>(
       instruction, [](uint64_t a) -> float { return static_cast<float>(a); });
 }
 
 // Single precision move instruction from integer to fp register file.
-void RiscVFMvwx(const Instruction *instruction) {
+void RiscVFMvwx(const Instruction* instruction) {
   RiscVUnaryNaNBoxOp<FPRegister::ValueType, uint32_t, uint32_t, uint32_t>(
       instruction, [](uint32_t a) -> uint32_t { return a; });
 }
@@ -388,15 +387,15 @@
 using XUint = typename std::make_unsigned<XRegister::ValueType>::type;
 using XInt = typename std::make_signed<XRegister::ValueType>::type;
 
-void RiscVFSw(const Instruction *instruction) {
+void RiscVFSw(const Instruction* instruction) {
   using T = uint32_t;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   if (state->mstatus()->fs() == 0) return;
   XUint base = generic::GetInstructionSource<XUint>(instruction, 0);
   XInt offset = generic::GetInstructionSource<XInt>(instruction, 1);
   XUint address = base + offset;
   T value = generic::GetInstructionSource<T>(instruction, 2);
-  auto *db = state->db_factory()->Allocate(sizeof(T));
+  auto* db = state->db_factory()->Allocate(sizeof(T));
   db->Set<T>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
@@ -405,39 +404,39 @@
 // Single precision conversion instructions.
 
 // Convert float to signed 32 bit integer.
-void RiscVFCvtWs(const Instruction *instruction) {
+void RiscVFCvtWs(const Instruction* instruction) {
   internal::RVFCvtWs<XInt>(instruction);
 }
 
 // Convert float to unsigned 32 bit integer.
-void RiscVFCvtWus(const Instruction *instruction) {
+void RiscVFCvtWus(const Instruction* instruction) {
   internal::RVFCvtWus<XUint>(instruction);
 }
 
 // Single precision move instruction to integer register file, with
 // sign-extension.
-void RiscVFMvxw(const Instruction *instruction) {
+void RiscVFMvxw(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, int32_t, int32_t>(instruction,
                                             [](int32_t a) { return a; });
 }
 
 // Single precision compare equal.
-void RiscVFCmpeq(const Instruction *instruction) {
+void RiscVFCmpeq(const Instruction* instruction) {
   internal::RVFCmpeq<XRegister>(instruction);
 }
 
 // Single precicion compare less than.
-void RiscVFCmplt(const Instruction *instruction) {
+void RiscVFCmplt(const Instruction* instruction) {
   internal::RVFCmplt<XRegister>(instruction);
 }
 
 // Single precision compare less than or equal.
-void RiscVFCmple(const Instruction *instruction) {
+void RiscVFCmple(const Instruction* instruction) {
   internal::RVFCmple<XRegister>(instruction);
 }
 
 // Single precision fp class instruction.
-void RiscVFClass(const Instruction *instruction) {
+void RiscVFClass(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, uint32_t, float>(
       instruction,
       [](float a) -> uint32_t { return static_cast<uint32_t>(ClassifyFP(a)); });
@@ -451,70 +450,70 @@
 using XUint = typename std::make_unsigned<XRegister::ValueType>::type;
 using XInt = typename std::make_signed<XRegister::ValueType>::type;
 
-void RiscVFSw(const Instruction *instruction) {
+void RiscVFSw(const Instruction* instruction) {
   using T = uint32_t;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   if (state->mstatus()->fs() == 0) return;
   XUint base = generic::GetInstructionSource<XUint>(instruction, 0);
   XInt offset = generic::GetInstructionSource<XInt>(instruction, 1);
   XUint address = base + offset;
   T value = generic::GetInstructionSource<T>(instruction, 2);
-  auto *db = state->db_factory()->Allocate(sizeof(T));
+  auto* db = state->db_factory()->Allocate(sizeof(T));
   db->Set<T>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
 }
 
 // Convert float to signed 32 bit integer in a 64 bit register.
-void RiscVFCvtWs(const Instruction *instruction) {
+void RiscVFCvtWs(const Instruction* instruction) {
   internal::RVFCvtWs<XInt>(instruction);
 }
 
 // Convert float to unsigned 32 bit integer in a 64 bit register.
-void RiscVFCvtWus(const Instruction *instruction) {
+void RiscVFCvtWus(const Instruction* instruction) {
   internal::RVFCvtWus<XUint>(instruction);
 }
 
 // Convert float to signed 64 bit integer.
-void RiscVFCvtLs(const Instruction *instruction) {
+void RiscVFCvtLs(const Instruction* instruction) {
   internal::RVFCvtLs<XInt>(instruction);
 }
 
 // Convert float to unsigned 64 bit integer.
-void RiscVFCvtLus(const Instruction *instruction) {
+void RiscVFCvtLus(const Instruction* instruction) {
   internal::RVFCvtLus<XUint>(instruction);
 }
 
 // Single precision move instruction to integer register file, with
 // sign-extension.
-void RiscVFMvxw(const Instruction *instruction) {
+void RiscVFMvxw(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, XInt, int32_t>(
       instruction, [](int32_t a) { return static_cast<XInt>(a); });
 }
 
 // Single precision move instruction from integer to fp register file.
-void RiscVFMvwx(const Instruction *instruction) {
+void RiscVFMvwx(const Instruction* instruction) {
   RiscVUnaryNaNBoxOp<FPRegister::ValueType, uint32_t, uint32_t, uint32_t>(
       instruction, [](uint32_t a) -> uint32_t { return a; });
 }
 
 // Single precision compare equal.
-void RiscVFCmpeq(const Instruction *instruction) {
+void RiscVFCmpeq(const Instruction* instruction) {
   internal::RVFCmpeq<XRegister>(instruction);
 }
 
 // Single precicion compare less than.
-void RiscVFCmplt(const Instruction *instruction) {
+void RiscVFCmplt(const Instruction* instruction) {
   internal::RVFCmplt<XRegister>(instruction);
 }
 
 // Single precision compare less than or equal.
-void RiscVFCmple(const Instruction *instruction) {
+void RiscVFCmple(const Instruction* instruction) {
   internal::RVFCmple<XRegister>(instruction);
 }
 
 // Single precision fp class instruction.
-void RiscVFClass(const Instruction *instruction) {
+void RiscVFClass(const Instruction* instruction) {
   RiscVUnaryOp<XRegister, uint32_t, float>(
       instruction,
       [](float a) -> uint32_t { return static_cast<uint32_t>(ClassifyFP(a)); });
diff --git a/riscv/riscv_f_instructions.h b/riscv/riscv_f_instructions.h
index e232c59..48deed2 100644
--- a/riscv/riscv_f_instructions.h
+++ b/riscv/riscv_f_instructions.h
@@ -29,62 +29,62 @@
 // Single precision arithmetic instructions each take 3 source operands and
 // 1 destination register operand. Source 0 and 1 are the data sources to the
 // operation, source 2 is the rounding mode specifier in the instruction.
-void RiscVFAdd(const Instruction *instruction);
-void RiscVFSub(const Instruction *instruction);
-void RiscVFMul(const Instruction *instruction);
-void RiscVFDiv(const Instruction *instruction);
+void RiscVFAdd(const Instruction* instruction);
+void RiscVFSub(const Instruction* instruction);
+void RiscVFMul(const Instruction* instruction);
+void RiscVFDiv(const Instruction* instruction);
 // Single precision load child instruction takes a single destination operand.
-void RiscVIFlwChild(const Instruction *instruction);
+void RiscVIFlwChild(const Instruction* instruction);
 // Single precision square root takes 2 source operands, the source register
 // and the rounding mode, and 1 destination register operand.
-void RiscVFSqrt(const Instruction *instruction);
+void RiscVFSqrt(const Instruction* instruction);
 // The single precision Min and Max instructions each take 2 source register
 // operands and 1 destination register operand.
-void RiscVFMin(const Instruction *instruction);
-void RiscVFMax(const Instruction *instruction);
+void RiscVFMin(const Instruction* instruction);
+void RiscVFMax(const Instruction* instruction);
 // The following four multiply-accumulate instruction each take 3 source
 // register operands (0, 1, 2) and the rounding mode (3), and one destination
 // register operand.
-void RiscVFMadd(const Instruction *instruction);
-void RiscVFMsub(const Instruction *instruction);
-void RiscVFNmadd(const Instruction *instruction);
-void RiscVFNmsub(const Instruction *instruction);
+void RiscVFMadd(const Instruction* instruction);
+void RiscVFMsub(const Instruction* instruction);
+void RiscVFNmadd(const Instruction* instruction);
+void RiscVFNmsub(const Instruction* instruction);
 // The single precision sign manipulation instructions take 2 source register
 // operands and a single destination register operand.
-void RiscVFSgnj(const Instruction *instruction);
-void RiscVFSgnjn(const Instruction *instruction);
-void RiscVFSgnjx(const Instruction *instruction);
+void RiscVFSgnj(const Instruction* instruction);
+void RiscVFSgnjn(const Instruction* instruction);
+void RiscVFSgnjx(const Instruction* instruction);
 // The single precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVFCvtSw(const Instruction *instruction);
-void RiscVFCvtSwu(const Instruction *instruction);
-void RiscVFCvtSl(const Instruction *instruction);
-void RiscVFCvtSlu(const Instruction *instruction);
+void RiscVFCvtSw(const Instruction* instruction);
+void RiscVFCvtSwu(const Instruction* instruction);
+void RiscVFCvtSl(const Instruction* instruction);
+void RiscVFCvtSlu(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
-void RiscVFMvwx(const Instruction *instruction);
+void RiscVFMvwx(const Instruction* instruction);
 
 namespace RV32 {
 
 // Store float instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVFSw(const Instruction *instruction);
+void RiscVFSw(const Instruction* instruction);
 // Single precision load child instruction takes a single destination operand.
 // The single precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVFCvtWs(const Instruction *instruction);
-void RiscVFCvtWus(const Instruction *instruction);
+void RiscVFCvtWs(const Instruction* instruction);
+void RiscVFCvtWus(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
 // destination register operand.
-void RiscVFMvxw(const Instruction *instruction);
+void RiscVFMvxw(const Instruction* instruction);
 // The single precision compare instructions take 2 source register operands
 // and a single destination register operand.
-void RiscVFCmpeq(const Instruction *instruction);
-void RiscVFCmplt(const Instruction *instruction);
-void RiscVFCmple(const Instruction *instruction);
+void RiscVFCmpeq(const Instruction* instruction);
+void RiscVFCmplt(const Instruction* instruction);
+void RiscVFCmple(const Instruction* instruction);
 // The single precision class instruction takes a single source register operand
 // and a single destination register operand.
-void RiscVFClass(const Instruction *instruction);
+void RiscVFClass(const Instruction* instruction);
 
 }  // namespace RV32
 
@@ -93,25 +93,25 @@
 // Store float instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVFSw(const Instruction *instruction);
+void RiscVFSw(const Instruction* instruction);
 // Single precision load child instruction takes a single destination operand.
 // The single precision conversion instructions each take 1 source register
 // operand, the rounding mode, and 1 destination register operand.
-void RiscVFCvtWs(const Instruction *instruction);
-void RiscVFCvtWus(const Instruction *instruction);
-void RiscVFCvtLs(const Instruction *instruction);
-void RiscVFCvtLus(const Instruction *instruction);
+void RiscVFCvtWs(const Instruction* instruction);
+void RiscVFCvtWus(const Instruction* instruction);
+void RiscVFCvtLs(const Instruction* instruction);
+void RiscVFCvtLus(const Instruction* instruction);
 // The move instruction takes a single register source operand and a single
 // destination register operand.
-void RiscVFMvxw(const Instruction *instruction);
+void RiscVFMvxw(const Instruction* instruction);
 // The single precision compare instructions take 2 source register operands
 // and a single destination register operand.
-void RiscVFCmpeq(const Instruction *instruction);
-void RiscVFCmplt(const Instruction *instruction);
-void RiscVFCmple(const Instruction *instruction);
+void RiscVFCmpeq(const Instruction* instruction);
+void RiscVFCmplt(const Instruction* instruction);
+void RiscVFCmple(const Instruction* instruction);
 // The single precision class instruction takes a single source register operand
 // and a single destination register operand.
-void RiscVFClass(const Instruction *instruction);
+void RiscVFClass(const Instruction* instruction);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_fp_host.h b/riscv/riscv_fp_host.h
index 044de96..0459309 100644
--- a/riscv/riscv_fp_host.h
+++ b/riscv/riscv_fp_host.h
@@ -32,7 +32,7 @@
   virtual void SetRiscVFcsr(uint32_t riscv_fcsr) = 0;
 };
 
-HostFloatingPointInterface *GetHostFloatingPointInterface();
+HostFloatingPointInterface* GetHostFloatingPointInterface();
 
 // This class is used to set the native fp status and rounding mode to the
 // current simulated status and rounding mode, and then copying the native
@@ -40,13 +40,13 @@
 class ScopedFPStatus {
  public:
   ScopedFPStatus() = delete;
-  explicit ScopedFPStatus(HostFloatingPointInterface *fp_interface);
-  ScopedFPStatus(HostFloatingPointInterface *fp_interface, uint32_t rm);
-  ScopedFPStatus(HostFloatingPointInterface *fp_interface, FPRoundingMode rm);
+  explicit ScopedFPStatus(HostFloatingPointInterface* fp_interface);
+  ScopedFPStatus(HostFloatingPointInterface* fp_interface, uint32_t rm);
+  ScopedFPStatus(HostFloatingPointInterface* fp_interface, FPRoundingMode rm);
   ~ScopedFPStatus();
 
  private:
-  HostFloatingPointInterface *fp_interface_ = nullptr;
+  HostFloatingPointInterface* fp_interface_ = nullptr;
   uint32_t host_rm_ = 0;
   uint64_t cpu_fp_status_ = 0;
 };
@@ -56,9 +56,9 @@
 class ScopedFPRoundingMode {
  public:
   ScopedFPRoundingMode();
-  explicit ScopedFPRoundingMode(HostFloatingPointInterface *fp_interface);
-  ScopedFPRoundingMode(HostFloatingPointInterface *fp_interface, uint32_t rm);
-  ScopedFPRoundingMode(HostFloatingPointInterface *fp_interface,
+  explicit ScopedFPRoundingMode(HostFloatingPointInterface* fp_interface);
+  ScopedFPRoundingMode(HostFloatingPointInterface* fp_interface, uint32_t rm);
+  ScopedFPRoundingMode(HostFloatingPointInterface* fp_interface,
                        FPRoundingMode rm);
   ~ScopedFPRoundingMode();
 
diff --git a/riscv/riscv_fp_host_arm.cc b/riscv/riscv_fp_host_arm.cc
index a18ded8..aaf9b73 100644
--- a/riscv/riscv_fp_host_arm.cc
+++ b/riscv/riscv_fp_host_arm.cc
@@ -12,7 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "absl/log/log.h"
+#include <cstdint>
+
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv/riscv_fp_host.h"
 #include "riscv/riscv_fp_info.h"
@@ -170,13 +171,13 @@
 };
 
 // Factory function.
-HostFloatingPointInterface *GetHostFloatingPointInterface() {
+HostFloatingPointInterface* GetHostFloatingPointInterface() {
   return new ArmFloatingPointInterface();
 }
 
 #pragma STDC FENV_ACCESS ON
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface)
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface)
     : fp_interface_(fp_interface) {
   uint64_t fpsr, fpcr;
   asm volatile(
@@ -186,8 +187,8 @@
 
   // Pack fpsr and fpcr into cpu_fp_status
   cpu_fp_status_ = (fpsr << 32) | (fpcr & 0xffff'ffff);
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface_);
   // Get the translated version of the simulated RiscV status.
   auto arm_fp_regs = host_fp_interface->arm_fp_regs();
   // Save current "dynamic" rounding mode.
@@ -201,7 +202,7 @@
         "r"(arm_fp_regs.fpcr));  // NOLINT(google3-runtime-inline-assembly)
 }
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface,
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface,
                                uint32_t riscv_rm)
     : fp_interface_(fp_interface) {
   uint64_t fpsr, fpcr;
@@ -212,8 +213,8 @@
 
   // Pack fpsr and fpcr into cpu_fp_status
   cpu_fp_status_ = (fpsr << 32) | (fpcr & 0xffff'ffff);
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface_);
   // Get the translated version of the simulated RiscV status.
   auto arm_fp_regs = host_fp_interface->arm_fp_regs();
   // Save current "dynamic" rounding mode.
@@ -232,7 +233,7 @@
         "r"(arm_fp_regs.fpcr));  // NOLINT(google3-runtime-inline-assembly)
 }
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface,
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface,
                                FPRoundingMode riscv_rm)
     : fp_interface_(fp_interface) {
   uint64_t fpsr, fpcr;
@@ -243,8 +244,8 @@
 
   // Pack fpsr and fpcr into cpu_fp_status
   cpu_fp_status_ = (fpsr << 32) | (fpcr & 0xffff'ffff);
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface_);
   // Get the translated version of the simulated RiscV status.
   auto arm_fp_regs = host_fp_interface->arm_fp_regs();
   // Save current "dynamic" rounding mode.
@@ -270,8 +271,8 @@
                : "=r"(fpsr));  // NOLINT(google3-runtime-inline-assembly
 
   // Save the simulated status.
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface_);
   host_fp_interface->set_arm_fp_regs({host_rm_, fpsr});
   // Restore the saved host status.
   fpcr = cpu_fp_status_ & 0xffff'ffff;
@@ -284,7 +285,7 @@
 }
 
 ScopedFPRoundingMode::ScopedFPRoundingMode(
-    HostFloatingPointInterface *fp_interface, uint32_t riscv_rm_value) {
+    HostFloatingPointInterface* fp_interface, uint32_t riscv_rm_value) {
   uint64_t fpsr, fpcr;
   asm volatile(
       "MRS %x0, FPSR\n"
@@ -293,8 +294,8 @@
 
   // Pack fpsr and fpcr into cpu_fp_status
   cpu_fp_status_ = (fpsr << 32) | (fpcr & 0xffff'ffff);
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface);
   // Get the translated version of the simulated RiscV status.
   auto arm_fp_regs = host_fp_interface->arm_fp_regs();
   if (riscv_rm_value != 0b111) {
@@ -312,7 +313,7 @@
 }
 
 ScopedFPRoundingMode::ScopedFPRoundingMode(
-    HostFloatingPointInterface *fp_interface, FPRoundingMode rm) {
+    HostFloatingPointInterface* fp_interface, FPRoundingMode rm) {
   uint64_t fpsr, fpcr;
   asm volatile(
       "MRS %x0, FPSR\n"
@@ -321,8 +322,8 @@
 
   // Pack fpsr and fpcr into cpu_fp_status
   cpu_fp_status_ = (fpsr << 32) | (fpcr & 0xffff'ffff);
-  auto *host_fp_interface =
-      static_cast<ArmFloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<ArmFloatingPointInterface*>(fp_interface);
   // Get the translated version of the simulated RiscV status.
   auto arm_fp_regs = host_fp_interface->arm_fp_regs();
   auto rm_value = static_cast<uint32_t>(rm);
diff --git a/riscv/riscv_fp_host_x86.cc b/riscv/riscv_fp_host_x86.cc
index be3bb03..cb5ba50 100644
--- a/riscv/riscv_fp_host_x86.cc
+++ b/riscv/riscv_fp_host_x86.cc
@@ -198,20 +198,20 @@
 };
 
 // Factory function.
-HostFloatingPointInterface *GetHostFloatingPointInterface() {
+HostFloatingPointInterface* GetHostFloatingPointInterface() {
   return new X86FloatingPointInterface();
 }
 
 #pragma STDC FENV_ACCESS ON
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface)
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface)
     : fp_interface_(fp_interface) {
   // The host processor status is saved in cpu_fp_status_.
   uint32_t sim_status = 0;
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "+X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface_);
   // Get the translated version of the simulated RiscV status.
   sim_status = host_fp_interface->x86_status();
   // Save current "dynamic" rounding mode.
@@ -222,15 +222,15 @@
                : "m"(sim_status));
 }
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface,
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface,
                                uint32_t rm)
     : fp_interface_(fp_interface) {
   // The host processor status is saved in cpu_fp_status_.
   uint32_t sim_status = 0;
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "=X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface_);
   sim_status = host_fp_interface->x86_status();
   // Save current "dynamic" rounding mode.
   host_rm_ = sim_status & 0x6000;
@@ -245,15 +245,15 @@
                : "m"(sim_status));
 }
 
-ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface *fp_interface,
+ScopedFPStatus::ScopedFPStatus(HostFloatingPointInterface* fp_interface,
                                FPRoundingMode rm)
     : fp_interface_(fp_interface) {
   // The host processor status is saved in cpu_fp_status_.
   uint32_t sim_status = 0;
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "=X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface);
   sim_status = host_fp_interface->x86_status();
   // Save current "dynamic" rounding mode.
   host_rm_ = sim_status & 0x6000;
@@ -275,8 +275,8 @@
   asm volatile(  // NOLINT(google3-runtime-inline-assembly)
       "stmxcsr %0\n"
       : "=m"(x86_sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface_);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface_);
   // Save the fp status of the simulated instructions.
   uint32_t sim_status = ((x86_sim_status) & 0x1fff) | host_rm_;
   // Save the new status as the x86 version of the RiscV status.
@@ -288,13 +288,13 @@
 }
 
 ScopedFPRoundingMode::ScopedFPRoundingMode(
-    HostFloatingPointInterface *fp_interface) {
+    HostFloatingPointInterface* fp_interface) {
   uint32_t sim_status = 0;
   // Get current x86 status and save it in cpu_fp_status_.
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "=X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface);
   sim_status = host_fp_interface->x86_status();
   asm volatile("ldmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                :
@@ -302,13 +302,13 @@
 }
 
 ScopedFPRoundingMode::ScopedFPRoundingMode(
-    HostFloatingPointInterface *fp_interface, uint32_t rm) {
+    HostFloatingPointInterface* fp_interface, uint32_t rm) {
   uint32_t sim_status = 0;
   // Get current x86 status and save it in cpu_fp_status_.
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "=X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface);
   sim_status = host_fp_interface->x86_status();
   if (rm != 0b111) {
     // Override rounding mode with that specified in the instruction.
@@ -321,13 +321,13 @@
 }
 
 ScopedFPRoundingMode::ScopedFPRoundingMode(
-    HostFloatingPointInterface *fp_interface, FPRoundingMode rm) {
+    HostFloatingPointInterface* fp_interface, FPRoundingMode rm) {
   uint32_t sim_status = 0;
   // Get current x86 status and save it in cpu_fp_status_.
   asm volatile("stmxcsr %0\n"  // NOLINT(google3-runtime-inline-assembly)
                : "=m"(cpu_fp_status_), "=X"(sim_status));
-  auto *host_fp_interface =
-      static_cast<X86FloatingPointInterface *>(fp_interface);
+  auto* host_fp_interface =
+      static_cast<X86FloatingPointInterface*>(fp_interface);
   sim_status = host_fp_interface->x86_status();
   auto rm_value = static_cast<uint32_t>(rm);
   if (rm_value != 0b111) {
diff --git a/riscv/riscv_fp_state.cc b/riscv/riscv_fp_state.cc
index 543d219..68b989b 100644
--- a/riscv/riscv_fp_state.cc
+++ b/riscv/riscv_fp_state.cc
@@ -50,7 +50,7 @@
   LOG(ERROR) << status.message();
 }
 
-RiscVFPState::RiscVFPState(RiscVCsrSet *csr_set, ArchState *rv_state)
+RiscVFPState::RiscVFPState(RiscVCsrSet* csr_set, ArchState* rv_state)
     : rv_state_(rv_state) {
   fcsr_ = new RiscVFcsr(this);
   frm_ = new RiscVFrm(this);
@@ -95,7 +95,7 @@
 }
 
 // The RiscV fp csr.
-RiscVFcsr::RiscVFcsr(RiscVFPState *fp_state)
+RiscVFcsr::RiscVFcsr(RiscVFPState* fp_state)
     : RiscVSimpleCsr<uint32_t>(kFcsrName, RiscVCsrEnum::kFCsr, kFcsrInitial,
                                kFcsrReadMask, kFcsrWriteMask,
                                fp_state->rv_state()),
@@ -124,7 +124,7 @@
 void RiscVFcsr::Write(uint64_t value) { Write(static_cast<uint32_t>(value)); }
 
 // RiscVFflags translates reads and writes into reads and writes of fcsr.
-RiscVFflags::RiscVFflags(RiscVFPState *fp_state)
+RiscVFflags::RiscVFflags(RiscVFPState* fp_state)
     : RiscVSimpleCsr<uint32_t>(kFflagsName, RiscVCsrEnum::kFFlags,
                                kFflagsInitial, kFflagsReadMask,
                                kFflagsWriteMask, fp_state->rv_state()),
@@ -149,7 +149,7 @@
 
 // RiscV rm (rounding mode) csr translates reads and writes into reads
 // and writes of fcsr.
-RiscVFrm::RiscVFrm(RiscVFPState *fp_state)
+RiscVFrm::RiscVFrm(RiscVFPState* fp_state)
     : RiscVSimpleCsr<uint32_t>(kFrmName, RiscVCsrEnum::kFrm, kFrmInitial,
                                kFrmReadMask, kFrmWriteMask,
                                fp_state->rv_state()),
diff --git a/riscv/riscv_fp_state.h b/riscv/riscv_fp_state.h
index f5d8a1e..337d201 100644
--- a/riscv/riscv_fp_state.h
+++ b/riscv/riscv_fp_state.h
@@ -35,7 +35,7 @@
 class RiscVFcsr : public RiscVSimpleCsr<uint32_t> {
  public:
   RiscVFcsr() = delete;
-  explicit RiscVFcsr(RiscVFPState *fp_state);
+  explicit RiscVFcsr(RiscVFPState* fp_state);
   ~RiscVFcsr() override = default;
 
   // Overrides.
@@ -45,14 +45,14 @@
   void Write(uint64_t value) override;
 
  private:
-  RiscVFPState *fp_state_;
+  RiscVFPState* fp_state_;
 };
 
 // Floating point rounding mode csr.
 class RiscVFrm : public RiscVSimpleCsr<uint32_t> {
  public:
   RiscVFrm() = delete;
-  explicit RiscVFrm(RiscVFPState *fp_state);
+  explicit RiscVFrm(RiscVFPState* fp_state);
   ~RiscVFrm() override = default;
 
   // Overrides.
@@ -66,14 +66,14 @@
   void Set(uint64_t value) override { Set(static_cast<uint32_t>(value)); }
 
  private:
-  RiscVFPState *fp_state_;
+  RiscVFPState* fp_state_;
 };
 
 // Floating point status flags csr.
 class RiscVFflags : public RiscVSimpleCsr<uint32_t> {
  public:
   RiscVFflags() = delete;
-  explicit RiscVFflags(RiscVFPState *fp_state);
+  explicit RiscVFflags(RiscVFPState* fp_state);
   ~RiscVFflags() override = default;
 
   // Overrides.
@@ -87,14 +87,14 @@
   void Set(uint64_t value) override { Set(static_cast<uint32_t>(value)); }
 
  private:
-  RiscVFPState *fp_state_;
+  RiscVFPState* fp_state_;
 };
 
 class RiscVFPState {
  public:
   RiscVFPState() = delete;
-  RiscVFPState(const RiscVFPState &) = delete;
-  explicit RiscVFPState(RiscVCsrSet *csr_set, ArchState *rv_state);
+  RiscVFPState(const RiscVFPState&) = delete;
+  explicit RiscVFPState(RiscVCsrSet* csr_set, ArchState* rv_state);
   ~RiscVFPState();
 
   FPRoundingMode GetRoundingMode() const;
@@ -104,22 +104,22 @@
   bool rounding_mode_valid() const { return rounding_mode_valid_; }
 
   // FP CSRs.
-  RiscVFcsr *fcsr() const { return fcsr_; }
-  RiscVFrm *frm() const { return frm_; }
-  RiscVFflags *fflags() const { return fflags_; }
+  RiscVFcsr* fcsr() const { return fcsr_; }
+  RiscVFrm* frm() const { return frm_; }
+  RiscVFflags* fflags() const { return fflags_; }
   // Parent state.
-  ArchState *rv_state() const { return rv_state_; }
+  ArchState* rv_state() const { return rv_state_; }
   // Host interface.
-  HostFloatingPointInterface *host_fp_interface() const {
+  HostFloatingPointInterface* host_fp_interface() const {
     return host_fp_interface_;
   }
 
  private:
-  ArchState *rv_state_;
-  RiscVFcsr *fcsr_ = nullptr;
-  RiscVFrm *frm_ = nullptr;
-  RiscVFflags *fflags_ = nullptr;
-  HostFloatingPointInterface *host_fp_interface_;
+  ArchState* rv_state_;
+  RiscVFcsr* fcsr_ = nullptr;
+  RiscVFrm* frm_ = nullptr;
+  RiscVFflags* fflags_ = nullptr;
+  HostFloatingPointInterface* host_fp_interface_;
 
   bool rounding_mode_valid_ = true;
   FPRoundingMode rounding_mode_ = FPRoundingMode::kRoundToNearest;
diff --git a/riscv/riscv_getter_helpers.h b/riscv/riscv_getter_helpers.h
index 408da03..2b0da3d 100644
--- a/riscv/riscv_getter_helpers.h
+++ b/riscv/riscv_getter_helpers.h
@@ -39,23 +39,23 @@
 using ::mpact::sim::generic::SourceOperandInterface;
 
 using SourceOpGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<SourceOperandInterface*()>>;
 using ListSourceOpGetterMap = absl::flat_hash_map<
-    int, absl::AnyInvocable<std::vector<SourceOperandInterface *>()>>;
+    int, absl::AnyInvocable<std::vector<SourceOperandInterface*>()>>;
 using DestOpGetterMap =
     absl::flat_hash_map<int,
-                        absl::AnyInvocable<DestinationOperandInterface *(int)>>;
+                        absl::AnyInvocable<DestinationOperandInterface*(int)>>;
 using ListDestOpGetterMap = absl::flat_hash_map<
-    int, absl::AnyInvocable<std::vector<DestinationOperandInterface *>(int)>>;
+    int, absl::AnyInvocable<std::vector<DestinationOperandInterface*>(int)>>;
 using SimpleResourceGetterMap =
-    absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource *()>>;
+    absl::flat_hash_map<int, absl::AnyInvocable<generic::SimpleResource*()>>;
 using ComplexResourceGetterMap = absl::flat_hash_map<
-    int, absl::AnyInvocable<ResourceOperandInterface *(int, int)>>;
+    int, absl::AnyInvocable<ResourceOperandInterface*(int, int)>>;
 
 // Helper function to insert and entry into a "getter" map. This is used in
 // the riscv_*_getter.h files.
 template <typename M, typename E, typename G>
-inline void Insert(M &map, E entry, G getter) {
+inline void Insert(M& map, E entry, G getter) {
   if (!map.contains(static_cast<int>(entry))) {
     map.insert(std::make_pair(static_cast<int>(entry), getter));
   } else {
@@ -64,7 +64,7 @@
 }
 
 template <typename M, typename E1, typename E2, typename G>
-inline void Insert(M &map, E1 entry1, E2 entry2, G getter) {
+inline void Insert(M& map, E1 entry1, E2 entry2, G getter) {
   auto key = std::tie(entry1, entry2);
   if (!map.contains(key)) {
     map.insert(std::make_pair(key, getter));
@@ -75,48 +75,48 @@
 
 // Generic helper functions to create register operands.
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(RiscVState *state,
+inline DestinationOperandInterface* GetRegisterDestinationOp(RiscVState* state,
                                                              std::string name,
                                                              int latency) {
-  auto *reg = state->GetRegister<RegType>(name).first;
+  auto* reg = state->GetRegister<RegType>(name).first;
   return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetRegisterDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateDestinationOperand(latency, op_name);
+inline DestinationOperandInterface* GetRegisterDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename T>
-inline DestinationOperandInterface *GetCSRSetBitsDestinationOp(
-    RiscVState *state, std::string name, int latency, std::string op_name) {
+inline DestinationOperandInterface* GetCSRSetBitsDestinationOp(
+    RiscVState* state, std::string name, int latency, std::string op_name) {
   auto result = state->csr_set()->GetCsr(name);
   if (!result.ok()) {
     LOG(ERROR) << "No such CSR '" << name << "'";
     return nullptr;
   }
-  auto *csr = result.value();
-  auto *op = csr->CreateSetDestinationOperand(latency, op_name);
+  auto* csr = result.value();
+  auto* op = csr->CreateSetDestinationOperand(latency, op_name);
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand();
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand();
   return op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetRegisterSourceOp(RiscVState* state,
                                                    std::string name,
                                                    std::string op_name) {
-  auto *reg = state->GetRegister<RegType>(name).first;
-  auto *op = reg->CreateSourceOperand(op_name);
+  auto* reg = state->GetRegister<RegType>(name).first;
+  auto* op = reg->CreateSourceOperand(op_name);
   return op;
 }
 
diff --git a/riscv/riscv_getters.h b/riscv/riscv_getters.h
index 4aee8bb..7023fd1 100644
--- a/riscv/riscv_getters.h
+++ b/riscv/riscv_getters.h
@@ -53,16 +53,16 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVSourceGetters(SourceOpGetterMap &getter_map,
-                           RiscVEncodingCommon *common) {
+void AddRiscVSourceGetters(SourceOpGetterMap& getter_map,
+                           RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kAAq, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kAAq, [common]() -> SourceOperandInterface* {
     if (Extractors::Inst32Format::ExtractAq(common->inst_word())) {
       return new IntLiteralOperand<1>();
     }
     return new IntLiteralOperand<0>();
   });
-  Insert(getter_map, *Enum::kARl, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kARl, [common]() -> SourceOperandInterface* {
     if (Extractors::Inst32Format::ExtractRl(common->inst_word())) {
       return new generic::IntLiteralOperand<1>();
     }
@@ -118,40 +118,40 @@
     if (!res.ok()) {
       return new ImmediateOperand<uint32_t>(csr_indx);
     }
-    auto *csr = res.value();
+    auto* csr = res.value();
     return new ImmediateOperand<uint32_t>(csr_indx, csr->name());
   });
-  Insert(getter_map, *Enum::kDrs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kDrs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kDrs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kDrs2, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kDrs3, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kDrs3, [common]() -> SourceOperandInterface* {
     int num = Extractors::R4Type::ExtractRs3(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kFrs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kFrs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs2, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kFrs3, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs3, [common]() -> SourceOperandInterface* {
     int num = Extractors::R4Type::ExtractRs3(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
@@ -229,14 +229,14 @@
     return new ImmediateOperand<uint32_t>(
         Extractors::Fence::ExtractPred(common->inst_word()));
   });
-  Insert(getter_map, *Enum::kRd, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRd, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRd(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kXregPrefix, num),
         kXRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface* {
     int rm = Extractors::RType::ExtractFunc3(common->inst_word());
     switch (rm) {
       case 0:
@@ -259,14 +259,14 @@
         return nullptr;
     }
   });
-  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<IntRegister>(
         common->state(), absl::StrCat(RiscVState::kXregPrefix, num),
         kXRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kRs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs2, [common]() -> SourceOperandInterface* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<IntRegister>(
@@ -301,8 +301,8 @@
 // to construct the register operand.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVDestGetters(DestOpGetterMap &getter_map,
-                         RiscVEncodingCommon *common) {
+void AddRiscVDestGetters(DestOpGetterMap& getter_map,
+                         RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kC3drd, [common](int latency) {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
@@ -327,26 +327,26 @@
                                                  RiscVState::kCsrName, latency);
   });
   Insert(getter_map, *Enum::kDrd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            int num = Extractors::RType::ExtractRd(common->inst_word());
            return GetRegisterDestinationOp<IntRegister>(
                common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
                latency, kFRegisterAliases[num]);
          });
   Insert(getter_map, *Enum::kFrd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            int num = Extractors::RType::ExtractRd(common->inst_word());
            return GetRegisterDestinationOp<IntRegister>(
                common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
                latency, kFRegisterAliases[num]);
          });
   Insert(getter_map, *Enum::kNextPc,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            return GetRegisterDestinationOp<IntRegister>(
                common->state(), RiscVState::kPcName, latency);
          });
   Insert(getter_map, *Enum::kRd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            int num = Extractors::RType::ExtractRd(common->inst_word());
            if (num == 0) {
              return GetRegisterDestinationOp<IntRegister>(common->state(),
@@ -358,7 +358,7 @@
            }
          });
   Insert(getter_map, *Enum::kX0,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            return GetRegisterDestinationOp<IntRegister>(
                common->state(), "X0Dest", 0, kXRegisterAliases[0]);
          });
@@ -384,99 +384,99 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors>
-void AddRiscVSimpleResourceGetters(SimpleResourceGetterMap &getter_map,
-                                   RiscVEncodingCommon *common) {
-  Insert(getter_map, *Enum::kC3drd, [common]() -> generic::SimpleResource * {
+void AddRiscVSimpleResourceGetters(SimpleResourceGetterMap& getter_map,
+                                   RiscVEncodingCommon* common) {
+  Insert(getter_map, *Enum::kC3drd, [common]() -> generic::SimpleResource* {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kC3drs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kC3drs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::CS::ExtractCsRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kC3rd, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kC3rd, [common]() -> generic::SimpleResource* {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kC3rs1, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kC3rs1, [common]() -> generic::SimpleResource* {
     int num = Extractors::CS::ExtractCsRs1(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kC3rs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kC3rs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::CS::ExtractCsRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kCdrs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kCdrs2, [common]() -> generic::SimpleResource* {
     auto num = Extractors::CR::ExtractRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kCrs1, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kCrs1, [common]() -> generic::SimpleResource* {
     auto num = Extractors::CR::ExtractRs1(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kCrs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kCrs2, [common]() -> generic::SimpleResource* {
     auto num = Extractors::CR::ExtractRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kCsr, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kCsr, [common]() -> generic::SimpleResource* {
     return common->resource_pool()->GetOrAddResource("csr");
   });
-  Insert(getter_map, *Enum::kDrd, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kDrd, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRd(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kDrs1, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kDrs1, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kDrs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kDrs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kDrs3, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kDrs3, [common]() -> generic::SimpleResource* {
     int num = Extractors::R4Type::ExtractRs3(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kFrd, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kFrd, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRd(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kFrs1, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kFrs1, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRs1(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kFrs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kFrs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::RType::ExtractRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kFrs3, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kFrs3, [common]() -> generic::SimpleResource* {
     int num = Extractors::R4Type::ExtractRs3(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kNextPc, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kNextPc, [common]() -> generic::SimpleResource* {
     return common->resource_pool()->GetOrAddResource("next_pc");
   });
-  Insert(getter_map, *Enum::kRd, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kRd, [common]() -> generic::SimpleResource* {
     auto num = Extractors::RType::ExtractRd(common->inst_word());
     if (num == 0) return nullptr;
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kRs1, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kRs1, [common]() -> generic::SimpleResource* {
     auto num = Extractors::RType::ExtractRs1(common->inst_word());
     if (num == 0) return nullptr;
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
-  Insert(getter_map, *Enum::kRs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kRs2, [common]() -> generic::SimpleResource* {
     auto num = Extractors::RType::ExtractRs2(common->inst_word());
     if (num == 0) return nullptr;
     return common->resource_pool()->GetOrAddResource(absl::StrCat("x", num));
   });
   Insert(getter_map, *Enum::kX0,
-         []() -> generic::SimpleResource * { return nullptr; });
-  Insert(getter_map, *Enum::kX1, [common]() -> generic::SimpleResource * {
+         []() -> generic::SimpleResource* { return nullptr; });
+  Insert(getter_map, *Enum::kX1, [common]() -> generic::SimpleResource* {
     return common->resource_pool()->GetOrAddResource("x1");
   });
-  Insert(getter_map, *Enum::kX2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kX2, [common]() -> generic::SimpleResource* {
     return common->resource_pool()->GetOrAddResource("x2");
   });
 }
diff --git a/riscv/riscv_getters_rv32.h b/riscv/riscv_getters_rv32.h
index 0283882..93b3505 100644
--- a/riscv/riscv_getters_rv32.h
+++ b/riscv/riscv_getters_rv32.h
@@ -50,8 +50,8 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscV32SourceGetters(SourceOpGetterMap &getter_map,
-                             RiscVEncodingCommon *common) {
+void AddRiscV32SourceGetters(SourceOpGetterMap& getter_map,
+                             RiscVEncodingCommon* common) {
   // Source operand getters.
   Insert(getter_map, *Enum::kC3frs2, [common]() {
     auto num = Extractors::CS::ExtractCsRs2(common->inst_word());
@@ -74,8 +74,8 @@
 // to construct the register operand.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscV32DestGetters(DestOpGetterMap &getter_map,
-                           RiscVEncodingCommon *common) {
+void AddRiscV32DestGetters(DestOpGetterMap& getter_map,
+                           RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kC3frd, [common](int latency) {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
@@ -90,17 +90,17 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors>
-void AddRiscV32SimpleResourceGetters(SimpleResourceGetterMap &getter_map,
-                                     RiscVEncodingCommon *common) {
-  Insert(getter_map, *Enum::kC3frd, [common]() -> generic::SimpleResource * {
+void AddRiscV32SimpleResourceGetters(SimpleResourceGetterMap& getter_map,
+                                     RiscVEncodingCommon* common) {
+  Insert(getter_map, *Enum::kC3frd, [common]() -> generic::SimpleResource* {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kC3frs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kC3frs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::CS::ExtractCsRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
-  Insert(getter_map, *Enum::kCfrs2, [common]() -> generic::SimpleResource * {
+  Insert(getter_map, *Enum::kCfrs2, [common]() -> generic::SimpleResource* {
     int num = Extractors::CR::ExtractRs2(common->inst_word());
     return common->resource_pool()->GetOrAddResource(absl::StrCat("d", num));
   });
diff --git a/riscv/riscv_getters_rv64.h b/riscv/riscv_getters_rv64.h
index 15583c8..7fe52cc 100644
--- a/riscv/riscv_getters_rv64.h
+++ b/riscv/riscv_getters_rv64.h
@@ -46,8 +46,8 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscV64SourceGetters(SourceOpGetterMap &getter_map,
-                             RiscVEncodingCommon *common) {
+void AddRiscV64SourceGetters(SourceOpGetterMap& getter_map,
+                             RiscVEncodingCommon* common) {
   // Source operand getters.
   Insert(getter_map, *Enum::kIUimm6, [common]() {
     return new ImmediateOperand<uint32_t>(
@@ -62,8 +62,8 @@
 // to construct the register operand.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscV64DestGetters(DestOpGetterMap &getter_map,
-                           RiscVEncodingCommon *common) {
+void AddRiscV64DestGetters(DestOpGetterMap& getter_map,
+                           RiscVEncodingCommon* common) {
   // Empty.
 }
 
@@ -73,8 +73,8 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors>
-void AddRiscV64SimpleResourceGetters(SimpleResourceGetterMap &getter_map,
-                                     RiscVEncodingCommon *common) {
+void AddRiscV64SimpleResourceGetters(SimpleResourceGetterMap& getter_map,
+                                     RiscVEncodingCommon* common) {
   // Empty.
 }
 
diff --git a/riscv/riscv_getters_vector.h b/riscv/riscv_getters_vector.h
index 9a41a15..f68e2a6 100644
--- a/riscv/riscv_getters_vector.h
+++ b/riscv/riscv_getters_vector.h
@@ -16,7 +16,6 @@
 #define THIRD_PARTY_MPACT_RISCV_RISCV_GETTERS_VECTOR_H_
 
 #include <cstdint>
-#include <new>
 #include <string>
 #include <vector>
 
@@ -47,8 +46,8 @@
 constexpr int kNumRegTable[8] = {8, 1, 2, 1, 4, 1, 2, 1};
 
 template <typename RegType>
-inline void GetVRegGroup(RiscVState *state, int reg_num,
-                         std::vector<generic::RegisterBase *> *vreg_group) {
+inline void GetVRegGroup(RiscVState* state, int reg_num,
+                         std::vector<generic::RegisterBase*>* vreg_group) {
   // The number of registers in a vector register group depends on the register
   // index: 0, 8, 16, 24 each have 8 registers, 4, 12, 20, 28 each have 4,
   // 2, 6, 10, 14, 18, 22, 26, 30 each have two, and all odd numbered register
@@ -60,53 +59,53 @@
   }
 }
 template <typename RegType>
-inline SourceOperandInterface *GetVectorRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorRegisterSourceOp(RiscVState* state,
                                                          int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
-  std::vector<generic::RegisterBase *> vreg_group;
+inline DestinationOperandInterface* GetVectorRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
+  std::vector<generic::RegisterBase*> vreg_group;
   GetVRegGroup<RegType>(state, reg_num, &vreg_group);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
 
 template <typename RegType>
-inline SourceOperandInterface *GetVectorMaskRegisterSourceOp(RiscVState *state,
+inline SourceOperandInterface* GetVectorMaskRegisterSourceOp(RiscVState* state,
                                                              int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_src_op = new RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group),
+  auto* v_src_op = new RV32VectorSourceOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group),
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_src_op;
 }
 
 template <typename RegType>
-inline DestinationOperandInterface *GetVectorMaskRegisterDestinationOp(
-    RiscVState *state, int latency, int reg_num) {
+inline DestinationOperandInterface* GetVectorMaskRegisterDestinationOp(
+    RiscVState* state, int latency, int reg_num) {
   // Mask register groups only have a single register.
-  std::vector<generic::RegisterBase *> vreg_group;
+  std::vector<generic::RegisterBase*> vreg_group;
   vreg_group.push_back(
       state
           ->GetRegister<RegType>(absl::StrCat(RiscVState::kVregPrefix, reg_num))
           .first);
-  auto *v_dst_op = new RV32VectorDestinationOperand(
-      absl::Span<generic::RegisterBase *>(vreg_group), latency,
+  auto* v_dst_op = new RV32VectorDestinationOperand(
+      absl::Span<generic::RegisterBase*>(vreg_group), latency,
       absl::StrCat(RiscVState::kVregPrefix, reg_num));
   return v_dst_op;
 }
@@ -116,14 +115,14 @@
 // for the instruction set being decoded. The Extractors parameter is used to
 // get the correct instruction format extractor for the instruction set.
 template <typename Enum, typename Extractors, typename VectorRegister>
-void AddRiscVVectorSourceGetters(SourceOpGetterMap &getter_map,
-                                 RiscVEncodingCommon *common) {
+void AddRiscVVectorSourceGetters(SourceOpGetterMap& getter_map,
+                                 RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kVd, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVd, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVd(common->inst_word());
     return GetVectorRegisterSourceOp<VectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface* {
     auto vm = Extractors::VArith::ExtractVm(common->inst_word());
     if (vm == 1) {
       // Unmasked, return the True mask.
@@ -132,73 +131,73 @@
     // Masked. Return the mask register.
     return GetVectorMaskRegisterSourceOp<VectorRegister>(common->state(), 0);
   });
-  Insert(getter_map, *Enum::kVmaskTrue, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVmaskTrue, [common]() -> SourceOperandInterface* {
     return new RV32VectorTrueOperand(common->state());
   });
-  Insert(getter_map, *Enum::kVm, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVm, [common]() -> SourceOperandInterface* {
     auto vm = Extractors::VArith::ExtractVm(common->inst_word());
     return new generic::ImmediateOperand<bool>(
         vm, absl::StrCat("vm.", vm ? "t" : "f"));
   });
-  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs1(common->inst_word());
     return GetVectorRegisterSourceOp<VectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs2(common->inst_word());
     return GetVectorRegisterSourceOp<VectorRegister>(common->state(), num);
   });
-  Insert(getter_map, *Enum::kVs3, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs3, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VMem::ExtractVs3(common->inst_word());
     return GetVectorRegisterSourceOp<VectorRegister>(common->state(), num);
   });
 
-  Insert(getter_map, *Enum::kSimm5, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kSimm5, [common]() -> SourceOperandInterface* {
     const auto num =
         Extractors::Inst32Format::ExtractSimm5(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
 
-  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface* {
     const auto num =
         Extractors::Inst32Format::ExtractUimm5(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
 
-  Insert(getter_map, *Enum::kZimm10, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kZimm10, [common]() -> SourceOperandInterface* {
     const auto num =
         Extractors::Inst32Format::ExtractZimm10(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
 
-  Insert(getter_map, *Enum::kZimm11, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kZimm11, [common]() -> SourceOperandInterface* {
     const auto num =
         Extractors::Inst32Format::ExtractZimm11(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
 
-  Insert(getter_map, *Enum::kConst1, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst1, []() -> SourceOperandInterface* {
     return new generic::ImmediateOperand<int32_t>(1);
   });
 
-  Insert(getter_map, *Enum::kConst2, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst2, []() -> SourceOperandInterface* {
     return new generic::ImmediateOperand<int32_t>(2);
   });
 
-  Insert(getter_map, *Enum::kConst4, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst4, []() -> SourceOperandInterface* {
     return new generic::ImmediateOperand<int32_t>(4);
   });
 
-  Insert(getter_map, *Enum::kConst8, []() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kConst8, []() -> SourceOperandInterface* {
     return new generic::ImmediateOperand<int32_t>(8);
   });
 
-  Insert(getter_map, *Enum::kNf, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kNf, [common]() -> SourceOperandInterface* {
     auto num_fields = Extractors::VMem::ExtractNf(common->inst_word());
     return new generic::ImmediateOperand<uint8_t>(num_fields,
                                                   absl::StrCat(num_fields + 1));
   });
-  Insert(getter_map, *Enum::kFs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFs1, [common]() -> SourceOperandInterface* {
     const int num = Extractors::VArith::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<RV64Register>(common->state(),
                                              std::string(kFregNames[num]),
@@ -212,17 +211,17 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors, typename VectorRegister>
-void AddRiscVVectorDestGetters(DestOpGetterMap &getter_map,
-                               RiscVEncodingCommon *common) {
+void AddRiscVVectorDestGetters(DestOpGetterMap& getter_map,
+                               RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kVd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            auto num = Extractors::VArith::ExtractVd(common->inst_word());
            return GetVectorRegisterDestinationOp<VectorRegister>(
                common->state(), latency, num);
          });
   Insert(getter_map, *Enum::kFd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            const int num = Extractors::VArith::ExtractRd(common->inst_word());
            return GetRegisterDestinationOp<RV64Register>(
                common->state(), std::string(kFregNames[num]), latency,
@@ -236,8 +235,8 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors>
-void AddRiscVVectorSimpleResourceGetters(SimpleResourceGetterMap &getter_map,
-                                         RiscVEncodingCommon *common) {
+void AddRiscVVectorSimpleResourceGetters(SimpleResourceGetterMap& getter_map,
+                                         RiscVEncodingCommon* common) {
   // TODO(torerik): Add resource getters when appropriate.
 }
 
diff --git a/riscv/riscv_getters_zba.h b/riscv/riscv_getters_zba.h
index a7d06e3..f7b241d 100644
--- a/riscv/riscv_getters_zba.h
+++ b/riscv/riscv_getters_zba.h
@@ -15,8 +15,6 @@
 #ifndef THIRD_PARTY_MPACT_RISCV_RISCV_GETTERS_ZBA_H_
 #define THIRD_PARTY_MPACT_RISCV_RISCV_GETTERS_ZBA_H_
 
-#include <new>
-
 #include "mpact/sim/generic/literal_operand.h"
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv/riscv_encoding_common.h"
@@ -36,8 +34,8 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZbaSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVEncodingCommon *common) {
+void AddRiscVZbaSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVEncodingCommon* common) {
   // Source operand getters.
   Insert(getter_map, *Enum::kConst1,
          []() { return new generic::IntLiteralOperand<1>(); });
@@ -49,8 +47,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZbaDestGetters(DestOpGetterMap &getter_map,
-                            RiscVEncodingCommon *common) {
+void AddRiscVZbaDestGetters(DestOpGetterMap& getter_map,
+                            RiscVEncodingCommon* common) {
   // Destination operand getters.
   // Empty.
 }
diff --git a/riscv/riscv_getters_zbb32.h b/riscv/riscv_getters_zbb32.h
index f640a48..882dec6 100644
--- a/riscv/riscv_getters_zbb32.h
+++ b/riscv/riscv_getters_zbb32.h
@@ -16,7 +16,6 @@
 #define THIRD_PARTY_MPACT_RISCV_RISCV_GETTERS_ZBB32_H_
 
 #include <cstdint>
-#include <new>
 
 #include "mpact/sim/generic/immediate_operand.h"
 #include "mpact/sim/generic/type_helpers.h"
@@ -37,8 +36,8 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZbb32SourceGetters(SourceOpGetterMap &getter_map,
-                                RiscVEncodingCommon *common) {
+void AddRiscVZbb32SourceGetters(SourceOpGetterMap& getter_map,
+                                RiscVEncodingCommon* common) {
   // Source operand getters.
   Insert(getter_map, *Enum::kRUimm5, [common]() {
     uint32_t uimm = Extractors::RType::ExtractRUimm5(common->inst_word());
diff --git a/riscv/riscv_getters_zbb64.h b/riscv/riscv_getters_zbb64.h
index a824055..6d8aa1f 100644
--- a/riscv/riscv_getters_zbb64.h
+++ b/riscv/riscv_getters_zbb64.h
@@ -36,8 +36,8 @@
 // types for the instruction set.
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZbb64SourceGetters(SourceOpGetterMap &getter_map,
-                                RiscVEncodingCommon *common) {
+void AddRiscVZbb64SourceGetters(SourceOpGetterMap& getter_map,
+                                RiscVEncodingCommon* common) {
   // Source operand getters.
   Insert(getter_map, *Enum::kRUimm6, [common]() {
     uint32_t uimm = Extractors::RSType::ExtractRUimm6(common->inst_word());
diff --git a/riscv/riscv_getters_zvbb.h b/riscv/riscv_getters_zvbb.h
index 7484890..1b38953 100644
--- a/riscv/riscv_getters_zvbb.h
+++ b/riscv/riscv_getters_zvbb.h
@@ -16,7 +16,6 @@
 #define THIRD_PARTY_MPACT_RISCV_RISCV_GETTERS_ZVBB_H_
 
 #include <cstdint>
-#include <new>
 
 #include "absl/strings/str_cat.h"
 #include "mpact/sim/generic/immediate_operand.h"
@@ -39,10 +38,10 @@
 // for the instruction set being decoded. The Extractors parameter is used to
 // get the correct instruction format extractor for the instruction set.
 template <typename Enum, typename Extractors, typename VectorRegister>
-void AddRiscVZvbbSourceVectorGetters(SourceOpGetterMap &getter_map,
-                                     RiscVEncodingCommon *common) {
+void AddRiscVZvbbSourceVectorGetters(SourceOpGetterMap& getter_map,
+                                     RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVmask, [common]() -> SourceOperandInterface* {
     auto vm = Extractors::VArith::ExtractVm(common->inst_word());
     if (vm == 1) {
       // Unmasked, return the True mask.
@@ -52,12 +51,12 @@
     return mpact::sim::riscv::GetVectorMaskRegisterSourceOp<VectorRegister>(
         common->state(), 0);
   });
-  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs1, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs1(common->inst_word());
     return mpact::sim::riscv::GetVectorMaskRegisterSourceOp<VectorRegister>(
         common->state(), num);
   });
-  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kVs2, [common]() -> SourceOperandInterface* {
     auto num = Extractors::VArith::ExtractVs2(common->inst_word());
     return mpact::sim::riscv::GetVectorMaskRegisterSourceOp<VectorRegister>(
         common->state(), num);
@@ -65,32 +64,32 @@
 }
 
 template <typename Enum, typename Extractors, typename IntegerRegister>
-void AddRiscvZvbbSourceScalarGetters(SourceOpGetterMap &getter_map,
-                                     RiscVEncodingCommon *common) {
+void AddRiscvZvbbSourceScalarGetters(SourceOpGetterMap& getter_map,
+                                     RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::VArith::ExtractRs1(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<IntegerRegister>(
         common->state(), absl::StrCat(RiscVState::kXregPrefix, num),
         kXRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kUimm5, [common]() -> SourceOperandInterface* {
     const auto num = Extractors::VArith::ExtractUimm5(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
-  Insert(getter_map, *Enum::kUimm6, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kUimm6, [common]() -> SourceOperandInterface* {
     const auto num = Extractors::VArith::ExtractUimm6(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
 }
 
 template <typename Enum, typename Extractors, typename VectorRegister>
-void AddRiscVZvbbDestGetters(DestOpGetterMap &getter_map,
-                             RiscVEncodingCommon *common) {
+void AddRiscVZvbbDestGetters(DestOpGetterMap& getter_map,
+                             RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kVd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            auto num = Extractors::VArith::ExtractVd(common->inst_word());
            return mpact::sim::riscv::GetVectorRegisterDestinationOp<
                VectorRegister>(common->state(), latency, num);
diff --git a/riscv/riscv_i_instructions.cc b/riscv/riscv_i_instructions.cc
index 2376214..64645ec 100644
--- a/riscv/riscv_i_instructions.cc
+++ b/riscv/riscv_i_instructions.cc
@@ -32,8 +32,8 @@
 namespace sim {
 namespace riscv {
 
-void RiscVIllegalInstruction(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RiscVIllegalInstruction(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
               *ExceptionCode::kIllegalInstruction,
               /*epc*/ inst->address(), inst);
@@ -53,59 +53,59 @@
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 using IntReg = typename std::make_signed<UIntReg>::type;
 
-void RiscVIAdd(const Instruction *instruction) {
+void RiscVIAdd(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a + b; });
 }
 
-void RiscVISub(const Instruction *instruction) {
+void RiscVISub(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a - b; });
 }
 
-void RiscVISlt(const Instruction *instruction) {
+void RiscVISlt(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVISltu(const Instruction *instruction) {
+void RiscVISltu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIAnd(const Instruction *instruction) {
+void RiscVIAnd(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a & b; });
 }
 
-void RiscVIOr(const Instruction *instruction) {
+void RiscVIOr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | b; });
 }
 
-void RiscVIXor(const Instruction *instruction) {
+void RiscVIXor(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a ^ b; });
 }
 
-void RiscVISll(const Instruction *instruction) {
+void RiscVISll(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a << (b & 0x1f); });
 }
 
-void RiscVISrl(const Instruction *instruction) {
+void RiscVISrl(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >> (b & 0x1f); });
 }
 
-void RiscVISra(const Instruction *instruction) {
+void RiscVISra(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >> (b & 0x1f); });
 }
 
 // Load upper immediate. It is assumed that the decoder already shifted the
 // immediate. Operates on 32 bit quantities, not XLEN bits.
-void RiscVILui(const Instruction *instruction) {
+void RiscVILui(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, uint32_t, uint32_t>(
       instruction, [](uint32_t lhs) { return lhs & ~0xfff; });
 }
@@ -113,7 +113,7 @@
 // Add upper immediate to PC (for PC relative addressing). It is assumed that
 // the decoder already shifted the immediate. Operates on 32 bit quantities,
 // not XLEN bits.
-void RiscVIAuipc(const Instruction *instruction) {
+void RiscVIAuipc(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, uint32_t, uint32_t>(
       instruction, [instruction](uint32_t lhs) {
         return (lhs & ~0xfff) + instruction->address();
@@ -122,30 +122,30 @@
 
 // Jump and link instructions. One using a long offset, the other offset plus
 // base.
-void RiscVIJal(const Instruction *instruction) {
+void RiscVIJal(const Instruction* instruction) {
   UIntReg offset = generic::GetInstructionSource<UIntReg>(instruction, 0);
   UIntReg target = (offset + instruction->address()) & ~0x1;
   UIntReg return_address = instruction->address() + instruction->size();
-  auto *db = instruction->Destination(0)->AllocateDataBuffer();
+  auto* db = instruction->Destination(0)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->set_branch(true);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<UIntReg> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<UIntReg>*>(
                   instruction->Destination(1))
                   ->GetRegister();
   reg->data_buffer()->Set<UIntReg>(0, return_address);
 }
 
-void RiscVIJalr(const Instruction *instruction) {
+void RiscVIJalr(const Instruction* instruction) {
   UIntReg reg_base = generic::GetInstructionSource<UIntReg>(instruction, 0);
   UIntReg offset = generic::GetInstructionSource<UIntReg>(instruction, 1);
   UIntReg target = (offset + reg_base) & ~0x1;
   UIntReg return_address = instruction->address() + instruction->size();
-  auto *db = instruction->Destination(0)->AllocateDataBuffer();
+  auto* db = instruction->Destination(0)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->set_branch(true);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<UIntReg> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<UIntReg>*>(
                   instruction->Destination(1))
                   ->GetRegister();
   reg->data_buffer()->Set<UIntReg>(0, return_address);
@@ -164,12 +164,12 @@
 using NarrowIntReg = typename ::mpact::sim::generic::NarrowType<IntReg>::type;
 using NarrowUIntReg = typename ::mpact::sim::generic::NarrowType<UIntReg>::type;
 
-void RiscVIAdd(const Instruction *instruction) {
+void RiscVIAdd(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a + b; });
 }
 
-void RiscVIAddw(const Instruction *instruction) {
+void RiscVIAddw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) {
         IntReg c = static_cast<IntReg>(a + b);
@@ -177,12 +177,12 @@
       });
 }
 
-void RiscVISub(const Instruction *instruction) {
+void RiscVISub(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a - b; });
 }
 
-void RiscVISubw(const Instruction *instruction) {
+void RiscVISubw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) {
         IntReg c = static_cast<IntReg>(a - b);
@@ -190,54 +190,54 @@
       });
 }
 
-void RiscVISlt(const Instruction *instruction) {
+void RiscVISlt(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVISltu(const Instruction *instruction) {
+void RiscVISltu(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIAnd(const Instruction *instruction) {
+void RiscVIAnd(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a & b; });
 }
 
-void RiscVIOr(const Instruction *instruction) {
+void RiscVIOr(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a | b; });
 }
 
-void RiscVIXor(const Instruction *instruction) {
+void RiscVIXor(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a ^ b; });
 }
 
-void RiscVISll(const Instruction *instruction) {
+void RiscVISll(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a << (b & 0x3f); });
 }
 
-void RiscVISrl(const Instruction *instruction) {
+void RiscVISrl(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, UIntReg, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >> (b & 0x3f); });
 }
 
-void RiscVISra(const Instruction *instruction) {
+void RiscVISra(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >> (b & 0x3f); });
 }
 
-void RiscVISllw(const Instruction *instruction) {
+void RiscVISllw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) -> IntReg {
         return static_cast<IntReg>(a << (b & 0x1f));
       });
 }
 
-void RiscVISrlw(const Instruction *instruction) {
+void RiscVISrlw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, NarrowUIntReg>(
       instruction, [](NarrowUIntReg a, NarrowUIntReg b) -> IntReg {
         auto c = a >> (b & 0x1f);
@@ -245,7 +245,7 @@
       });
 }
 
-void RiscVISraw(const Instruction *instruction) {
+void RiscVISraw(const Instruction* instruction) {
   RiscVBinaryOp<RegisterType, IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) -> IntReg {
         return static_cast<IntReg>(a >> (b & 0x1f));
@@ -254,7 +254,7 @@
 
 // Load upper immediate. It is assumed that the decoder already shifted the
 // immediate.
-void RiscVILui(const Instruction *instruction) {
+void RiscVILui(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, IntReg, int32_t>(
       instruction, [](int32_t lhs) -> IntReg {
         auto lhs_w = static_cast<IntReg>(lhs);
@@ -264,7 +264,7 @@
 
 // Add upper immediate to PC (for PC relative addressing). It is assumed that
 // the decoder already shifted the immediate.
-void RiscVIAuipc(const Instruction *instruction) {
+void RiscVIAuipc(const Instruction* instruction) {
   RiscVUnaryOp<RegisterType, uint64_t, int32_t>(
       instruction, [instruction](int32_t lhs) {
         auto lhs_w = static_cast<IntReg>(lhs & ~0xfff);
@@ -274,32 +274,32 @@
 
 // Jump and link instructions. One using a long offset, the other offset plus
 // base.
-void RiscVIJal(const Instruction *instruction) {
+void RiscVIJal(const Instruction* instruction) {
   UIntReg offset = generic::GetInstructionSource<UIntReg>(instruction, 0);
   UIntReg target = offset + instruction->address();
   target &= (std::numeric_limits<UIntReg>::max() << 1);
   UIntReg return_address = instruction->address() + instruction->size();
-  auto *db = instruction->Destination(0)->AllocateDataBuffer();
+  auto* db = instruction->Destination(0)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->set_branch(true);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<UIntReg> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<UIntReg>*>(
                   instruction->Destination(1))
                   ->GetRegister();
   reg->data_buffer()->Set<UIntReg>(0, return_address);
 }
 
-void RiscVIJalr(const Instruction *instruction) {
+void RiscVIJalr(const Instruction* instruction) {
   UIntReg reg_base = generic::GetInstructionSource<UIntReg>(instruction, 0);
   UIntReg offset = generic::GetInstructionSource<UIntReg>(instruction, 1);
   UIntReg target = offset + reg_base;
   target &= (std::numeric_limits<UIntReg>::max() << 1);
   UIntReg return_address = instruction->address() + instruction->size();
-  auto *db = instruction->Destination(0)->AllocateDataBuffer();
+  auto* db = instruction->Destination(0)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->set_branch(true);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<UIntReg> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<UIntReg>*>(
                   instruction->Destination(1))
                   ->GetRegister();
   reg->data_buffer()->Set<UIntReg>(0, return_address);
@@ -307,7 +307,7 @@
 
 }  // namespace RV64
 
-void RiscVINop(const Instruction *instruction) {}
+void RiscVINop(const Instruction* instruction) {}
 
 namespace RV32 {
 
@@ -318,32 +318,32 @@
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 using IntReg = typename std::make_signed<UIntReg>::type;
 
-void RiscVIBeq(const Instruction *instruction) {
+void RiscVIBeq(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a == b; });
 }
 
-void RiscVIBne(const Instruction *instruction) {
+void RiscVIBne(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a != b; });
 }
 
-void RiscVIBlt(const Instruction *instruction) {
+void RiscVIBlt(const Instruction* instruction) {
   BranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVIBltu(const Instruction *instruction) {
+void RiscVIBltu(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIBge(const Instruction *instruction) {
+void RiscVIBge(const Instruction* instruction) {
   BranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >= b; });
 }
 
-void RiscVIBgeu(const Instruction *instruction) {
+void RiscVIBgeu(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >= b; });
 }
@@ -359,32 +359,32 @@
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 using IntReg = typename std::make_signed<UIntReg>::type;
 
-void RiscVIBeq(const Instruction *instruction) {
+void RiscVIBeq(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a == b; });
 }
 
-void RiscVIBne(const Instruction *instruction) {
+void RiscVIBne(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a != b; });
 }
 
-void RiscVIBlt(const Instruction *instruction) {
+void RiscVIBlt(const Instruction* instruction) {
   BranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a < b; });
 }
 
-void RiscVIBltu(const Instruction *instruction) {
+void RiscVIBltu(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a < b; });
 }
 
-void RiscVIBge(const Instruction *instruction) {
+void RiscVIBge(const Instruction* instruction) {
   BranchConditional<RegisterType, IntReg>(
       instruction, [](IntReg a, IntReg b) { return a >= b; });
 }
 
-void RiscVIBgeu(const Instruction *instruction) {
+void RiscVIBgeu(const Instruction* instruction) {
   BranchConditional<RegisterType, UIntReg>(
       instruction, [](UIntReg a, UIntReg b) { return a >= b; });
 }
@@ -395,47 +395,47 @@
 
 using RegisterType = RV32Register;
 
-void RiscVILd(const Instruction *instruction) {
+void RiscVILd(const Instruction* instruction) {
   RVLoad<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVILw(const Instruction *instruction) {
+void RiscVILw(const Instruction* instruction) {
   RVLoad<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILwChild(const Instruction *instruction) {
+void RiscVILwChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILh(const Instruction *instruction) {
+void RiscVILh(const Instruction* instruction) {
   RVLoad<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhChild(const Instruction *instruction) {
+void RiscVILhChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhu(const Instruction *instruction) {
+void RiscVILhu(const Instruction* instruction) {
   RVLoad<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILhuChild(const Instruction *instruction) {
+void RiscVILhuChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILb(const Instruction *instruction) {
+void RiscVILb(const Instruction* instruction) {
   RVLoad<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbChild(const Instruction *instruction) {
+void RiscVILbChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbu(const Instruction *instruction) {
+void RiscVILbu(const Instruction* instruction) {
   RVLoad<RegisterType, uint8_t>(instruction);
 }
 
-void RiscVILbuChild(const Instruction *instruction) {
+void RiscVILbuChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, uint8_t>(instruction);
 }
 
@@ -445,59 +445,59 @@
 
 using RegisterType = RV64Register;
 
-void RiscVILd(const Instruction *instruction) {
+void RiscVILd(const Instruction* instruction) {
   RVLoad<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVILdChild(const Instruction *instruction) {
+void RiscVILdChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int64_t>(instruction);
 }
 
-void RiscVILw(const Instruction *instruction) {
+void RiscVILw(const Instruction* instruction) {
   RVLoad<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILwChild(const Instruction *instruction) {
+void RiscVILwChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int32_t>(instruction);
 }
 
-void RiscVILwu(const Instruction *instruction) {
+void RiscVILwu(const Instruction* instruction) {
   RVLoad<RegisterType, uint32_t>(instruction);
 }
 
-void RiscVILwuChild(const Instruction *instruction) {
+void RiscVILwuChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, uint32_t>(instruction);
 }
 
-void RiscVILh(const Instruction *instruction) {
+void RiscVILh(const Instruction* instruction) {
   RVLoad<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhChild(const Instruction *instruction) {
+void RiscVILhChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int16_t>(instruction);
 }
 
-void RiscVILhu(const Instruction *instruction) {
+void RiscVILhu(const Instruction* instruction) {
   RVLoad<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILhuChild(const Instruction *instruction) {
+void RiscVILhuChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVILb(const Instruction *instruction) {
+void RiscVILb(const Instruction* instruction) {
   RVLoad<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbChild(const Instruction *instruction) {
+void RiscVILbChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, int8_t>(instruction);
 }
 
-void RiscVILbu(const Instruction *instruction) {
+void RiscVILbu(const Instruction* instruction) {
   RVLoad<RegisterType, uint8_t>(instruction);
 }
 
-void RiscVILbuChild(const Instruction *instruction) {
+void RiscVILbuChild(const Instruction* instruction) {
   RVLoadChild<RegisterType, uint8_t>(instruction);
 }
 
@@ -507,19 +507,19 @@
 
 using RegisterType = RV32Register;
 
-void RiscVISd(const Instruction *instruction) {
+void RiscVISd(const Instruction* instruction) {
   RVStore<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVISw(const Instruction *instruction) {
+void RiscVISw(const Instruction* instruction) {
   RVStore<RegisterType, uint32_t>(instruction);
 }
 
-void RiscVISh(const Instruction *instruction) {
+void RiscVISh(const Instruction* instruction) {
   RVStore<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVISb(const Instruction *instruction) {
+void RiscVISb(const Instruction* instruction) {
   RVStore<RegisterType, uint8_t>(instruction);
 }
 
@@ -529,26 +529,26 @@
 
 using RegisterType = RV64Register;
 
-void RiscVISd(const Instruction *instruction) {
+void RiscVISd(const Instruction* instruction) {
   RVStore<RegisterType, uint64_t>(instruction);
 }
 
-void RiscVISw(const Instruction *instruction) {
+void RiscVISw(const Instruction* instruction) {
   RVStore<RegisterType, uint32_t>(instruction);
 }
 
-void RiscVISh(const Instruction *instruction) {
+void RiscVISh(const Instruction* instruction) {
   RVStore<RegisterType, uint16_t>(instruction);
 }
 
-void RiscVISb(const Instruction *instruction) {
+void RiscVISb(const Instruction* instruction) {
   RVStore<RegisterType, uint8_t>(instruction);
 }
 
 }  // namespace RV64
 
-void RiscVIUnimplemented(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVIUnimplemented(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   // Get instruction word, as it needs to be used as trap value.
   uint64_t address = instruction->address();
   auto db = state->db_factory()->Allocate<uint32_t>(1);
@@ -562,32 +562,32 @@
               /*epc=*/instruction->address(), instruction);
 }
 
-void RiscVIFence(const Instruction *instruction) {
+void RiscVIFence(const Instruction* instruction) {
   int pred = generic::GetInstructionSource<uint32_t>(instruction, 0) & 0xf;
   int succ = generic::GetInstructionSource<uint32_t>(instruction, 1) & 0xf;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   // Fence mode is 0x0
   state->Fence(instruction, /*fence_mode=*/0x0, pred, succ);
 }
 
-void RiscVIFenceTso(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVIFenceTso(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->Fence(instruction, /*fence_mode=*/0b1000, /*pred=*/0b0011,
                /*succ=*/0b0011);
 }
 
-void RiscVIEcall(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVIEcall(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->ECall(instruction);
 }
 
-void RiscVIEbreak(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVIEbreak(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->EBreak(instruction);
 }
 
-void RiscVWFI(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVWFI(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->WFI(instruction);
 }
 
diff --git a/riscv/riscv_i_instructions.h b/riscv/riscv_i_instructions.h
index f0770cb..f04b214 100644
--- a/riscv/riscv_i_instructions.h
+++ b/riscv/riscv_i_instructions.h
@@ -31,51 +31,51 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVIllegalInstruction(const Instruction *inst);
+void RiscVIllegalInstruction(const Instruction* inst);
 
 // No operands necessary for Nop. For now, all hint instructions should be
 // decoded as Nop.
-void RiscVINop(const Instruction *instruction);
+void RiscVINop(const Instruction* instruction);
 
 namespace RV32 {
 
 // For the following, source operand 0 refers to the register specified in rs1,
 // and source operand 1 refers to either the register specified in rs2, or the
 // immediate. Destination operand 0 refers to the register specified in rd.
-void RiscVIAdd(const Instruction *instruction);
-void RiscVISub(const Instruction *instruction);
-void RiscVISlt(const Instruction *instruction);
-void RiscVISltu(const Instruction *instruction);
-void RiscVIAnd(const Instruction *instruction);
-void RiscVIOr(const Instruction *instruction);
-void RiscVIXor(const Instruction *instruction);
-void RiscVISll(const Instruction *instruction);
-void RiscVISrl(const Instruction *instruction);
-void RiscVISra(const Instruction *instruction);
+void RiscVIAdd(const Instruction* instruction);
+void RiscVISub(const Instruction* instruction);
+void RiscVISlt(const Instruction* instruction);
+void RiscVISltu(const Instruction* instruction);
+void RiscVIAnd(const Instruction* instruction);
+void RiscVIOr(const Instruction* instruction);
+void RiscVIXor(const Instruction* instruction);
+void RiscVISll(const Instruction* instruction);
+void RiscVISrl(const Instruction* instruction);
+void RiscVISra(const Instruction* instruction);
 // For the following two semantic functions, source operand 0 refers to the
 // immediate value, and destination 0 the register specified in rd. Note, the
 // value of the immediate shall be properly shifted.
-void RiscVILui(const Instruction *instruction);
-void RiscVIAuipc(const Instruction *instruction);
+void RiscVILui(const Instruction* instruction);
+void RiscVIAuipc(const Instruction* instruction);
 // Source operand 0 contains the immediate value. Destination operand 0 refers
 // to the pc destination operand, wheras destination operand 1 refers to the
 // link register specified in rd.
-void RiscVIJal(const Instruction *instruction);
+void RiscVIJal(const Instruction* instruction);
 // Source operand 0 refers to the base registers specified by rs1, source
 // operand 1 contains the immediate value. Destination operand 0 refers to the
 // pc destination operand, wheras destination operand 1 refers to the
 // link register specified in rd.
-void RiscVIJalr(const Instruction *instruction);
+void RiscVIJalr(const Instruction* instruction);
 // For the following branch instructions. Source operand 0 refers to the
 // register specified by rs1, source operand 2 refers to the register specified
 // by rs2, and source operand 3 refers to the immediate offset. Destination
 // operand 0 refers to the pc destination operand.
-void RiscVIBeq(const Instruction *instruction);
-void RiscVIBne(const Instruction *instruction);
-void RiscVIBlt(const Instruction *instruction);
-void RiscVIBltu(const Instruction *instruction);
-void RiscVIBge(const Instruction *instruction);
-void RiscVIBgeu(const Instruction *instruction);
+void RiscVIBeq(const Instruction* instruction);
+void RiscVIBne(const Instruction* instruction);
+void RiscVIBlt(const Instruction* instruction);
+void RiscVIBltu(const Instruction* instruction);
+void RiscVIBge(const Instruction* instruction);
+void RiscVIBgeu(const Instruction* instruction);
 // Each of the load instructions are modeled by a pair of semantic instruction
 // functions. The "main" function computes the effective address and initiates
 // the load, the "child" function processes the load result and writes it back
@@ -84,24 +84,24 @@
 // source operand 1 the offset. Destination operand 0 is the register specified
 // by rd. The "child" semantic function will get a copy of the destination
 // operand.
-void RiscVILd(const Instruction *instruction);
-void RiscVILw(const Instruction *instruction);
-void RiscVILwChild(const Instruction *instruction);
-void RiscVILh(const Instruction *instruction);
-void RiscVILhChild(const Instruction *instruction);
-void RiscVILhu(const Instruction *instruction);
-void RiscVILhuChild(const Instruction *instruction);
-void RiscVILb(const Instruction *instruction);
-void RiscVILbChild(const Instruction *instruction);
-void RiscVILbu(const Instruction *instruction);
-void RiscVILbuChild(const Instruction *instruction);
+void RiscVILd(const Instruction* instruction);
+void RiscVILw(const Instruction* instruction);
+void RiscVILwChild(const Instruction* instruction);
+void RiscVILh(const Instruction* instruction);
+void RiscVILhChild(const Instruction* instruction);
+void RiscVILhu(const Instruction* instruction);
+void RiscVILhuChild(const Instruction* instruction);
+void RiscVILb(const Instruction* instruction);
+void RiscVILbChild(const Instruction* instruction);
+void RiscVILbu(const Instruction* instruction);
+void RiscVILbuChild(const Instruction* instruction);
 // For each store instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVISd(const Instruction *instruction);
-void RiscVISw(const Instruction *instruction);
-void RiscVISh(const Instruction *instruction);
-void RiscVISb(const Instruction *instruction);
+void RiscVISd(const Instruction* instruction);
+void RiscVISw(const Instruction* instruction);
+void RiscVISh(const Instruction* instruction);
+void RiscVISb(const Instruction* instruction);
 
 }  // namespace RV32
 
@@ -110,48 +110,48 @@
 // For the following, source operand 0 refers to the register specified in rs1,
 // and source operand 1 refers to either the register specified in rs2, or the
 // immediate. Destination operand 0 refers to the register specified in rd.
-void RiscVIAdd(const Instruction *instruction);
-void RiscVIAddw(const Instruction *instruction);
-void RiscVISub(const Instruction *instruction);
-void RiscVISubw(const Instruction *instruction);
-void RiscVISlt(const Instruction *instruction);
-void RiscVISltu(const Instruction *instruction);
-void RiscVIAnd(const Instruction *instruction);
-void RiscVIOr(const Instruction *instruction);
-void RiscVIXor(const Instruction *instruction);
-void RiscVISll(const Instruction *instruction);
-void RiscVISrl(const Instruction *instruction);
-void RiscVISra(const Instruction *instruction);
-void RiscVISllw(const Instruction *instruction);
-void RiscVISrlw(const Instruction *instruction);
-void RiscVISraw(const Instruction *instruction);
+void RiscVIAdd(const Instruction* instruction);
+void RiscVIAddw(const Instruction* instruction);
+void RiscVISub(const Instruction* instruction);
+void RiscVISubw(const Instruction* instruction);
+void RiscVISlt(const Instruction* instruction);
+void RiscVISltu(const Instruction* instruction);
+void RiscVIAnd(const Instruction* instruction);
+void RiscVIOr(const Instruction* instruction);
+void RiscVIXor(const Instruction* instruction);
+void RiscVISll(const Instruction* instruction);
+void RiscVISrl(const Instruction* instruction);
+void RiscVISra(const Instruction* instruction);
+void RiscVISllw(const Instruction* instruction);
+void RiscVISrlw(const Instruction* instruction);
+void RiscVISraw(const Instruction* instruction);
 // For the following two semantic functions, source operand 0 refers to the
 // immediate value, and destination 0 the register specified in rd. Note, the
 // value of the immediate shall be properly shifted.
-void RiscVILui(const Instruction *instruction);
-void RiscVIAuipc(const Instruction *instruction);
+void RiscVILui(const Instruction* instruction);
+void RiscVIAuipc(const Instruction* instruction);
 // No operands necessary for Nop. For now, all hint instructions should be
 // decoded as Nop.
-void RiscVINop(const Instruction *instruction);
+void RiscVINop(const Instruction* instruction);
 // Source operand 0 contains the immediate value. Destination operand 0 refers
 // to the pc destination operand, wheras destination operand 1 refers to the
 // link register specified in rd.
-void RiscVIJal(const Instruction *instruction);
+void RiscVIJal(const Instruction* instruction);
 // Source operand 0 refers to the base registers specified by rs1, source
 // operand 1 contains the immediate value. Destination operand 0 refers to the
 // pc destination operand, wheras destination operand 1 refers to the
 // link register specified in rd.
-void RiscVIJalr(const Instruction *instruction);
+void RiscVIJalr(const Instruction* instruction);
 // For the following branch instructions. Source operand 0 refers to the
 // register specified by rs1, source operand 2 refers to the register specified
 // by rs2, and source operand 3 refers to the immediate offset. Destination
 // operand 0 refers to the pc destination operand.
-void RiscVIBeq(const Instruction *instruction);
-void RiscVIBne(const Instruction *instruction);
-void RiscVIBlt(const Instruction *instruction);
-void RiscVIBltu(const Instruction *instruction);
-void RiscVIBge(const Instruction *instruction);
-void RiscVIBgeu(const Instruction *instruction);
+void RiscVIBeq(const Instruction* instruction);
+void RiscVIBne(const Instruction* instruction);
+void RiscVIBlt(const Instruction* instruction);
+void RiscVIBltu(const Instruction* instruction);
+void RiscVIBge(const Instruction* instruction);
+void RiscVIBgeu(const Instruction* instruction);
 // Each of the load instructions are modeled by a pair of semantic instruction
 // functions. The "main" function computes the effective address and initiates
 // the load, the "child" function processes the load result and writes it back
@@ -160,27 +160,27 @@
 // source operand 1 the offset. Destination operand 0 is the register specified
 // by rd. The "child" semantic function will get a copy of the destination
 // operand.
-void RiscVILd(const Instruction *instruction);
-void RiscVILdChild(const Instruction *instruction);
-void RiscVILw(const Instruction *instruction);
-void RiscVILwChild(const Instruction *instruction);
-void RiscVILwu(const Instruction *instruction);
-void RiscVILwuChild(const Instruction *instruction);
-void RiscVILh(const Instruction *instruction);
-void RiscVILhChild(const Instruction *instruction);
-void RiscVILhu(const Instruction *instruction);
-void RiscVILhuChild(const Instruction *instruction);
-void RiscVILb(const Instruction *instruction);
-void RiscVILbChild(const Instruction *instruction);
-void RiscVILbu(const Instruction *instruction);
-void RiscVILbuChild(const Instruction *instruction);
+void RiscVILd(const Instruction* instruction);
+void RiscVILdChild(const Instruction* instruction);
+void RiscVILw(const Instruction* instruction);
+void RiscVILwChild(const Instruction* instruction);
+void RiscVILwu(const Instruction* instruction);
+void RiscVILwuChild(const Instruction* instruction);
+void RiscVILh(const Instruction* instruction);
+void RiscVILhChild(const Instruction* instruction);
+void RiscVILhu(const Instruction* instruction);
+void RiscVILhuChild(const Instruction* instruction);
+void RiscVILb(const Instruction* instruction);
+void RiscVILbChild(const Instruction* instruction);
+void RiscVILbu(const Instruction* instruction);
+void RiscVILbuChild(const Instruction* instruction);
 // For each store instruction semantic function, source operand 0 is the base
 // register, source operand 1 is the offset, while source operand 2 is the value
 // to be stored referred to by rs2.
-void RiscVISd(const Instruction *instruction);
-void RiscVISw(const Instruction *instruction);
-void RiscVISh(const Instruction *instruction);
-void RiscVISb(const Instruction *instruction);
+void RiscVISd(const Instruction* instruction);
+void RiscVISw(const Instruction* instruction);
+void RiscVISh(const Instruction* instruction);
+void RiscVISb(const Instruction* instruction);
 
 }  // namespace RV64
 
@@ -188,19 +188,19 @@
 // c.unimp instructions are issued. The instruction takes an unknown instruction
 // exception, but does not print a log message.
 // The instruction does not take any operands.
-void RiscVIUnimplemented(const Instruction *instruction);
+void RiscVIUnimplemented(const Instruction* instruction);
 
 // The Fence instruction takes two source operands, the 4 bit values of the
 // predecessor and successor sets.
-void RiscVIFence(const Instruction *instruction);
+void RiscVIFence(const Instruction* instruction);
 // The Fence.tso takes no operands.
-void RiscVIFenceTso(const Instruction *instruction);
+void RiscVIFenceTso(const Instruction* instruction);
 // Ecall and EBreak take no source or destination operands.
-void RiscVIEcall(const Instruction *instruction);
-void RiscVIEbreak(const Instruction *instruction);
+void RiscVIEcall(const Instruction* instruction);
+void RiscVIEbreak(const Instruction* instruction);
 // Trap doesn't implement any specific instruction, but can be called as an
 // instruction, for instance for unknown instructions.
-void RiscVITrap(bool is_interrupt, uint32_t cause, Instruction *instruction);
+void RiscVITrap(bool is_interrupt, uint32_t cause, Instruction* instruction);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_instruction_helpers.h b/riscv/riscv_instruction_helpers.h
index 8999576..89d6050 100644
--- a/riscv/riscv_instruction_helpers.h
+++ b/riscv/riscv_instruction_helpers.h
@@ -73,20 +73,20 @@
 // Generic helper function for floating op instructions that do not require
 // NaN boxing since they produce non fp-values, but set fflags.
 template <typename Result, typename From, typename To>
-inline void RiscVConvertFloatWithFflagsOp(const Instruction *instruction) {
+inline void RiscVConvertFloatWithFflagsOp(const Instruction* instruction) {
   constexpr To kMax = std::numeric_limits<To>::max();
   constexpr To kMin = std::numeric_limits<To>::min();
 
   From lhs = generic::GetInstructionSource<From>(instruction, 0);
   using FromUint = typename FPTypeInfo<From>::UIntType;
-  FromUint lhs_u = *reinterpret_cast<FromUint *>(&lhs);
+  FromUint lhs_u = *reinterpret_cast<FromUint*>(&lhs);
   auto constexpr kExpMask = FPTypeInfo<From>::kExpMask;
   auto constexpr kSigMask = FPTypeInfo<From>::kSigMask;
   uint32_t flags = 0;
   uint32_t rm = generic::GetInstructionSource<uint32_t>(instruction, 1);
   // Dynamic rounding mode will get rounding mode from the global state.
   if (rm == *FPRoundingMode::kDynamic) {
-    auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+    auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
     if (!rv_fp->rounding_mode_valid()) {
       LOG(ERROR) << "Invalid rounding mode";
       return;
@@ -111,7 +111,7 @@
     auto constexpr kSigSize = FPTypeInfo<From>::kSigSize;
     auto constexpr kSigMask = FPTypeInfo<From>::kSigMask;
     auto constexpr kBitSize = FPTypeInfo<From>::kBitSize;
-    FromUint lhs_u = *reinterpret_cast<FromUint *>(&lhs);
+    FromUint lhs_u = *reinterpret_cast<FromUint*>(&lhs);
     const bool sign = (lhs_u & (1ULL << (kBitSize - 1))) != 0;
     FromUint exp = kExpMask & lhs_u;
     int exp_value = exp >> kSigSize;
@@ -264,17 +264,17 @@
     }
   }
   using SignedTo = typename std::make_signed<To>::type;
-  auto *dest = instruction->Destination(0);
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<Result> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* dest = instruction->Destination(0);
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<Result>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   // The final value is sign-extended to the register width, even if it's
   // conversion to an unsigned value.
   SignedTo signed_value = static_cast<SignedTo>(value);
   Result dest_value = static_cast<Result>(signed_value);
   reg->data_buffer()->template Set<Result>(0, dest_value);
   if (flags) {
-    auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+    auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
     flag_db->Set<uint32_t>(0, flags);
     flag_db->Submit();
   }
@@ -283,7 +283,7 @@
 // Helper function to read a NaN boxed source value, converting it to NaN if
 // it isn't formatted properly.
 template <typename RegValue, typename Argument>
-inline Argument GetNaNBoxedSource(const Instruction *instruction, int arg) {
+inline Argument GetNaNBoxedSource(const Instruction* instruction, int arg) {
   if (sizeof(RegValue) <= sizeof(Argument)) {
     return generic::GetInstructionSource<Argument>(instruction, arg);
   } else {
@@ -291,7 +291,7 @@
     UInt uval = generic::GetInstructionSource<UInt>(instruction, arg);
     UInt mask = std::numeric_limits<UInt>::max() << (sizeof(Argument) * 8);
     if (((mask & uval) != mask)) {
-      return *reinterpret_cast<const Argument *>(
+      return *reinterpret_cast<const Argument*>(
           &FPTypeInfo<Argument>::kCanonicalNaN);
     }
     return generic::GetInstructionSource<Argument>(instruction, arg);
@@ -300,13 +300,13 @@
 
 // Generic helper function for binary instructions.
 template <typename Register, typename Result, typename Argument>
-inline void RiscVBinaryOp(const Instruction *instruction,
+inline void RiscVBinaryOp(const Instruction* instruction,
                           std::function<Result(Argument, Argument)> operation) {
   using RegValue = typename Register::ValueType;
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   Argument rhs = generic::GetInstructionSource<Argument>(instruction, 1);
   Result dest_value = operation(lhs, rhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
@@ -315,9 +315,9 @@
 // Generic helper function for writing a value to a register by destination
 // operand index.
 template <typename Register, typename Value>
-inline void RiscVWriteReg(const Instruction *instruction, int index,
+inline void RiscVWriteReg(const Instruction* instruction, int index,
                           Value value) {
-  auto *reg = static_cast<generic::RegisterDestinationOperand<Value> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<Value>*>(
                   instruction->Destination(index))
                   ->GetRegister();
   reg->data_buffer()->template Set<Value>(0, value);
@@ -325,12 +325,12 @@
 
 // Generic helper function for unary instructions.
 template <typename Register, typename Result, typename Argument>
-inline void RiscVUnaryOp(const Instruction *instruction,
+inline void RiscVUnaryOp(const Instruction* instruction,
                          std::function<Result(Argument)> operation) {
   using RegValue = typename Register::ValueType;
   auto lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   Result dest_value = operation(lhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
@@ -339,7 +339,7 @@
 // Helper function for conditional branches.
 template <typename RegisterType, typename ValueType>
 static inline void BranchConditional(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<bool(ValueType, ValueType)> cond) {
   using UIntType =
       typename std::make_unsigned<typename RegisterType::ValueType>::type;
@@ -348,26 +348,26 @@
   if (cond(a, b)) {
     UIntType offset = generic::GetInstructionSource<UIntType>(instruction, 2);
     UIntType target = offset + instruction->address();
-    auto *db = instruction->Destination(0)->AllocateDataBuffer();
+    auto* db = instruction->Destination(0)->AllocateDataBuffer();
     db->SetSubmit<UIntType>(0, target);
-    auto state = static_cast<RiscVState *>(instruction->state());
+    auto state = static_cast<RiscVState*>(instruction->state());
     state->set_branch(true);
   }
 }
 
 // Generic helper function for load instructions.
 template <typename Register, typename ValueType>
-inline void RVLoad(const Instruction *instruction) {
+inline void RVLoad(const Instruction* instruction) {
   using RegVal = typename Register::ValueType;
   using URegVal = typename std::make_unsigned<RegVal>::type;
   URegVal base = generic::GetInstructionSource<URegVal>(instruction, 0);
   RegVal offset = generic::GetInstructionSource<RegVal>(instruction, 1);
   URegVal address = base + offset;
-  auto *value_db =
+  auto* value_db =
       instruction->state()->db_factory()->Allocate(sizeof(ValueType));
   value_db->set_latency(0);
-  auto *context = new LoadContext(value_db);
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* context = new LoadContext(value_db);
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->LoadMemory(instruction, address, value_db, instruction->child(),
                     context);
   context->DecRef();
@@ -375,12 +375,12 @@
 
 // Generic helper function for load instructions' "child instruction".
 template <typename Register, typename ValueType>
-inline void RVLoadChild(const Instruction *instruction) {
+inline void RVLoadChild(const Instruction* instruction) {
   using RegVal = typename Register::ValueType;
   using URegVal = typename std::make_unsigned<RegVal>::type;
   using SRegVal = typename std::make_signed<URegVal>::type;
-  LoadContext *context = static_cast<LoadContext *>(instruction->context());
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegVal> *>(
+  LoadContext* context = static_cast<LoadContext*>(instruction->context());
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegVal>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   if (std::is_signed<ValueType>::value) {
@@ -394,7 +394,7 @@
 
 // Generic helper function for store instructions.
 template <typename RegisterType, typename ValueType>
-inline void RVStore(const Instruction *instruction) {
+inline void RVStore(const Instruction* instruction) {
   using URegVal =
       typename std::make_unsigned<typename RegisterType::ValueType>::type;
   using SRegVal = typename std::make_signed<URegVal>::type;
@@ -402,8 +402,8 @@
   SRegVal offset = generic::GetInstructionSource<SRegVal>(instruction, 1);
   URegVal address = base + offset;
   ValueType value = generic::GetInstructionSource<ValueType>(instruction, 2);
-  auto *state = static_cast<RiscVState *>(instruction->state());
-  auto *db = state->db_factory()->Allocate(sizeof(ValueType));
+  auto* state = static_cast<RiscVState*>(instruction->state());
+  auto* db = state->db_factory()->Allocate(sizeof(ValueType));
   db->Set<ValueType>(0, value);
   state->StoreMemory(instruction, address, db);
   db->DecRef();
@@ -414,12 +414,12 @@
 // not really executing an fp operation that requires rounding.
 template <typename RegValue, typename Result, typename Argument>
 inline void RiscVBinaryNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<RegValue, Argument>(instruction, 0);
   Argument rhs = GetNaNBoxedSource<RegValue, Argument>(instruction, 1);
   Result dest_value = operation(lhs, rhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -428,7 +428,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<RegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(RegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -441,11 +441,11 @@
 // Generic helper function for unary instructions with NaN boxing.
 template <typename DstRegValue, typename SrcRegValue, typename Result,
           typename Argument>
-inline void RiscVUnaryNaNBoxOp(const Instruction *instruction,
+inline void RiscVUnaryNaNBoxOp(const Instruction* instruction,
                                std::function<Result(Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<SrcRegValue, Argument>(instruction, 0);
   Result dest_value = operation(lhs);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -454,7 +454,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<DstRegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(DstRegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -468,7 +468,7 @@
 // difference is that it handles rounding mode and performs NaN boxing.
 template <typename DstRegValue, typename SrcRegValue, typename Result,
           typename Argument>
-inline void RiscVUnaryFloatNaNBoxOp(const Instruction *instruction,
+inline void RiscVUnaryFloatNaNBoxOp(const Instruction* instruction,
                                     std::function<Result(Argument)> operation) {
   using ResUint = typename FPTypeInfo<Result>::UIntType;
   Argument lhs = GetNaNBoxedSource<SrcRegValue, Argument>(instruction, 0);
@@ -476,7 +476,7 @@
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
   // If the rounding mode is dynamic, read it from the current state.
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
       LOG(ERROR) << "Invalid rounding mode";
@@ -491,21 +491,21 @@
   }
   if (FPTypeInfo<Result>::IsNaN(dest_value) &&
       FPTypeInfo<Result>::SignBit(dest_value)) {
-    ResUint res_value = *reinterpret_cast<ResUint *>(&dest_value);
+    ResUint res_value = *reinterpret_cast<ResUint*>(&dest_value);
     res_value &= FPTypeInfo<Result>::kInfMask;
-    dest_value = *reinterpret_cast<Result *>(&res_value);
+    dest_value = *reinterpret_cast<Result*>(&res_value);
   }
-  auto *dest = instruction->Destination(0);
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* dest = instruction->Destination(0);
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   // Check to see if we need to NaN box the result.
   if (sizeof(DstRegValue) > sizeof(Result)) {
     // If the floating point Value is narrower than the register, the upper
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<DstRegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(DstRegValue) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -518,13 +518,13 @@
 // Generic helper function for floating op instructions that do not require
 // NaN boxing since they produce non fp-values.
 template <typename Result, typename Argument>
-inline void RiscVUnaryFloatOp(const Instruction *instruction,
+inline void RiscVUnaryFloatOp(const Instruction* instruction,
                               std::function<Result(Argument)> operation) {
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -538,11 +538,11 @@
     ScopedFPStatus set_fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(lhs);
   }
-  auto *dest = instruction->Destination(0);
+  auto* dest = instruction->Destination(0);
   using UInt = typename FPTypeInfo<Result>::UIntType;
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<UInt> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<UInt>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
 }
 
@@ -550,13 +550,13 @@
 // NaN boxing since they produce non fp-values, but set fflags.
 template <typename Result, typename Argument>
 inline void RiscVUnaryFloatWithFflagsOp(
-    const Instruction *instruction,
-    std::function<Result(Argument, uint32_t &)> operation) {
+    const Instruction* instruction,
+    std::function<Result(Argument, uint32_t&)> operation) {
   Argument lhs = generic::GetInstructionSource<Argument>(instruction, 0);
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -571,13 +571,13 @@
     ScopedFPStatus set_fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(lhs, flag);
   }
-  auto *dest = instruction->Destination(0);
+  auto* dest = instruction->Destination(0);
   using UInt = typename FPTypeInfo<Result>::UIntType;
-  auto *reg_dest =
-      static_cast<generic::RegisterDestinationOperand<UInt> *>(dest);
-  auto *reg = reg_dest->GetRegister();
+  auto* reg_dest =
+      static_cast<generic::RegisterDestinationOperand<UInt>*>(dest);
+  auto* reg = reg_dest->GetRegister();
   reg->data_buffer()->template Set<Result>(0, dest_value);
-  auto *flag_db = instruction->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = instruction->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, flag);
   flag_db->Submit();
 }
@@ -586,7 +586,7 @@
 // difference is that it handles rounding mode.
 template <typename Register, typename Result, typename Argument>
 inline void RiscVBinaryFloatNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument)> operation) {
   Argument lhs = GetNaNBoxedSource<Register, Argument>(instruction, 0);
   Argument rhs = GetNaNBoxedSource<Register, Argument>(instruction, 1);
@@ -594,7 +594,7 @@
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 2);
 
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -609,10 +609,10 @@
     dest_value = operation(lhs, rhs);
   }
   if (FPTypeInfo<Result>::IsNaN(dest_value)) {
-    *reinterpret_cast<typename FPTypeInfo<Result>::UIntType *>(&dest_value) =
+    *reinterpret_cast<typename FPTypeInfo<Result>::UIntType*>(&dest_value) =
         FPTypeInfo<Result>::kCanonicalNaN;
   }
-  auto *reg = static_cast<generic::RegisterDestinationOperand<Register> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<Register>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -621,7 +621,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<Register>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(Register) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -634,7 +634,7 @@
 // Generic helper function for ternary floating point instructions.
 template <typename Register, typename Result, typename Argument>
 inline void RiscVTernaryFloatNaNBoxOp(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<Result(Argument, Argument, Argument)> operation) {
   Argument rs1 = generic::GetInstructionSource<Argument>(instruction, 0);
   Argument rs2 = generic::GetInstructionSource<Argument>(instruction, 1);
@@ -642,7 +642,7 @@
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 3);
 
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -656,7 +656,7 @@
     ScopedFPStatus fp_status(rv_fp->host_fp_interface(), rm_value);
     dest_value = operation(rs1, rs2, rs3);
   }
-  auto *reg = static_cast<generic::RegisterDestinationOperand<Register> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<Register>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   // Check to see if we need to NaN box the result.
@@ -665,7 +665,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<Register>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * (sizeof(Register) - sizeof(Result));
     reg_value = (reg_value << shift) | dest_u_value;
@@ -679,7 +679,7 @@
 template <typename T>
 typename FPTypeInfo<T>::UIntType ClassifyFP(T val) {
   using UIntType = typename FPTypeInfo<T>::UIntType;
-  auto int_value = *reinterpret_cast<UIntType *>(&val);
+  auto int_value = *reinterpret_cast<UIntType*>(&val);
   UIntType sign = int_value >> (FPTypeInfo<T>::kBitSize - 1);
   UIntType exp_mask = (1 << FPTypeInfo<T>::kExpSize) - 1;
   UIntType exp = (int_value >> FPTypeInfo<T>::kSigSize) & exp_mask;
diff --git a/riscv/riscv_instrumentation_control.cc b/riscv/riscv_instrumentation_control.cc
index 24d913b..cea4aac 100644
--- a/riscv/riscv_instrumentation_control.cc
+++ b/riscv/riscv_instrumentation_control.cc
@@ -34,8 +34,8 @@
 using ::mpact::sim::util::MemoryUseProfiler;
 
 RiscVInstrumentationControl::RiscVInstrumentationControl(
-    DebugCommandShell *shell, RiscVTop *riscv_top,
-    MemoryUseProfiler *mem_profiler)
+    DebugCommandShell* shell, RiscVTop* riscv_top,
+    MemoryUseProfiler* mem_profiler)
     : shell_(shell),
       top_(riscv_top),
       mem_profiler_(mem_profiler),
@@ -44,8 +44,8 @@
 }
 
 bool RiscVInstrumentationControl::PerformShellCommand(
-    absl::string_view input, const DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    absl::string_view input, const DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   std::string cmd;
   std::string what;
   std::string where;
@@ -116,7 +116,7 @@
       return true;
     }
     // Let's see if it is a symbol.
-    auto *loader = core_access.loader_getter();
+    auto* loader = core_access.loader_getter();
     if (loader == nullptr) {
       output = "Error: cannot perform symbol lookup";
       return true;
diff --git a/riscv/riscv_instrumentation_control.h b/riscv/riscv_instrumentation_control.h
index af5f937..911eb08 100644
--- a/riscv/riscv_instrumentation_control.h
+++ b/riscv/riscv_instrumentation_control.h
@@ -29,19 +29,19 @@
 
 class RiscVInstrumentationControl {
  public:
-  RiscVInstrumentationControl(DebugCommandShell *shell, RiscVTop *riscv_top,
-                              util::MemoryUseProfiler *mem_profiler);
+  RiscVInstrumentationControl(DebugCommandShell* shell, RiscVTop* riscv_top,
+                              util::MemoryUseProfiler* mem_profiler);
 
   bool PerformShellCommand(absl::string_view input,
-                           const DebugCommandShell::CoreAccess &core_access,
-                           std::string &output);
+                           const DebugCommandShell::CoreAccess& core_access,
+                           std::string& output);
 
   std::string Usage() const;
 
  private:
-  DebugCommandShell *shell_;
-  RiscVTop *top_ = nullptr;
-  util::MemoryUseProfiler *mem_profiler_;
+  DebugCommandShell* shell_;
+  RiscVTop* top_ = nullptr;
+  util::MemoryUseProfiler* mem_profiler_;
   LazyRE2 pattern_re_;
 };
 
diff --git a/riscv/riscv_jvt.h b/riscv/riscv_jvt.h
index 0e89765..c8aa3a8 100644
--- a/riscv/riscv_jvt.h
+++ b/riscv/riscv_jvt.h
@@ -27,7 +27,7 @@
 class RiscVJvtCsr : public RiscVSimpleCsr<T> {
  public:
   RiscVJvtCsr(std::string name, RiscVCsrEnum index, T initial_value,
-              RiscVState *state)
+              RiscVState* state)
       : RiscVSimpleCsr<T>(name, index, initial_value, state) {}
   // Clear the low 6 bits of the value (sets mode to 0b00'0000). This will be
   // modified as any new modes are added.
diff --git a/riscv/riscv_m_instructions.cc b/riscv/riscv_m_instructions.cc
index 5761595..c7e231f 100644
--- a/riscv/riscv_m_instructions.cc
+++ b/riscv/riscv_m_instructions.cc
@@ -38,7 +38,7 @@
 using IntReg = typename std::make_signed<RV32Register::ValueType>::type;
 using WideIntReg = typename WideType<IntReg>::type;
 
-void MMul(Instruction *instruction) {
+void MMul(Instruction* instruction) {
   BinaryOp<UintReg, WideIntReg>(instruction, [](WideIntReg a_wide,
                                                 WideIntReg b_wide) {
     WideIntReg c_wide = a_wide * b_wide;
@@ -46,21 +46,21 @@
   });
 }
 
-void MMulh(Instruction *instruction) {
+void MMulh(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](WideIntReg a_wide, WideIntReg b_wide) {
     WideIntReg c_wide = a_wide * b_wide;
     return static_cast<IntReg>(c_wide >> 32);
   });
 }
 
-void MMulhu(Instruction *instruction) {
+void MMulhu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](WideUintReg a_wide, WideUintReg b_wide) {
     WideUintReg c_wide = a_wide * b_wide;
     return static_cast<UintReg>(c_wide >> 32);
   });
 }
 
-void MMulhsu(Instruction *instruction) {
+void MMulhsu(Instruction* instruction) {
   BinaryOp<UintReg, WideIntReg, WideUintReg>(
       instruction, [](WideIntReg a_wide, WideUintReg b_wide) {
         WideIntReg c_wide = a_wide * b_wide;
@@ -68,7 +68,7 @@
       });
 }
 
-void MDiv(Instruction *instruction) {
+void MDiv(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](IntReg a, IntReg b) -> IntReg {
     if (b == 0) return -1;
     if ((b == -1) && (a == std::numeric_limits<IntReg>::min())) {
@@ -78,14 +78,14 @@
   });
 }
 
-void MDivu(Instruction *instruction) {
+void MDivu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](UintReg a, UintReg b) -> UintReg {
     if (b == 0) return std::numeric_limits<UintReg>::max();
     return a / b;
   });
 }
 
-void MRem(Instruction *instruction) {
+void MRem(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](IntReg a, IntReg b) -> IntReg {
     if (b == 0) return a;
     if ((b == -1) && (a == std::numeric_limits<IntReg>::min())) {
@@ -95,7 +95,7 @@
   });
 }
 
-void MRemu(Instruction *instruction) {
+void MRemu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](UintReg a, UintReg b) {
     if (b == 0) return a;
     return a % b;
@@ -114,7 +114,7 @@
 using WideIntReg = typename WideType<IntReg>::type;
 using NarrowIntReg = typename NarrowType<IntReg>::type;
 
-void MMul(Instruction *instruction) {
+void MMul(Instruction* instruction) {
   BinaryOp<UintReg, WideIntReg>(instruction, [](WideIntReg a_wide,
                                                 WideIntReg b_wide) {
     WideIntReg c_wide = a_wide * b_wide;
@@ -122,21 +122,21 @@
   });
 }
 
-void MMulh(Instruction *instruction) {
+void MMulh(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](WideIntReg a_wide, WideIntReg b_wide) {
     WideIntReg c_wide = a_wide * b_wide;
     return static_cast<IntReg>(c_wide >> 64);
   });
 }
 
-void MMulhu(Instruction *instruction) {
+void MMulhu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](WideUintReg a_wide, WideUintReg b_wide) {
     WideUintReg c_wide = a_wide * b_wide;
     return static_cast<UintReg>(c_wide >> 64);
   });
 }
 
-void MMulhsu(Instruction *instruction) {
+void MMulhsu(Instruction* instruction) {
   BinaryOp<UintReg, WideIntReg, WideUintReg>(
       instruction, [](WideIntReg a_wide, WideUintReg b_wide) {
         bool negate = false;
@@ -156,7 +156,7 @@
       });
 }
 
-void MDiv(Instruction *instruction) {
+void MDiv(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](IntReg a, IntReg b) -> IntReg {
     if (b == 0) return -1;
     if ((b == -1) && (a == std::numeric_limits<IntReg>::min())) {
@@ -166,14 +166,14 @@
   });
 }
 
-void MDivu(Instruction *instruction) {
+void MDivu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](UintReg a, UintReg b) -> UintReg {
     if (b == 0) return std::numeric_limits<UintReg>::max();
     return a / b;
   });
 }
 
-void MRem(Instruction *instruction) {
+void MRem(Instruction* instruction) {
   BinaryOp<IntReg>(instruction, [](IntReg a, IntReg b) -> IntReg {
     if (b == 0) return a;
     if ((b == -1) && (a == std::numeric_limits<IntReg>::min())) {
@@ -183,14 +183,14 @@
   });
 }
 
-void MRemu(Instruction *instruction) {
+void MRemu(Instruction* instruction) {
   BinaryOp<UintReg>(instruction, [](UintReg a, UintReg b) {
     if (b == 0) return a;
     return a % b;
   });
 }
 
-void MMulw(Instruction *instruction) {
+void MMulw(Instruction* instruction) {
   BinaryOp<IntReg, NarrowIntReg>(instruction,
                                  [](NarrowIntReg a, NarrowIntReg b) -> IntReg {
                                    NarrowIntReg c = a * b;
@@ -199,7 +199,7 @@
                                  });
 }
 
-void MDivw(Instruction *instruction) {
+void MDivw(Instruction* instruction) {
   BinaryOp<IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) -> IntReg {
         if (b == 0) return static_cast<IntReg>(-1);
@@ -211,7 +211,7 @@
       });
 }
 
-void MDivuw(Instruction *instruction) {
+void MDivuw(Instruction* instruction) {
   BinaryOp<IntReg, NarrowUintReg>(
       instruction, [](NarrowUintReg a, NarrowUintReg b) -> IntReg {
         if (b == 0) return std::numeric_limits<UintReg>::max();
@@ -219,7 +219,7 @@
       });
 }
 
-void MRemw(Instruction *instruction) {
+void MRemw(Instruction* instruction) {
   BinaryOp<IntReg, NarrowIntReg>(
       instruction, [](NarrowIntReg a, NarrowIntReg b) -> IntReg {
         if (b == 0) return static_cast<IntReg>(a);
@@ -230,7 +230,7 @@
       });
 }
 
-void MRemuw(Instruction *instruction) {
+void MRemuw(Instruction* instruction) {
   BinaryOp<IntReg, NarrowUintReg>(
       instruction, [](NarrowUintReg a, NarrowUintReg b) -> IntReg {
         if (b == 0) return static_cast<IntReg>(static_cast<NarrowIntReg>(a));
diff --git a/riscv/riscv_m_instructions.h b/riscv/riscv_m_instructions.h
index b2f6fbb..055e7d3 100644
--- a/riscv/riscv_m_instructions.h
+++ b/riscv/riscv_m_instructions.h
@@ -27,33 +27,33 @@
 // and rd as destination operand 0.
 namespace RV32 {
 
-void MMul(Instruction *instruction);
-void MMulh(Instruction *instruction);
-void MMulhu(Instruction *instruction);
-void MMulhsu(Instruction *instruction);
-void MDiv(Instruction *instruction);
-void MDivu(Instruction *instruction);
-void MRem(Instruction *instruction);
-void MRemu(Instruction *instruction);
+void MMul(Instruction* instruction);
+void MMulh(Instruction* instruction);
+void MMulhu(Instruction* instruction);
+void MMulhsu(Instruction* instruction);
+void MDiv(Instruction* instruction);
+void MDivu(Instruction* instruction);
+void MRem(Instruction* instruction);
+void MRemu(Instruction* instruction);
 
 }  // namespace RV32
 
 namespace RV64 {
 
-void MMul(Instruction *instruction);
-void MMulh(Instruction *instruction);
-void MMulhu(Instruction *instruction);
-void MMulhsu(Instruction *instruction);
-void MDiv(Instruction *instruction);
-void MDivu(Instruction *instruction);
-void MRem(Instruction *instruction);
-void MRemu(Instruction *instruction);
+void MMul(Instruction* instruction);
+void MMulh(Instruction* instruction);
+void MMulhu(Instruction* instruction);
+void MMulhsu(Instruction* instruction);
+void MDiv(Instruction* instruction);
+void MDivu(Instruction* instruction);
+void MRem(Instruction* instruction);
+void MRemu(Instruction* instruction);
 
-void MMulw(Instruction *instruction);
-void MDivw(Instruction *instruction);
-void MDivuw(Instruction *instruction);
-void MRemw(Instruction *instruction);
-void MRemuw(Instruction *instruction);
+void MMulw(Instruction* instruction);
+void MDivw(Instruction* instruction);
+void MDivuw(Instruction* instruction);
+void MRemw(Instruction* instruction);
+void MRemuw(Instruction* instruction);
 }  // namespace RV64
 
 }  // namespace riscv
diff --git a/riscv/riscv_misa.cc b/riscv/riscv_misa.cc
index b6d66ee..6a9da83 100644
--- a/riscv/riscv_misa.cc
+++ b/riscv/riscv_misa.cc
@@ -40,10 +40,10 @@
 }
 
 // Constructors.
-RiscVMIsa::RiscVMIsa(uint32_t initial_value, ArchState *state)
+RiscVMIsa::RiscVMIsa(uint32_t initial_value, ArchState* state)
     : RiscVMIsa(StretchMisa32(initial_value), state) {}
 
-RiscVMIsa::RiscVMIsa(uint64_t initial_value, ArchState *state)
+RiscVMIsa::RiscVMIsa(uint64_t initial_value, ArchState* state)
     : RiscVSimpleCsr<uint64_t>("misa", RiscVCsrEnum::kMIsa, initial_value,
                                /*read_mask*/ 0xc000'0000'03ff'ffffULL,
                                /*write_mask*/ 0, state) {
diff --git a/riscv/riscv_misa.h b/riscv/riscv_misa.h
index d8ec1b5..3edb00e 100644
--- a/riscv/riscv_misa.h
+++ b/riscv/riscv_misa.h
@@ -35,8 +35,8 @@
  public:
   // Disable default constructor.
   RiscVMIsa() = delete;
-  RiscVMIsa(uint32_t initial_value, ArchState *state);
-  RiscVMIsa(uint64_t initial_value, ArchState *state);
+  RiscVMIsa(uint32_t initial_value, ArchState* state);
+  RiscVMIsa(uint64_t initial_value, ArchState* state);
   ~RiscVMIsa() override = default;
 
   // RiscVSimpleCsr method overrides.
diff --git a/riscv/riscv_plic.cc b/riscv/riscv_plic.cc
index 10fb89c..0b9be95 100644
--- a/riscv/riscv_plic.cc
+++ b/riscv/riscv_plic.cc
@@ -33,7 +33,7 @@
   // Initialize the gateway info.
   gateway_info_ = new GatewayInfo[num_sources_];
   // Initialize the context interface.
-  context_if_ = new RiscVPlicIrqInterface *[num_contexts_];
+  context_if_ = new RiscVPlicIrqInterface*[num_contexts_];
   context_irq_ = new bool[num_contexts_];
   for (int i = 0; i < num_contexts_; ++i) {
     context_if_[i] = nullptr;
@@ -47,7 +47,7 @@
   std::memset(interrupt_pending_, 0,
               sizeof(uint32_t) * (num_sources_ / 32 + 1));
   // Initialize the interrupt enabled bits.
-  interrupt_enabled_ = new uint32_t *[num_contexts_];
+  interrupt_enabled_ = new uint32_t*[num_contexts_];
   for (int i = 0; i < num_contexts_; ++i) {
     interrupt_enabled_[i] = new uint32_t[num_sources_ / 32 + 1];
     std::memset(interrupt_enabled_[i], 0,
@@ -149,7 +149,7 @@
   // No action for clearing a non-level based interrupt.
   if (!value && !is_level) return;
 
-  auto &info = gateway_info_[source];
+  auto& info = gateway_info_[source];
   if (!info.ready || !value) {
     if (is_level) info.pending = value;
     return;
@@ -197,8 +197,8 @@
 
 // Implementation of the memory load interface for reading memory mapped
 // registers.
-void RiscVPlic::Load(uint64_t address, DataBuffer *db, Instruction *inst,
-                     ReferenceCount *context) {
+void RiscVPlic::Load(uint64_t address, DataBuffer* db, Instruction* inst,
+                     ReferenceCount* context) {
   uint32_t offset = address & 0xff'ffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -237,15 +237,15 @@
 }
 
 // No support for vector loads.
-void RiscVPlic::Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-                     DataBuffer *db, Instruction *inst,
-                     ReferenceCount *context) {
+void RiscVPlic::Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+                     DataBuffer* db, Instruction* inst,
+                     ReferenceCount* context) {
   LOG(FATAL) << "RiscVPlic does not support vector loads";
 }
 
 // Implementation of memory store interface to support writes to memory mapped
 // registers.
-void RiscVPlic::Store(uint64_t address, DataBuffer *db) {
+void RiscVPlic::Store(uint64_t address, DataBuffer* db) {
   uint32_t offset = address & 0xff'ffff;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -262,13 +262,13 @@
   }
 }
 
-void RiscVPlic::SetContext(int context_no, RiscVPlicIrqInterface *context_if) {
+void RiscVPlic::SetContext(int context_no, RiscVPlicIrqInterface* context_if) {
   context_if_[context_no] = context_if;
 }
 
 // No support for vector stores.
-void RiscVPlic::Store(DataBuffer *address, DataBuffer *mask, int el_size,
-                      DataBuffer *db) {
+void RiscVPlic::Store(DataBuffer* address, DataBuffer* mask, int el_size,
+                      DataBuffer* db) {
   LOG(FATAL) << "RiscVPlic does not support vector stores";
 }
 
@@ -348,7 +348,7 @@
     // If the priority is being changed from 0 to non-zero, see if there is a
     // pending level based interrupt, and if so, set the plic pending bit.
     if (prev == 0 && value != 0) {
-      auto &info = gateway_info_[source];
+      auto& info = gateway_info_[source];
       if (info.ready && info.pending) {
         SetPlicPendingInterrupt(source);
       }
@@ -550,7 +550,7 @@
   // interrupt_claim_complete_ value.
   auto source = interrupt_claim_complete_[context];
   interrupt_claim_complete_[context] = 0;
-  auto &info = gateway_info_[source];
+  auto& info = gateway_info_[source];
   // Check to see if there's a pending level based interrupt w priority > 0.
   if (info.pending && (interrupt_priority_[source] > 0)) {
     // Set the plic pending bit but no need to set the ready bit as this will
@@ -578,7 +578,7 @@
   return (interrupt_pending_[word] & (1 << bit)) != 0;
 }
 
-RiscVPlicSourceInterface::RiscVPlicSourceInterface(RiscVPlic *plic, int source,
+RiscVPlicSourceInterface::RiscVPlicSourceInterface(RiscVPlic* plic, int source,
                                                    bool is_level)
     : plic_(plic), source_(source), is_level_(is_level) {}
 
diff --git a/riscv/riscv_plic.h b/riscv/riscv_plic.h
index 8d8745f..37dc6d9 100644
--- a/riscv/riscv_plic.h
+++ b/riscv/riscv_plic.h
@@ -61,8 +61,8 @@
   // capable of receiving and handling interrupts.
   RiscVPlic(int num_sources, int num_contexts);
   RiscVPlic() = delete;
-  RiscVPlic(const RiscVPlic &) = delete;
-  RiscVPlic &operator=(const RiscVPlic &) = delete;
+  RiscVPlic(const RiscVPlic&) = delete;
+  RiscVPlic& operator=(const RiscVPlic&) = delete;
   ~RiscVPlic() override;
 
   // Configure the PLIC state according to the source and context configuration
@@ -88,19 +88,19 @@
 
   // MemoryInterface overrides.
   // Non-vector load method.
-  void Load(uint64_t address, DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(uint64_t address, DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Vector load method - this is stubbed out.
-  void Load(DataBuffer *address_db, DataBuffer *mask_db, int el_size,
-            DataBuffer *db, Instruction *inst,
-            ReferenceCount *context) override;
+  void Load(DataBuffer* address_db, DataBuffer* mask_db, int el_size,
+            DataBuffer* db, Instruction* inst,
+            ReferenceCount* context) override;
   // Non-vector store method.
-  void Store(uint64_t address, DataBuffer *db) override;
+  void Store(uint64_t address, DataBuffer* db) override;
   // Vector store method - this is stubbed out.
-  void Store(DataBuffer *address, DataBuffer *mask, int el_size,
-             DataBuffer *db) override;
+  void Store(DataBuffer* address, DataBuffer* mask, int el_size,
+             DataBuffer* db) override;
 
-  void SetContext(int context_no, RiscVPlicIrqInterface *context_if);
+  void SetContext(int context_no, RiscVPlicIrqInterface* context_if);
 
  private:
   struct GatewayInfo {
@@ -128,22 +128,22 @@
   int num_sources_;
   int num_contexts_;
   // Interface to call to write the IRQ line for a context.
-  RiscVPlicIrqInterface **context_if_;
+  RiscVPlicIrqInterface** context_if_;
   // Last value written to the IRQ line for a context.
-  bool *context_irq_ = nullptr;
+  bool* context_irq_ = nullptr;
   // Source gateway info.
-  GatewayInfo *gateway_info_ = nullptr;
+  GatewayInfo* gateway_info_ = nullptr;
   // Interrupt priorities by source.
-  uint32_t *interrupt_priority_ = nullptr;
+  uint32_t* interrupt_priority_ = nullptr;
   // Pending interrupts by source - 32 bits per word.
-  uint32_t *interrupt_pending_ = nullptr;
+  uint32_t* interrupt_pending_ = nullptr;
   // Enable bits per context per source - 32 bits per word.
   // Array is organized as interrupt_enabled_[context][source / 32].
-  uint32_t **interrupt_enabled_ = nullptr;
+  uint32_t** interrupt_enabled_ = nullptr;
   // Priority threshold by context.
-  uint32_t *priority_threshold_ = nullptr;
+  uint32_t* priority_threshold_ = nullptr;
   // Interrupt claim/complete register by context.
-  uint32_t *interrupt_claim_complete_ = nullptr;
+  uint32_t* interrupt_claim_complete_ = nullptr;
   // Map from source to context that has the source enabled. This must be
   // updated whenever an an enable bit is changed for a context.
   absl::btree_multimap<int, int> source_to_context_;
@@ -153,7 +153,7 @@
 
 class RiscVPlicSourceInterface : public RiscVPlicIrqInterface {
  public:
-  RiscVPlicSourceInterface(RiscVPlic *plic, int source, bool is_level);
+  RiscVPlicSourceInterface(RiscVPlic* plic, int source, bool is_level);
   RiscVPlicSourceInterface() = delete;
   ~RiscVPlicSourceInterface() override = default;
   void SetIrq(bool irq_value) override {
@@ -161,7 +161,7 @@
   };
 
  private:
-  RiscVPlic *plic_ = nullptr;
+  RiscVPlic* plic_ = nullptr;
   int source_ = 0;
   bool is_level_ = false;
 };
diff --git a/riscv/riscv_priv_instructions.cc b/riscv/riscv_priv_instructions.cc
index fd23133..6508ee5 100644
--- a/riscv/riscv_priv_instructions.cc
+++ b/riscv/riscv_priv_instructions.cc
@@ -38,12 +38,12 @@
 using UIntReg =
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 
-void RiscVPrivURet(const Instruction *inst) {
+void RiscVPrivURet(const Instruction* inst) {
   // TODO Fill in semantics.
 }
 
-void RiscVPrivSRet(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSRet(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   if (state->privilege_mode() != PrivilegeMode::kSupervisor) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
                 *ExceptionCode::kIllegalInstruction, inst->address(), inst);
@@ -60,9 +60,9 @@
                                " sret: cannot access sepc");
     return;
   }
-  auto *sepc = *res;
+  auto* sepc = *res;
   // Get db for PC.
-  auto *db = inst->Destination(0)->AllocateDataBuffer();
+  auto* db = inst->Destination(0)->AllocateDataBuffer();
   // Write the contents of mepc to the pc.
   db->SetSubmit<UIntReg>(0, sepc->AsUint32());
   state->set_branch(true);
@@ -73,7 +73,7 @@
                                " sret: cannot access mstatus");
     return;
   }
-  auto *mstatus = static_cast<RiscVMStatus *>(*res);
+  auto* mstatus = static_cast<RiscVMStatus*>(*res);
   // Get misa too.
   res = state->csr_set()->GetCsr(*RiscVCsrEnum::kMIsa);
   if (!res.ok()) {
@@ -97,8 +97,8 @@
   mstatus->Submit();
 }
 
-void RiscVPrivMRet(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivMRet(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   if (state->privilege_mode() != PrivilegeMode::kMachine) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
                 *ExceptionCode::kIllegalInstruction, inst->address(), inst);
@@ -110,9 +110,9 @@
                                " mret: cannot access mepc");
     return;
   }
-  auto *mepc = *res;
+  auto* mepc = *res;
   // Get db for PC.
-  auto *db = inst->Destination(0)->AllocateDataBuffer();
+  auto* db = inst->Destination(0)->AllocateDataBuffer();
   // Write the contents of mepc to the pc.
   db->SetSubmit<UIntReg>(0, mepc->AsUint32());
   state->set_branch(true);
@@ -123,7 +123,7 @@
                                " mret: cannot access mstatus");
     return;
   }
-  auto *mstatus = static_cast<RiscVMStatus *>(*res);
+  auto* mstatus = static_cast<RiscVMStatus*>(*res);
   // Get misa too.
   res = state->csr_set()->GetCsr(*RiscVCsrEnum::kMIsa);
   if (!res.ok()) {
@@ -131,7 +131,7 @@
                                " mret: cannot access isa");
     return;
   }
-  auto *misa = static_cast<RiscVMIsa *>(*res);
+  auto* misa = static_cast<RiscVMIsa*>(*res);
   // Set mstatus:mpp to new privilege mode as per RiscV Privileged Architectures
   // Arch V20190608-Priv-MSU-Ratified page 21:
   // When executing an xRet instruction, supposing xPP holds the value y, xIE
@@ -160,12 +160,12 @@
 using UIntReg =
     typename std::make_unsigned<typename RegisterType::ValueType>::type;
 
-void RiscVPrivURet(const Instruction *inst) {
+void RiscVPrivURet(const Instruction* inst) {
   // TODO Fill in semantics.
 }
 
-void RiscVPrivSRet(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSRet(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   if (*state->privilege_mode() < *PrivilegeMode::kSupervisor) {
     LOG(ERROR) << absl::StrCat(
         "sret executed when not in Supervisor mode at pc = 0x",
@@ -185,9 +185,9 @@
                                " sret: cannot access sepc");
     return;
   }
-  auto *sepc = *res;
+  auto* sepc = *res;
   // Get db for PC.
-  auto *db = inst->Destination(0)->AllocateDataBuffer();
+  auto* db = inst->Destination(0)->AllocateDataBuffer();
   // Write the contents of mepc to the pc.
   db->SetSubmit<UIntReg>(0, sepc->AsUint64());
   state->set_branch(true);
@@ -198,7 +198,7 @@
                                " sret: cannot access mstatus");
     return;
   }
-  auto *mstatus = static_cast<RiscVMStatus *>(*res);
+  auto* mstatus = static_cast<RiscVMStatus*>(*res);
   // Get misa too.
   res = state->csr_set()->GetCsr(*RiscVCsrEnum::kMIsa);
   if (!res.ok()) {
@@ -223,7 +223,7 @@
                                " mret: cannot access isa");
     return;
   }
-  auto *misa = static_cast<RiscVMIsa *>(*res);
+  auto* misa = static_cast<RiscVMIsa*>(*res);
   if (misa->HasUserMode()) {
     mstatus->set_spp(*PrivilegeMode::kUser);
   } else {
@@ -234,8 +234,8 @@
   mstatus->Submit();
 }
 
-void RiscVPrivMRet(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivMRet(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   if (state->privilege_mode() != PrivilegeMode::kMachine) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
                 *ExceptionCode::kIllegalInstruction, inst->address(), inst);
@@ -247,9 +247,9 @@
                                " mret: cannot access mepc");
     return;
   }
-  auto *mepc = *res;
+  auto* mepc = *res;
   // Get db for PC.
-  auto *db = inst->Destination(0)->AllocateDataBuffer();
+  auto* db = inst->Destination(0)->AllocateDataBuffer();
   // Write the contents of mepc to the pc.
   db->SetSubmit<UIntReg>(0, mepc->AsUint64());
   state->set_branch(true);
@@ -260,7 +260,7 @@
                                " mret: cannot access mstatus");
     return;
   }
-  auto *mstatus = static_cast<RiscVMStatus *>(*res);
+  auto* mstatus = static_cast<RiscVMStatus*>(*res);
   // Get misa too.
   res = state->csr_set()->GetCsr(*RiscVCsrEnum::kMIsa);
   if (!res.ok()) {
@@ -268,7 +268,7 @@
                                " mret: cannot access isa");
     return;
   }
-  auto *misa = static_cast<RiscVMIsa *>(*res);
+  auto* misa = static_cast<RiscVMIsa*>(*res);
   // Set mstatus:mpp to new privilege mode as per RiscV Privileged Architectures
   // Arch V20190608-Priv-MSU-Ratified page 21:
   // When executing an xRet instruction, supposing xPP holds the value y, xIE
@@ -291,16 +291,16 @@
 
 }  // namespace RV64
 
-void RiscVPrivWfi(const Instruction *inst) {
+void RiscVPrivWfi(const Instruction* inst) {
   // WFI is treated as a no-op, unless the user sets a callback.
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   state->WFI(inst);
 }
 
-void RiscVPrivSFenceVmaZZ(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSFenceVmaZZ(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   PrivilegeMode mode = state->privilege_mode();
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   if ((mode == PrivilegeMode::kUser) ||
       ((mode == PrivilegeMode::kSupervisor) && mstatus->tvm())) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
@@ -310,10 +310,10 @@
   // TODO Fill in semantics.
 }
 
-void RiscVPrivSFenceVmaZN(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSFenceVmaZN(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   PrivilegeMode mode = state->privilege_mode();
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   if ((mode == PrivilegeMode::kUser) ||
       ((mode == PrivilegeMode::kSupervisor) && mstatus->tvm())) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
@@ -323,10 +323,10 @@
   // TODO Fill in semantics.
 }
 
-void RiscVPrivSFenceVmaNZ(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSFenceVmaNZ(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   PrivilegeMode mode = state->privilege_mode();
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   if ((mode == PrivilegeMode::kUser) ||
       ((mode == PrivilegeMode::kSupervisor) && mstatus->tvm())) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
@@ -336,10 +336,10 @@
   // TODO Fill in semantics.
 }
 
-void RiscVPrivSFenceVmaNN(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RiscVPrivSFenceVmaNN(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   PrivilegeMode mode = state->privilege_mode();
-  auto *mstatus = state->mstatus();
+  auto* mstatus = state->mstatus();
   if ((mode == PrivilegeMode::kUser) ||
       ((mode == PrivilegeMode::kSupervisor) && mstatus->tvm())) {
     state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
diff --git a/riscv/riscv_priv_instructions.h b/riscv/riscv_priv_instructions.h
index 5b5238e..a93ee7a 100644
--- a/riscv/riscv_priv_instructions.h
+++ b/riscv/riscv_priv_instructions.h
@@ -27,22 +27,22 @@
 using ::mpact::sim::generic::Instruction;
 
 namespace RV32 {
-void RiscVPrivURet(const Instruction *inst);
-void RiscVPrivSRet(const Instruction *inst);
-void RiscVPrivMRet(const Instruction *inst);
+void RiscVPrivURet(const Instruction* inst);
+void RiscVPrivSRet(const Instruction* inst);
+void RiscVPrivMRet(const Instruction* inst);
 }  // namespace RV32
 
 namespace RV64 {
-void RiscVPrivURet(const Instruction *inst);
-void RiscVPrivSRet(const Instruction *inst);
-void RiscVPrivMRet(const Instruction *inst);
+void RiscVPrivURet(const Instruction* inst);
+void RiscVPrivSRet(const Instruction* inst);
+void RiscVPrivMRet(const Instruction* inst);
 }  // namespace RV64
 
-void RiscVPrivWfi(const Instruction *inst);
-void RiscVPrivSFenceVmaZZ(const Instruction *inst);
-void RiscVPrivSFenceVmaZN(const Instruction *inst);
-void RiscVPrivSFenceVmaNZ(const Instruction *inst);
-void RiscVPrivSFenceVmaNN(const Instruction *inst);
+void RiscVPrivWfi(const Instruction* inst);
+void RiscVPrivSFenceVmaZZ(const Instruction* inst);
+void RiscVPrivSFenceVmaZN(const Instruction* inst);
+void RiscVPrivSFenceVmaNZ(const Instruction* inst);
+void RiscVPrivSFenceVmaNN(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_register.cc b/riscv/riscv_register.cc
index 957b341..41ee74a 100644
--- a/riscv/riscv_register.cc
+++ b/riscv/riscv_register.cc
@@ -32,7 +32,7 @@
 using DataBuffer = generic::DataBuffer;
 
 RV32VectorSourceOperand::RV32VectorSourceOperand(
-    absl::Span<generic::RegisterBase *> reg_span, std::string op_name)
+    absl::Span<generic::RegisterBase*> reg_span, std::string op_name)
     : op_name_(op_name) {
   if (reg_span.empty()) return;
   if (reg_span[0] == nullptr) return;
@@ -58,10 +58,10 @@
 }
 
 RV32VectorSourceOperand::RV32VectorSourceOperand(
-    absl::Span<generic::RegisterBase *> reg_span)
+    absl::Span<generic::RegisterBase*> reg_span)
     : RV32VectorSourceOperand(reg_span, reg_span[0]->name()) {}
 
-RV32VectorSourceOperand::RV32VectorSourceOperand(generic::RegisterBase *reg,
+RV32VectorSourceOperand::RV32VectorSourceOperand(generic::RegisterBase* reg,
                                                  std::string op_name)
     : op_name_(op_name) {
   if (reg == nullptr) return;
@@ -72,7 +72,7 @@
   registers_.push_back(reg);
 }
 
-RV32VectorSourceOperand::RV32VectorSourceOperand(generic::RegisterBase *reg)
+RV32VectorSourceOperand::RV32VectorSourceOperand(generic::RegisterBase* reg)
     : RV32VectorSourceOperand(reg, reg->name()) {}
 
 bool RV32VectorSourceOperand::AsBool(int i) {
@@ -130,11 +130,11 @@
   return registers_[group]->data_buffer()->Get<uint64_t>(offset);
 }
 
-RV32VectorTrueOperand::RV32VectorTrueOperand(RiscVState *state)
+RV32VectorTrueOperand::RV32VectorTrueOperand(RiscVState* state)
     : RV32VectorSourceOperand(
           state->GetRegister<RVVectorRegister>(kName).first) {
   // Ensure the value is all ones.
-  auto *reg = state->GetRegister<RVVectorRegister>(kName).first;
+  auto* reg = state->GetRegister<RVVectorRegister>(kName).first;
   auto data = reg->data_buffer()->Get<uint64_t>();
   for (int i = 0; i < data.size(); i++) {
     data[i] = std::numeric_limits<uint64_t>::max();
@@ -142,7 +142,7 @@
 }
 
 RV32VectorDestinationOperand::RV32VectorDestinationOperand(
-    absl::Span<generic::RegisterBase *> reg_span, int latency,
+    absl::Span<generic::RegisterBase*> reg_span, int latency,
     std::string op_name)
     : db_factory_(reg_span[0]->arch_state()->db_factory()),
       delay_line_(reg_span[0]->arch_state()->data_buffer_delay_line()),
@@ -172,11 +172,11 @@
 }
 
 RV32VectorDestinationOperand::RV32VectorDestinationOperand(
-    absl::Span<generic::RegisterBase *> reg_span, int latency)
+    absl::Span<generic::RegisterBase*> reg_span, int latency)
     : RV32VectorDestinationOperand(reg_span, latency, reg_span[0]->name()) {}
 
 RV32VectorDestinationOperand::RV32VectorDestinationOperand(
-    generic::RegisterBase *reg, int latency, std::string op_name)
+    generic::RegisterBase* reg, int latency, std::string op_name)
     : op_name_(op_name) {
   if (reg == nullptr) return;
 
@@ -187,18 +187,18 @@
 }
 
 RV32VectorDestinationOperand::RV32VectorDestinationOperand(
-    generic::RegisterBase *reg, int latency)
+    generic::RegisterBase* reg, int latency)
     : RV32VectorDestinationOperand(reg, latency, reg->name()) {}
 
-DataBuffer *RV32VectorDestinationOperand::AllocateDataBuffer() {
+DataBuffer* RV32VectorDestinationOperand::AllocateDataBuffer() {
   return AllocateDataBuffer(0);
 }
 
-void RV32VectorDestinationOperand::InitializeDataBuffer(DataBuffer *db) {
+void RV32VectorDestinationOperand::InitializeDataBuffer(DataBuffer* db) {
   InitializeDataBuffer(0, db);
 }
 
-DataBuffer *RV32VectorDestinationOperand::CopyDataBuffer() {
+DataBuffer* RV32VectorDestinationOperand::CopyDataBuffer() {
   return CopyDataBuffer(0);
 }
 
@@ -214,20 +214,20 @@
 
 std::string RV32VectorDestinationOperand::AsString() const { return op_name_; }
 
-DataBuffer *RV32VectorDestinationOperand::AllocateDataBuffer(int i) {
-  DataBuffer *db = db_factory_->Allocate(registers_[i]->size());
+DataBuffer* RV32VectorDestinationOperand::AllocateDataBuffer(int i) {
+  DataBuffer* db = db_factory_->Allocate(registers_[i]->size());
   InitializeDataBuffer(i, db);
   return db;
 }
 
-void RV32VectorDestinationOperand::InitializeDataBuffer(int i, DataBuffer *db) {
+void RV32VectorDestinationOperand::InitializeDataBuffer(int i, DataBuffer* db) {
   db->set_destination(registers_[i]);
   db->set_latency(latency_);
   db->set_delay_line(delay_line_);
 }
 
-DataBuffer *RV32VectorDestinationOperand::CopyDataBuffer(int i) {
-  DataBuffer *db = db_factory_->MakeCopyOf(registers_[i]->data_buffer());
+DataBuffer* RV32VectorDestinationOperand::CopyDataBuffer(int i) {
+  DataBuffer* db = db_factory_->MakeCopyOf(registers_[i]->data_buffer());
   InitializeDataBuffer(i, db);
   return db;
 }
diff --git a/riscv/riscv_register.h b/riscv/riscv_register.h
index ad3f5b0..1048b19 100644
--- a/riscv/riscv_register.h
+++ b/riscv/riscv_register.h
@@ -54,12 +54,11 @@
 
 class RV32VectorSourceOperand : public generic::SourceOperandInterface {
  public:
-  RV32VectorSourceOperand(absl::Span<generic::RegisterBase *> reg_span,
+  RV32VectorSourceOperand(absl::Span<generic::RegisterBase*> reg_span,
                           std::string op_name);
-  explicit RV32VectorSourceOperand(
-      absl::Span<generic::RegisterBase *> reg_span);
-  explicit RV32VectorSourceOperand(generic::RegisterBase *reg);
-  RV32VectorSourceOperand(generic::RegisterBase *reg, std::string op_name);
+  explicit RV32VectorSourceOperand(absl::Span<generic::RegisterBase*> reg_span);
+  explicit RV32VectorSourceOperand(generic::RegisterBase* reg);
+  RV32VectorSourceOperand(generic::RegisterBase* reg, std::string op_name);
 
   RV32VectorSourceOperand() = delete;
   bool AsBool(int i) override;
@@ -74,7 +73,7 @@
   // Returns the RegisterBase object wrapped in absl::any.
   std::any GetObject() const override { return std::any(registers_[0]); }
   // Non-inherited method to get the register object.
-  generic::RegisterBase *GetRegister(int i) const { return registers_[i]; }
+  generic::RegisterBase* GetRegister(int i) const { return registers_[i]; }
   // Returns the shape of the register.
   std::vector<int> shape() const override { return registers_[0]->shape(); }
   std::string AsString() const override { return registers_[0]->name(); }
@@ -86,13 +85,13 @@
   int group_size_ = 0;
   int vector_size_ = 0;
   int vector_byte_size_ = 0;
-  std::vector<generic::RegisterBase *> registers_;
+  std::vector<generic::RegisterBase*> registers_;
   std::string op_name_;
 };
 
 class RV32VectorTrueOperand : public RV32VectorSourceOperand {
  public:
-  explicit RV32VectorTrueOperand(RiscVState *state);
+  explicit RV32VectorTrueOperand(RiscVState* state);
 
   RV32VectorTrueOperand() = delete;
   bool AsBool(int) final { return true; }
@@ -113,41 +112,41 @@
 class RV32VectorDestinationOperand
     : public generic::DestinationOperandInterface {
  public:
-  RV32VectorDestinationOperand(absl::Span<generic::RegisterBase *> reg_span,
+  RV32VectorDestinationOperand(absl::Span<generic::RegisterBase*> reg_span,
                                int latency, std::string op_name);
-  RV32VectorDestinationOperand(absl::Span<generic::RegisterBase *> reg_span,
+  RV32VectorDestinationOperand(absl::Span<generic::RegisterBase*> reg_span,
                                int latency);
-  RV32VectorDestinationOperand(generic::RegisterBase *reg, int latency,
+  RV32VectorDestinationOperand(generic::RegisterBase* reg, int latency,
                                std::string op_name);
-  RV32VectorDestinationOperand(generic::RegisterBase *reg, int latency);
-  generic::DataBuffer *AllocateDataBuffer() override;
-  void InitializeDataBuffer(generic::DataBuffer *db) override;
-  generic::DataBuffer *CopyDataBuffer() override;
+  RV32VectorDestinationOperand(generic::RegisterBase* reg, int latency);
+  generic::DataBuffer* AllocateDataBuffer() override;
+  void InitializeDataBuffer(generic::DataBuffer* db) override;
+  generic::DataBuffer* CopyDataBuffer() override;
   int latency() const override;
   std::any GetObject() const override;
   std::vector<int> shape() const override;
   std::string AsString() const override;
   // New method.
-  generic::DataBuffer *AllocateDataBuffer(int i);
-  void InitializeDataBuffer(int i, generic::DataBuffer *db);
-  generic::DataBuffer *CopyDataBuffer(int i);
+  generic::DataBuffer* AllocateDataBuffer(int i);
+  void InitializeDataBuffer(int i, generic::DataBuffer* db);
+  generic::DataBuffer* CopyDataBuffer(int i);
   std::any GetObject(int i) const;
   int size() const { return registers_.size(); }
 
  private:
-  generic::DataBufferFactory *db_factory_;
-  generic::DataBufferDelayLine *delay_line_;
+  generic::DataBufferFactory* db_factory_;
+  generic::DataBufferDelayLine* delay_line_;
   int latency_ = 0;
   int group_size_ = 0;
   int vector_size_ = 0;
   int vector_byte_size_ = 0;
-  std::vector<generic::RegisterBase *> registers_;
+  std::vector<generic::RegisterBase*> registers_;
   std::string op_name_;
 };
 
 using RVVectorRegister =
-    generic::StateItem<generic::RegisterBase, uint8_t *,
-                       RV32VectorSourceOperand, RV32VectorDestinationOperand>;
+    generic::StateItem<generic::RegisterBase, uint8_t*, RV32VectorSourceOperand,
+                       RV32VectorDestinationOperand>;
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_renode.cc b/riscv/riscv_renode.cc
index 148845a..df72f6e 100644
--- a/riscv/riscv_renode.cc
+++ b/riscv/riscv_renode.cc
@@ -89,19 +89,19 @@
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
-RiscVRenode::RiscVRenode(std::string name, MemoryInterface *renode_sysbus,
+RiscVRenode::RiscVRenode(std::string name, MemoryInterface* renode_sysbus,
                          RiscVXlen xlen)
     : name_(name), renode_sysbus_(renode_sysbus) {
   router_ = new util::SingleInitiatorRouter(name + "_router");
   renode_router_ = new util::SingleInitiatorRouter(name + "_renode_router");
-  auto *data_memory = static_cast<MemoryInterface *>(router_);
+  auto* data_memory = static_cast<MemoryInterface*>(router_);
   // Instantiate memory profiler, but disable it until the config information
   // has been received.
   mem_profiler_ = new MemoryUseProfiler(data_memory);
   mem_profiler_->set_is_enabled(false);
   // Set up state, decoder, and top.
   rv_state_ = new RiscVState("RiscVRenode", xlen, mem_profiler_,
-                             static_cast<AtomicMemoryOpInterface *>(router_));
+                             static_cast<AtomicMemoryOpInterface*>(router_));
   rv_fp_state_ = new RiscVFPState(rv_state_->csr_set(), rv_state_);
   rv_state_->set_rv_fp(rv_fp_state_);
   std::string reg_name;
@@ -154,7 +154,7 @@
                                        : RiscVArmSemihost::BitWidth::kWord64,
                                    data_memory, data_memory);
   // Set up special handlers (ebreak, wfi, ecall).
-  riscv_top_->state()->AddEbreakHandler([this](const Instruction *inst) {
+  riscv_top_->state()->AddEbreakHandler([this](const Instruction* inst) {
     if (this->semihost_->IsSemihostingCall(inst)) {
       this->semihost_->OnEBreak(inst);
       return true;
@@ -165,8 +165,8 @@
     }
     return false;
   });
-  riscv_top_->state()->set_on_wfi([](const Instruction *) { return true; });
-  riscv_top_->state()->set_on_ecall([](const Instruction *) { return false; });
+  riscv_top_->state()->set_on_wfi([](const Instruction*) { return true; });
+  riscv_top_->state()->set_on_ecall([](const Instruction*) { return false; });
   semihost_->set_exit_callback([this]() {
     LOG(INFO) << "Simulation halting due to semihosting exit";
     this->riscv_top_->RequestHalt(HaltReason::kProgramDone, nullptr);
@@ -211,8 +211,8 @@
   std::string serialized;
   if (!proto_file.good()) {
     LOG(ERROR) << "Failed to open proto file for writing";
-  } else if (!google::protobuf::TextFormat::PrintToString(
-                 *component_proto.get(), &serialized)) {
+  } else if (!google::protobuf::TextFormat::PrintToString(*component_proto,
+                                                          &serialized)) {
     LOG(ERROR) << "Failed to serialize protos";
   } else {
     proto_file << serialized;
@@ -239,7 +239,7 @@
   delete clint_;
 }
 
-absl::StatusOr<uint64_t> RiscVRenode::LoadExecutable(const char *elf_file_name,
+absl::StatusOr<uint64_t> RiscVRenode::LoadExecutable(const char* elf_file_name,
                                                      bool for_symbols_only) {
   program_loader_ = new ElfProgramLoader(this);
   uint64_t entry_pt = 0;
@@ -264,12 +264,12 @@
     uint64_t tohost_addr = res.value().first;
     // Add to_host watchpoint that halts the execution when program exit is
     // signaled.
-    auto *db = riscv_top_->state()->db_factory()->Allocate<uint32_t>(2);
+    auto* db = riscv_top_->state()->db_factory()->Allocate<uint32_t>(2);
     auto status = riscv_top_->memory_watcher()->SetStoreWatchCallback(
         MemoryWatcher::AddressRange{tohost_addr,
                                     tohost_addr + 2 * sizeof(uint32_t) - 1},
         [this, tohost_addr, db](uint64_t addr, int sz) {
-          static DataBuffer *load_db = db;
+          static DataBuffer* load_db = db;
           if (load_db == nullptr) return;
           memory_->Load(tohost_addr, load_db, nullptr, nullptr);
           uint32_t code = load_db->Get<uint32_t>(0);
@@ -317,9 +317,9 @@
 
 // Perform direct read of the memory through the renode router. The renode
 // router avoids routing the request back out to the sysbus.
-absl::StatusOr<size_t> RiscVRenode::ReadMemory(uint64_t address, void *buf,
+absl::StatusOr<size_t> RiscVRenode::ReadMemory(uint64_t address, void* buf,
                                                size_t length) {
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   renode_router_->Load(address, db, nullptr, nullptr);
   std::memcpy(buf, db->raw_ptr(), length);
   db->DecRef();
@@ -329,9 +329,9 @@
 // Perform direct write of the memory through the renode router. The renode
 // router avoids routing the request back out to the sysbus.
 absl::StatusOr<size_t> RiscVRenode::WriteMemory(uint64_t address,
-                                                const void *buf,
+                                                const void* buf,
                                                 size_t length) {
-  auto *db = db_factory_.Allocate<uint8_t>(length);
+  auto* db = db_factory_.Allocate<uint8_t>(length);
   std::memcpy(db->raw_ptr(), buf, length);
   renode_router_->Store(address, db);
   db->DecRef();
@@ -365,15 +365,15 @@
 }
 
 absl::Status RiscVRenode::GetRenodeRegisterInfo(int32_t index, int32_t max_len,
-                                                char *name,
-                                                RenodeCpuRegister &info) {
-  auto const &register_info = RiscVRenodeRegisterInfo::GetRenodeRegisterInfo();
+                                                char* name,
+                                                RenodeCpuRegister& info) {
+  auto const& register_info = RiscVRenodeRegisterInfo::GetRenodeRegisterInfo();
   if ((index < 0) || (index >= register_info.size())) {
     return absl::OutOfRangeError(
         absl::StrCat("Register info index (", index, ") out of range"));
   }
   info = register_info[index];
-  auto const &reg_map = RiscVDebugInfo::Instance()->debug_register_map();
+  auto const& reg_map = RiscVDebugInfo::Instance()->debug_register_map();
   auto ptr = reg_map.find(info.index);
   if (ptr == reg_map.end()) {
     name[0] = '\0';
@@ -383,7 +383,7 @@
   return absl::OkStatus();
 }
 
-static absl::StatusOr<uint64_t> ParseNumber(const std::string &number) {
+static absl::StatusOr<uint64_t> ParseNumber(const std::string& number) {
   if (number.empty()) {
     return absl::InvalidArgumentError("Empty number");
   }
@@ -402,8 +402,8 @@
   return res.value();
 }
 
-absl::Status RiscVRenode::SetConfig(const char *config_names[],
-                                    const char *config_values[], int size) {
+absl::Status RiscVRenode::SetConfig(const char* config_names[],
+                                    const char* config_values[], int size) {
   std::string icache_cfg;
   std::string dcache_cfg;
   uint64_t memory_base = 0;
@@ -494,7 +494,7 @@
     instrumentation_control_ =
         new RiscVInstrumentationControl(cmd_shell_, riscv_top_, mem_profiler_);
     cmd_shell_->AddCore(
-        {static_cast<RiscVDebugInterface *>(riscv_cli_forwarder_),
+        {static_cast<RiscVDebugInterface*>(riscv_cli_forwarder_),
          [this]() { return program_loader_; }});
     cmd_shell_->AddCommand(
         instrumentation_control_->Usage(),
@@ -552,7 +552,7 @@
     ComponentValueEntry icache_value;
     icache_value.set_name("icache");
     icache_value.set_string_value(icache_cfg);
-    auto *cfg = riscv_top_->GetConfig("icache");
+    auto* cfg = riscv_top_->GetConfig("icache");
     auto status = cfg->Import(&icache_value);
     if (!status.ok()) return status;
   }
@@ -560,11 +560,11 @@
     ComponentValueEntry dcache_value;
     dcache_value.set_name("dcache");
     dcache_value.set_string_value(dcache_cfg);
-    auto *cfg = riscv_top_->GetConfig("dcache");
+    auto* cfg = riscv_top_->GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return status;
     // Hook the cache into the memory port.
-    auto *dcache = riscv_top_->dcache();
+    auto* dcache = riscv_top_->dcache();
     dcache->set_memory(riscv_top_->state()->memory());
     riscv_top_->state()->set_memory(dcache);
   }
diff --git a/riscv/riscv_renode.h b/riscv/riscv_renode.h
index 2f1fc73..4f02f57 100644
--- a/riscv/riscv_renode.h
+++ b/riscv/riscv_renode.h
@@ -97,10 +97,10 @@
 
   // Constructor takes a name and a memory interface that is used for memory
   // transactions routed to the system bus.
-  RiscVRenode(std::string name, MemoryInterface *renode_sysbus, RiscVXlen xlen);
+  RiscVRenode(std::string name, MemoryInterface* renode_sysbus, RiscVXlen xlen);
   ~RiscVRenode() override;
 
-  absl::StatusOr<uint64_t> LoadExecutable(const char *elf_file_name,
+  absl::StatusOr<uint64_t> LoadExecutable(const char* elf_file_name,
                                           bool for_symbols_only) override;
   // Step the core by num instructions.
   absl::StatusOr<int> Step(int num) override;
@@ -111,18 +111,18 @@
   absl::Status WriteRegister(uint32_t reg_id, uint64_t value) override;
   // Get register data buffer call. Not implemented, stubbed out to return null.
   // Read/write the buffers to memory.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
   // Return register information.
   int32_t GetRenodeRegisterInfoSize() const override;
-  absl::Status GetRenodeRegisterInfo(int32_t index, int32_t max_len, char *name,
-                                     RenodeCpuRegister &info) override;
+  absl::Status GetRenodeRegisterInfo(int32_t index, int32_t max_len, char* name,
+                                     RenodeCpuRegister& info) override;
 
   // Set configuration value.
-  absl::Status SetConfig(const char *config_names[],
-                         const char *config_values[], int size) override;
+  absl::Status SetConfig(const char* config_names[],
+                         const char* config_values[], int size) override;
 
   // Set IRQ value for supported IRQs. Supported irq_nums are:
   //          MachineSoftwareInterrupt = 0x3
@@ -133,26 +133,26 @@
 
  private:
   std::string name_;
-  MemoryInterface *renode_sysbus_ = nullptr;
-  RiscVState *rv_state_ = nullptr;
-  RiscVFPState *rv_fp_state_ = nullptr;
-  generic::DecoderInterface *rv_decoder_ = nullptr;
-  RiscVTop *riscv_top_ = nullptr;
-  RiscVArmSemihost *semihost_ = nullptr;
-  SingleInitiatorRouter *router_ = nullptr;
-  SingleInitiatorRouter *renode_router_ = nullptr;
+  MemoryInterface* renode_sysbus_ = nullptr;
+  RiscVState* rv_state_ = nullptr;
+  RiscVFPState* rv_fp_state_ = nullptr;
+  generic::DecoderInterface* rv_decoder_ = nullptr;
+  RiscVTop* riscv_top_ = nullptr;
+  RiscVArmSemihost* semihost_ = nullptr;
+  SingleInitiatorRouter* router_ = nullptr;
+  SingleInitiatorRouter* renode_router_ = nullptr;
   DataBufferFactory db_factory_;
-  AtomicMemory *atomic_memory_ = nullptr;
-  FlatDemandMemory *memory_ = nullptr;
-  RiscVClint *clint_ = nullptr;
-  SocketCLI *socket_cli_ = nullptr;
-  RiscVRenodeCLITop *riscv_renode_cli_top_ = nullptr;
-  RiscVCLIForwarder *riscv_cli_forwarder_ = nullptr;
-  ElfProgramLoader *program_loader_ = nullptr;
-  DebugCommandShell *cmd_shell_ = nullptr;
-  InstructionProfiler *inst_profiler_ = nullptr;
-  MemoryUseProfiler *mem_profiler_ = nullptr;
-  RiscVInstrumentationControl *instrumentation_control_ = nullptr;
+  AtomicMemory* atomic_memory_ = nullptr;
+  FlatDemandMemory* memory_ = nullptr;
+  RiscVClint* clint_ = nullptr;
+  SocketCLI* socket_cli_ = nullptr;
+  RiscVRenodeCLITop* riscv_renode_cli_top_ = nullptr;
+  RiscVCLIForwarder* riscv_cli_forwarder_ = nullptr;
+  ElfProgramLoader* program_loader_ = nullptr;
+  DebugCommandShell* cmd_shell_ = nullptr;
+  InstructionProfiler* inst_profiler_ = nullptr;
+  MemoryUseProfiler* mem_profiler_ = nullptr;
+  RiscVInstrumentationControl* instrumentation_control_ = nullptr;
   uint64_t stack_size_ = 32 * 1024;
   uint64_t stack_end_ = 0;
 };
diff --git a/riscv/riscv_renode_cli_top.cc b/riscv/riscv_renode_cli_top.cc
index 3015750..5d9fc4b 100644
--- a/riscv/riscv_renode_cli_top.cc
+++ b/riscv/riscv_renode_cli_top.cc
@@ -31,7 +31,7 @@
 namespace sim {
 namespace riscv {
 
-RiscVRenodeCLITop::RiscVRenodeCLITop(RiscVTop *riscv_top, bool wait_for_cli)
+RiscVRenodeCLITop::RiscVRenodeCLITop(RiscVTop* riscv_top, bool wait_for_cli)
     : util::renode::RenodeCLITop(riscv_top, wait_for_cli),
       riscv_top_(riscv_top) {}
 
diff --git a/riscv/riscv_renode_cli_top.h b/riscv/riscv_renode_cli_top.h
index 4f0fc93..4e42724 100644
--- a/riscv/riscv_renode_cli_top.h
+++ b/riscv/riscv_renode_cli_top.h
@@ -35,7 +35,7 @@
 // CherIoT CLI.
 class RiscVRenodeCLITop : public util::renode::RenodeCLITop {
  public:
-  RiscVRenodeCLITop(RiscVTop *riscv_top, bool wait_for_cli);
+  RiscVRenodeCLITop(RiscVTop* riscv_top, bool wait_for_cli);
 
   absl::Status CLISetDataWatchpoint(uint64_t address, size_t length,
                                     AccessType access_type);
@@ -48,7 +48,7 @@
   absl::Status CLIDisableAction(uint64_t address, int id);
 
  private:
-  RiscVTop *riscv_top_ = nullptr;
+  RiscVTop* riscv_top_ = nullptr;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv_renode_register_info.cc b/riscv/riscv_renode_register_info.cc
index 49316f1..c4b9a9f 100644
--- a/riscv/riscv_renode_register_info.cc
+++ b/riscv/riscv_renode_register_info.cc
@@ -23,7 +23,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT - used below.
 
-RiscVRenodeRegisterInfo *RiscVRenodeRegisterInfo::instance_ = nullptr;
+RiscVRenodeRegisterInfo* RiscVRenodeRegisterInfo::instance_ = nullptr;
 
 void RiscVRenodeRegisterInfo::InitializeRenodeRegisterInfo() {
   using DbgReg = DebugRegisterEnum;
@@ -69,19 +69,19 @@
   InitializeRenodeRegisterInfo();
 }
 
-const RiscVRenodeRegisterInfo::RenodeRegisterInfo &
+const RiscVRenodeRegisterInfo::RenodeRegisterInfo&
 RiscVRenodeRegisterInfo::GetRenodeRegisterInfo() {
   return Instance()->GetRenodeRegisterInfoPrivate();
 }
 
-RiscVRenodeRegisterInfo *RiscVRenodeRegisterInfo::Instance() {
+RiscVRenodeRegisterInfo* RiscVRenodeRegisterInfo::Instance() {
   if (instance_ == nullptr) {
     instance_ = new RiscVRenodeRegisterInfo();
   }
   return instance_;
 }
 
-const RiscVRenodeRegisterInfo::RenodeRegisterInfo &
+const RiscVRenodeRegisterInfo::RenodeRegisterInfo&
 RiscVRenodeRegisterInfo::GetRenodeRegisterInfoPrivate() {
   return renode_register_info_;
 }
diff --git a/riscv/riscv_renode_register_info.h b/riscv/riscv_renode_register_info.h
index ab554d8..6e50532 100644
--- a/riscv/riscv_renode_register_info.h
+++ b/riscv/riscv_renode_register_info.h
@@ -32,15 +32,15 @@
  public:
   using RenodeRegisterInfo = std::vector<util::renode::RenodeCpuRegister>;
 
-  static const RenodeRegisterInfo &GetRenodeRegisterInfo();
+  static const RenodeRegisterInfo& GetRenodeRegisterInfo();
 
  private:
   RiscVRenodeRegisterInfo();
-  static RiscVRenodeRegisterInfo *Instance();
+  static RiscVRenodeRegisterInfo* Instance();
   void InitializeRenodeRegisterInfo();
-  const RenodeRegisterInfo &GetRenodeRegisterInfoPrivate();
+  const RenodeRegisterInfo& GetRenodeRegisterInfoPrivate();
 
-  static RiscVRenodeRegisterInfo *instance_;
+  static RiscVRenodeRegisterInfo* instance_;
   RenodeRegisterInfo renode_register_info_;
 };
 
diff --git a/riscv/riscv_sim_csrs.h b/riscv/riscv_sim_csrs.h
index 015ae66..9371500 100644
--- a/riscv/riscv_sim_csrs.h
+++ b/riscv/riscv_sim_csrs.h
@@ -27,7 +27,7 @@
 
 class RiscVSimModeCsr : public RiscVSimpleCsr<uint32_t> {
  public:
-  RiscVSimModeCsr(std::string name, RiscVCsrEnum index, RiscVState *state)
+  RiscVSimModeCsr(std::string name, RiscVCsrEnum index, RiscVState* state)
       : RiscVSimpleCsr<uint32_t>(name, index, 0x0, 0x3, 0x3, state),
         state_(state) {}
 
@@ -37,7 +37,7 @@
   void Set(uint64_t value) override;
 
  private:
-  RiscVState *state_;
+  RiscVState* state_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv_state.cc b/riscv/riscv_state.cc
index 8d71bad..0553d46 100644
--- a/riscv/riscv_state.cc
+++ b/riscv/riscv_state.cc
@@ -104,9 +104,9 @@
 // This creates the CSR and assigns it to a pointer in the state object. Type
 // can be inferred from the state object pointer.
 template <typename T, typename... Ps>
-T *CreateCsr(RiscVState *state, T *&ptr,
-             std::vector<RiscVCsrInterface *> &csr_vec, Ps... pargs) {
-  auto *csr = new T(pargs...);
+T* CreateCsr(RiscVState* state, T*& ptr,
+             std::vector<RiscVCsrInterface*>& csr_vec, Ps... pargs) {
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -123,9 +123,9 @@
 // that pointer is of abstract type, so the CSR type cannot be inferred, but
 // has to be specified in the call.
 template <typename T, typename... Ps>
-T *CreateCsr(RiscVState *state, RiscVCsrInterface *&ptr,
-             std::vector<RiscVCsrInterface *> &csr_vec, Ps... pargs) {
-  auto *csr = new T(pargs...);
+T* CreateCsr(RiscVState* state, RiscVCsrInterface*& ptr,
+             std::vector<RiscVCsrInterface*>& csr_vec, Ps... pargs) {
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -142,9 +142,9 @@
 // object. That means the type cannot be inferred, but has to be specified
 // in the call.
 template <typename T, typename... Ps>
-T *CreateCsr(RiscVState *state, std::vector<RiscVCsrInterface *> &csr_vec,
+T* CreateCsr(RiscVState* state, std::vector<RiscVCsrInterface*>& csr_vec,
              Ps... pargs) {
-  auto *csr = new T(pargs...);
+  auto* csr = new T(pargs...);
   auto result = state->csr_set()->AddCsr(csr);
   if (!result.ok()) {
     LOG(ERROR) << absl::StrCat("Failed to add csr '", csr->name(),
@@ -159,7 +159,7 @@
 // Templated helper function that is used to create the set of CSRs needed
 // for simulation.
 template <typename T>
-void CreateCsrs(RiscVState *state, std::vector<RiscVCsrInterface *> &csr_vec) {
+void CreateCsrs(RiscVState* state, std::vector<RiscVCsrInterface*>& csr_vec) {
   absl::Status result;
   // Create CSRs.
 
@@ -169,7 +169,7 @@
            nullptr);
 
   // misa
-  auto *misa = CreateCsr(state, state->misa_, csr_vec,
+  auto* misa = CreateCsr(state, state->misa_, csr_vec,
                          CsrInfo<T>::kMisaInitialValue, state);
   CHECK_NE(misa, nullptr);
   // mtvec
@@ -184,11 +184,11 @@
 
   // Mip and Mie are always 32 bit.
   // mip
-  auto *mip = CreateCsr(state, state->mip_, csr_vec, 0, state);
+  auto* mip = CreateCsr(state, state->mip_, csr_vec, 0, state);
   CHECK_NE(mip, nullptr);
 
   // mie
-  auto *mie = CreateCsr(state, state->mie_, csr_vec, 0, state);
+  auto* mie = CreateCsr(state, state->mie_, csr_vec, 0, state);
   CHECK_NE(mie, nullptr);
 
   // mhartid
@@ -215,13 +215,13 @@
            nullptr);
 
   // mideleg - machine mode interrupt delegation register.
-  auto *mideleg = CreateCsr<RiscVSimpleCsr<T>>(
+  auto* mideleg = CreateCsr<RiscVSimpleCsr<T>>(
       state, state->mideleg_, csr_vec, "mideleg", RiscVCsrEnum::kMIDeleg, 0,
       CsrInfo<T>::kMIdelegRMask, CsrInfo<T>::kMIdelegWMask, state);
   CHECK_NE(mideleg, nullptr);
 
   // mstatus
-  auto *mstatus =
+  auto* mstatus =
       CreateCsr(state, state->mstatus_, csr_vec,
                 CsrInfo<uint64_t>::kMstatusInitialValue, state, misa);
   CHECK_NE(mstatus, nullptr);
@@ -231,25 +231,25 @@
            nullptr);
 
   // minstret/minstreth
-  auto *minstret = CreateCsr<RiscVCounterCsr<T, RiscVState>>(
+  auto* minstret = CreateCsr<RiscVCounterCsr<T, RiscVState>>(
       state, csr_vec, "minstret", RiscVCsrEnum ::kMInstret, state);
   CHECK_NE(minstret, nullptr);
   if (sizeof(T) == sizeof(uint32_t)) {
-    CHECK_NE(CreateCsr<RiscVCounterCsrHigh<RiscVState>>(
-                 state, csr_vec, "minstreth", RiscVCsrEnum::kMInstretH, state,
-                 reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState> *>(
-                     minstret)),
-             nullptr);
+    CHECK_NE(
+        CreateCsr<RiscVCounterCsrHigh<RiscVState>>(
+            state, csr_vec, "minstreth", RiscVCsrEnum::kMInstretH, state,
+            reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState>*>(minstret)),
+        nullptr);
   }
   // mcycle/mcycleh
-  auto *mcycle = CreateCsr<RiscVCounterCsr<T, RiscVState>>(
+  auto* mcycle = CreateCsr<RiscVCounterCsr<T, RiscVState>>(
       state, csr_vec, "mcycle", RiscVCsrEnum::kMCycle, state);
   CHECK_NE(mcycle, nullptr);
   if (sizeof(T) == sizeof(uint32_t)) {
     CHECK_NE(
         CreateCsr<RiscVCounterCsrHigh<RiscVState>>(
             state, csr_vec, "mcycleh", RiscVCsrEnum::kMCycleH, state,
-            reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState> *>(mcycle)),
+            reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState>*>(mcycle)),
         nullptr);
   }
 
@@ -329,7 +329,7 @@
   state->pmp_->CreatePmpCsrs<T, RiscVCsrEnum>(state->csr_set());
 
   // Jump base vector and control register (for Zcmt instructions).
-  auto *jvt_csr = CreateCsr<RiscVJvtCsr<T>>(state, state->jvt_, csr_vec, "jvt",
+  auto* jvt_csr = CreateCsr<RiscVJvtCsr<T>>(state, state->jvt_, csr_vec, "jvt",
                                             RiscVCsrEnum::kJvt, 0, state);
   CHECK_NE(jvt_csr, nullptr);
   state->jvt_ = jvt_csr;
@@ -348,8 +348,8 @@
 constexpr uint64_t kRiscv64MaxMemorySize = 0x00ff'ffff'ffff'ffffULL;
 
 RiscVState::RiscVState(absl::string_view id, RiscVXlen xlen,
-                       util::MemoryInterface *memory,
-                       util::AtomicMemoryOpInterface *atomic_memory)
+                       util::MemoryInterface* memory,
+                       util::AtomicMemoryOpInterface* atomic_memory)
     : ArchState(id),
       xlen_(xlen),
       memory_(memory),
@@ -359,10 +359,10 @@
       counter_interrupt_returns_("interrupt_returns", 0) {
   CHECK_OK(AddCounter(&counter_interrupt_returns_));
   CHECK_OK(AddCounter(&counter_interrupts_taken_));
-  DataBuffer *db = nullptr;
+  DataBuffer* db = nullptr;
   switch (xlen_) {
     case RiscVXlen::RV32: {
-      auto *pc32 = GetRegister<RV32Register>(kPcName).first;
+      auto* pc32 = GetRegister<RV32Register>(kPcName).first;
       pc_src_operand_ = pc32->CreateSourceOperand();
       pc_dst_operand_ = pc32->CreateDestinationOperand(0);
       pc_ = pc32;
@@ -373,7 +373,7 @@
       break;
     }
     case RiscVXlen::RV64: {
-      auto *pc64 = GetRegister<RV64Register>(kPcName).first;
+      auto* pc64 = GetRegister<RV64Register>(kPcName).first;
       pc_src_operand_ = pc64->CreateSourceOperand();
       pc_dst_operand_ = pc64->CreateDestinationOperand(0);
       pc_ = pc64;
@@ -399,7 +399,7 @@
     LOG(ERROR) << "Failed to get misa register";
     return;
   }
-  auto *misa = result.value();
+  auto* misa = result.value();
   auto misa_value = misa->AsUint32();
   if (misa_value & *IsaExtension::kSinglePrecisionFp) {
     flen_ = 32;
@@ -417,7 +417,7 @@
   delete pc_dst_operand_;
   delete csr_set_;
   delete pmp_;
-  for (auto *csr : csr_vec_) {
+  for (auto* csr : csr_vec_) {
     delete csr;
   }
   csr_vec_.clear();
@@ -438,9 +438,9 @@
   }
 }
 
-void RiscVState::LoadMemory(const Instruction *inst, uint64_t address,
-                            DataBuffer *db, Instruction *child_inst,
-                            ReferenceCount *context) {
+void RiscVState::LoadMemory(const Instruction* inst, uint64_t address,
+                            DataBuffer* db, Instruction* child_inst,
+                            ReferenceCount* context) {
   if (address > max_physical_address_) {
     Trap(/*is_interrupt*/ false, address, *ExceptionCode::kLoadAccessFault,
          inst->address(), inst);
@@ -449,9 +449,9 @@
   memory_->Load(address, db, child_inst, context);
 }
 
-void RiscVState::LoadMemory(const Instruction *inst, DataBuffer *address_db,
-                            DataBuffer *mask_db, int el_size, DataBuffer *db,
-                            Instruction *child_inst, ReferenceCount *context) {
+void RiscVState::LoadMemory(const Instruction* inst, DataBuffer* address_db,
+                            DataBuffer* mask_db, int el_size, DataBuffer* db,
+                            Instruction* child_inst, ReferenceCount* context) {
   for (auto address : address_db->Get<uint64_t>()) {
     if (address > max_physical_address_) {
       Trap(/*is_interrupt*/ false, address, *ExceptionCode::kLoadAccessFault,
@@ -462,8 +462,8 @@
   memory_->Load(address_db, mask_db, el_size, db, child_inst, context);
 }
 
-void RiscVState::StoreMemory(const Instruction *inst, uint64_t address,
-                             DataBuffer *db) {
+void RiscVState::StoreMemory(const Instruction* inst, uint64_t address,
+                             DataBuffer* db) {
   if (address > max_physical_address_) {
     Trap(/*is_interrupt*/ false, address, *ExceptionCode::kStoreAccessFault,
          inst->address(), inst);
@@ -472,8 +472,8 @@
   memory_->Store(address, db);
 }
 
-void RiscVState::StoreMemory(const Instruction *inst, DataBuffer *address_db,
-                             DataBuffer *mask_db, int el_size, DataBuffer *db) {
+void RiscVState::StoreMemory(const Instruction* inst, DataBuffer* address_db,
+                             DataBuffer* mask_db, int el_size, DataBuffer* db) {
   for (auto address : address_db->Get<uint64_t>()) {
     if (address > max_physical_address_) {
       Trap(/*is_interrupt*/ false, address, *ExceptionCode::kStoreAccessFault,
@@ -484,16 +484,16 @@
   memory_->Store(address_db, mask_db, el_size, db);
 }
 
-void RiscVState::Fence(const Instruction *inst, int fm, int predecessor,
+void RiscVState::Fence(const Instruction* inst, int fm, int predecessor,
                        int successor) {
   // TODO: Add fence operation once operations have non-zero latency.
 }
 
-void RiscVState::FenceI(const Instruction *inst) {
+void RiscVState::FenceI(const Instruction* inst) {
   // TODO: Add instruction fence operation when needed.
 }
 
-void RiscVState::ECall(const Instruction *inst) {
+void RiscVState::ECall(const Instruction* inst) {
   if (on_ecall_ != nullptr) {
     auto res = on_ecall_(inst);
     if (res) return;
@@ -523,8 +523,8 @@
   Trap(/*is_interrupt*/ false, 0, *code, epc, inst);
 }
 
-void RiscVState::EBreak(const Instruction *inst) {
-  for (auto &handler : on_ebreak_) {
+void RiscVState::EBreak(const Instruction* inst) {
+  for (auto& handler : on_ebreak_) {
     bool res = handler(inst);
     if (res) return;
   }
@@ -534,7 +534,7 @@
   Trap(/*is_interrupt=*/false, 0, 3, epc, inst);
 }
 
-void RiscVState::WFI(const Instruction *inst) {
+void RiscVState::WFI(const Instruction* inst) {
   if (on_wfi_ != nullptr) {
     bool res = on_wfi_(inst);
     if (res) return;
@@ -547,7 +547,7 @@
   LOG(INFO) << "No handler for wfi: treating as nop: " << where;
 }
 
-void RiscVState::Cease(const Instruction *inst) {
+void RiscVState::Cease(const Instruction* inst) {
   if (on_cease_ != nullptr) {
     const bool res = on_cease_(inst);
     if (res) return;
@@ -555,7 +555,7 @@
 
   // If no handler is specified, then CEASE is treated as an infinite loop.
   auto current_xlen = xlen();
-  auto *db = pc_dst_operand_->AllocateDataBuffer();
+  auto* db = pc_dst_operand_->AllocateDataBuffer();
   if (current_xlen == RiscVXlen::RV32) {
     db->SetSubmit<uint32_t>(0, static_cast<uint32_t>(inst->address()));
     set_branch(true);
@@ -575,7 +575,7 @@
 
 void RiscVState::Trap(bool is_interrupt, uint64_t trap_value,
                       uint64_t exception_code, uint64_t epc,
-                      const Instruction *inst) {
+                      const Instruction* inst) {
   if (on_trap_ != nullptr) {
     bool res = on_trap_(is_interrupt, trap_value, exception_code, epc, inst);
     if (res) return;
@@ -615,9 +615,9 @@
 
   // Based on the destination privilege mode, select the CSRs that will be
   // used.
-  RiscVCsrInterface *epc_csr = nullptr;
-  RiscVCsrInterface *cause_csr = nullptr;
-  RiscVCsrInterface *tvec_csr = nullptr;
+  RiscVCsrInterface* epc_csr = nullptr;
+  RiscVCsrInterface* cause_csr = nullptr;
+  RiscVCsrInterface* tvec_csr = nullptr;
   if (destination_mode == PrivilegeMode::kMachine) {
     epc_csr = mepc_;
     cause_csr = mcause_;
@@ -677,7 +677,7 @@
   }
 
   // Update the PC.
-  auto *db = pc_dst_operand_->AllocateDataBuffer();
+  auto* db = pc_dst_operand_->AllocateDataBuffer();
   if (current_xlen == RiscVXlen::RV32) {
     db->SetSubmit<uint32_t>(0, static_cast<uint32_t>(trap_target));
     set_branch(true);
diff --git a/riscv/riscv_state.h b/riscv/riscv_state.h
index a09c8d6..63c5aaa 100644
--- a/riscv/riscv_state.h
+++ b/riscv/riscv_state.h
@@ -120,7 +120,7 @@
 
 // A simple load context class for convenience.
 struct LoadContext : public generic::ReferenceCount {
-  explicit LoadContext(DataBuffer *vdb) : value_db(vdb) {}
+  explicit LoadContext(DataBuffer* vdb) : value_db(vdb) {}
   ~LoadContext() override {
     if (value_db != nullptr) value_db->DecRef();
   }
@@ -134,12 +134,12 @@
     generic::ReferenceCount::OnRefCountIsZero();
   }
   // Data buffers for the value loaded from memory (byte, half, word, etc.).
-  DataBuffer *value_db = nullptr;
+  DataBuffer* value_db = nullptr;
 };
 
 // Vector load context class.
 struct VectorLoadContext : public generic::ReferenceCount {
-  VectorLoadContext(DataBuffer *vdb, DataBuffer *mdb, int element_width_,
+  VectorLoadContext(DataBuffer* vdb, DataBuffer* mdb, int element_width_,
                     int vstart_, int vlength_)
       : value_db(vdb),
         mask_db(mdb),
@@ -161,9 +161,9 @@
     generic::ReferenceCount::OnRefCountIsZero();
   }
   // DataBuffer instances for the value loaded from memory.
-  DataBuffer *value_db = nullptr;
+  DataBuffer* value_db = nullptr;
   // Mask data buffer.
-  DataBuffer *mask_db = nullptr;
+  DataBuffer* mask_db = nullptr;
   // Vector element width.
   int element_width;
   // Starting element index.
@@ -181,7 +181,7 @@
 
 // Forward declare a template function defined in the .cc file.
 template <typename T>
-void CreateCsrs(RiscVState *, std::vector<RiscVCsrInterface *> &);
+void CreateCsrs(RiscVState*, std::vector<RiscVCsrInterface*>&);
 
 class RiscVFPState;
 class RiscVPmp;
@@ -191,10 +191,10 @@
 // calls and software breakpoints.
 class RiscVState : public ArchState {
  public:
-  friend void CreateCsrs<uint32_t>(RiscVState *,
-                                   std::vector<RiscVCsrInterface *> &);
-  friend void CreateCsrs<uint64_t>(RiscVState *,
-                                   std::vector<RiscVCsrInterface *> &);
+  friend void CreateCsrs<uint32_t>(RiscVState*,
+                                   std::vector<RiscVCsrInterface*>&);
+  friend void CreateCsrs<uint64_t>(RiscVState*,
+                                   std::vector<RiscVCsrInterface*>&);
 
   static constexpr char kFregPrefix[] = "f";
   static constexpr char kXregPrefix[] = "x";
@@ -204,28 +204,28 @@
   static constexpr char kPcName[] = "pc";
 
   RiscVState(absl::string_view id, RiscVXlen xlen,
-             util::MemoryInterface *memory,
-             util::AtomicMemoryOpInterface *atomic_memory);
+             util::MemoryInterface* memory,
+             util::AtomicMemoryOpInterface* atomic_memory);
   RiscVState(absl::string_view id, RiscVXlen xlen,
-             util::MemoryInterface *memory)
+             util::MemoryInterface* memory)
       : RiscVState(id, xlen, memory, nullptr) {}
   ~RiscVState() override;
 
   // Deleted Constructors and operators.
-  RiscVState(const RiscVState &) = delete;
-  RiscVState(RiscVState &&) = delete;
-  RiscVState &operator=(const RiscVState &) = delete;
-  RiscVState &operator=(RiscVState &&) = delete;
+  RiscVState(const RiscVState&) = delete;
+  RiscVState(RiscVState&&) = delete;
+  RiscVState& operator=(const RiscVState&) = delete;
+  RiscVState& operator=(RiscVState&&) = delete;
 
   // Return a pair consisting of pointer to the named register and a bool that
   // is true if the register had to be created, and false if it was found
   // in the register map (or if nullptr is returned).
   template <typename RegisterType>
-  std::pair<RegisterType *, bool> GetRegister(absl::string_view name) {
+  std::pair<RegisterType*, bool> GetRegister(absl::string_view name) {
     // If the register already exists, return a pointer to the register.
     auto ptr = registers()->find(std::string(name));
     if (ptr != registers()->end())
-      return std::make_pair(static_cast<RegisterType *>(ptr->second), false);
+      return std::make_pair(static_cast<RegisterType*>(ptr->second), false);
     // Create a new register and return a pointer to the object.
     return std::make_pair(AddRegister<RegisterType>(name), true);
   }
@@ -244,35 +244,35 @@
   }
 
   // Methods called by instruction semantic functions to load from memory.
-  void LoadMemory(const Instruction *inst, uint64_t address, DataBuffer *db,
-                  Instruction *child_inst, ReferenceCount *context);
-  void LoadMemory(const Instruction *inst, DataBuffer *address_db,
-                  DataBuffer *mask_db, int el_size, DataBuffer *db,
-                  Instruction *child_inst, ReferenceCount *context);
+  void LoadMemory(const Instruction* inst, uint64_t address, DataBuffer* db,
+                  Instruction* child_inst, ReferenceCount* context);
+  void LoadMemory(const Instruction* inst, DataBuffer* address_db,
+                  DataBuffer* mask_db, int el_size, DataBuffer* db,
+                  Instruction* child_inst, ReferenceCount* context);
   // Methods called by instruction semantic functions to store to memory.
-  void StoreMemory(const Instruction *inst, uint64_t address, DataBuffer *db);
-  void StoreMemory(const Instruction *inst, DataBuffer *address_db,
-                   DataBuffer *mask_db, int el_size, DataBuffer *db);
+  void StoreMemory(const Instruction* inst, uint64_t address, DataBuffer* db);
+  void StoreMemory(const Instruction* inst, DataBuffer* address_db,
+                   DataBuffer* mask_db, int el_size, DataBuffer* db);
   // Called by the fence instruction semantic function to signal a fence
   // operation.
-  void Fence(const Instruction *inst, int fm, int predecessor, int successor);
+  void Fence(const Instruction* inst, int fm, int predecessor, int successor);
   // Synchronize instruction and data streams.
-  void FenceI(const Instruction *inst);
+  void FenceI(const Instruction* inst);
   // System call.
-  void ECall(const Instruction *inst);
+  void ECall(const Instruction* inst);
   // Breakpoint.
-  void EBreak(const Instruction *inst);
+  void EBreak(const Instruction* inst);
   // WFI
-  void WFI(const Instruction *inst);
+  void WFI(const Instruction* inst);
   // Ceases execution on the core. This is a non-standard instruction that
   // quiesces traffic for embedded cores before halting. The core must be reset
   // to come out of this state.
-  void Cease(const Instruction *inst);
+  void Cease(const Instruction* inst);
   // Trap.
   void Trap(bool is_interrupt, uint64_t trap_value, uint64_t exception_code,
-            uint64_t epc, const Instruction *inst);
+            uint64_t epc, const Instruction* inst);
   // Add ebreak handler.
-  void AddEbreakHandler(absl::AnyInvocable<bool(const Instruction *)> handler) {
+  void AddEbreakHandler(absl::AnyInvocable<bool(const Instruction*)> handler) {
     on_ebreak_.emplace_back(std::move(handler));
   }
   // This function is called after any event that may have caused an interrupt
@@ -296,12 +296,12 @@
   }
 
   // Accessors.
-  void set_memory(util::MemoryInterface *memory) { memory_ = memory; }
-  util::MemoryInterface *memory() const { return memory_; }
-  util::AtomicMemoryOpInterface *atomic_memory() const {
+  void set_memory(util::MemoryInterface* memory) { memory_ = memory; }
+  util::MemoryInterface* memory() const { return memory_; }
+  util::AtomicMemoryOpInterface* atomic_memory() const {
     return atomic_memory_;
   }
-  void set_atomic_memory(util::AtomicMemoryOpInterface *atomic_memory) {
+  void set_atomic_memory(util::AtomicMemoryOpInterface* atomic_memory) {
     atomic_memory_ = atomic_memory;
   }
 
@@ -311,36 +311,36 @@
   // Setters for handlers for ecall, and trap. The handler returns true
   // if the instruction/event was handled, and false otherwise.
 
-  void set_on_ecall(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_ecall(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_ecall_ = std::move(callback);
   }
 
-  void set_on_wfi(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_wfi(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_wfi_ = std::move(callback);
   }
 
-  void set_on_cease(absl::AnyInvocable<bool(const Instruction *)> callback) {
+  void set_on_cease(absl::AnyInvocable<bool(const Instruction*)> callback) {
     on_cease_ = std::move(callback);
   }
 
   void set_on_trap(
       absl::AnyInvocable<bool(bool /*is_interrupt*/, uint64_t /*trap_value*/,
                               uint64_t /*exception_code*/, uint64_t /*epc*/,
-                              const Instruction *)>
+                              const Instruction*)>
           callback) {
     on_trap_ = std::move(callback);
   }
 
   int flen() const { return flen_; }
   RiscVXlen xlen() const { return xlen_; }
-  RiscVVectorState *rv_vector() const { return rv_vector_; }
-  void set_rv_vector(RiscVVectorState *value) { rv_vector_ = value; }
-  RiscVFPState *rv_fp() const { return rv_fp_; }
-  void set_rv_fp(RiscVFPState *value) { rv_fp_ = value; }
+  RiscVVectorState* rv_vector() const { return rv_vector_; }
+  void set_rv_vector(RiscVVectorState* value) { rv_vector_ = value; }
+  RiscVFPState* rv_fp() const { return rv_fp_; }
+  void set_rv_fp(RiscVFPState* value) { rv_fp_ = value; }
   void set_vector_register_width(int value) { vector_register_width_ = value; }
   int vector_register_width() const { return vector_register_width_; }
 
-  RiscVCsrSet *csr_set() const { return csr_set_; }
+  RiscVCsrSet* csr_set() const { return csr_set_; }
 
   PrivilegeMode privilege_mode() const { return privilege_mode_; }
   void set_privilege_mode(PrivilegeMode privilege_mode) {
@@ -361,49 +361,49 @@
   bool branch() const { return branch_; }
 
   // Getters for select CSRs.
-  RiscVMStatus *mstatus() const { return mstatus_; }
-  RiscVMIsa *misa() const { return misa_; }
-  RiscVMIp *mip() const { return mip_; }
-  RiscVMIe *mie() const { return mie_; }
-  RiscVCsrInterface *jvt() const { return jvt_; }
-  RiscVCsrInterface *mtvec() const { return mtvec_; }
-  RiscVCsrInterface *mepc() const { return mepc_; }
-  RiscVCsrInterface *mcause() const { return mcause_; }
-  RiscVCsrInterface *medeleg() const { return medeleg_; }
-  RiscVCsrInterface *mideleg() const { return mideleg_; }
-  RiscVSIp *sip() const { return sip_; }
-  RiscVSIe *sie() const { return sie_; }
-  RiscVCsrInterface *stvec() const { return stvec_; }
-  RiscVCsrInterface *sepc() const { return sepc_; }
-  RiscVCsrInterface *scause() const { return scause_; }
-  RiscVCsrInterface *sideleg() const { return sideleg_; }
+  RiscVMStatus* mstatus() const { return mstatus_; }
+  RiscVMIsa* misa() const { return misa_; }
+  RiscVMIp* mip() const { return mip_; }
+  RiscVMIe* mie() const { return mie_; }
+  RiscVCsrInterface* jvt() const { return jvt_; }
+  RiscVCsrInterface* mtvec() const { return mtvec_; }
+  RiscVCsrInterface* mepc() const { return mepc_; }
+  RiscVCsrInterface* mcause() const { return mcause_; }
+  RiscVCsrInterface* medeleg() const { return medeleg_; }
+  RiscVCsrInterface* mideleg() const { return mideleg_; }
+  RiscVSIp* sip() const { return sip_; }
+  RiscVSIe* sie() const { return sie_; }
+  RiscVCsrInterface* stvec() const { return stvec_; }
+  RiscVCsrInterface* sepc() const { return sepc_; }
+  RiscVCsrInterface* scause() const { return scause_; }
+  RiscVCsrInterface* sideleg() const { return sideleg_; }
 
  private:
   InterruptCode PickInterrupt(uint32_t interrupts);
   RiscVXlen xlen_;
   uint64_t max_physical_address_;
-  RiscVVectorState *rv_vector_ = nullptr;
-  RiscVFPState *rv_fp_ = nullptr;
+  RiscVVectorState* rv_vector_ = nullptr;
+  RiscVFPState* rv_fp_ = nullptr;
   // Program counter register.
-  generic::RegisterBase *pc_;
+  generic::RegisterBase* pc_;
   // Operands used to access pc values generically. Note, the pc value may read
   // as the address of the next instruction during execution of an instruction,
   // so the address of the instruction executing should be used instead.
-  generic::SourceOperandInterface *pc_src_operand_ = nullptr;
-  generic::DestinationOperandInterface *pc_dst_operand_ = nullptr;
+  generic::SourceOperandInterface* pc_src_operand_ = nullptr;
+  generic::DestinationOperandInterface* pc_dst_operand_ = nullptr;
   int vector_register_width_ = 0;
   int flen_ = 0;
-  util::MemoryInterface *memory_ = nullptr;
-  util::AtomicMemoryOpInterface *atomic_memory_ = nullptr;
-  RiscVCsrSet *csr_set_ = nullptr;
-  std::vector<absl::AnyInvocable<bool(const Instruction *)>> on_ebreak_;
-  absl::AnyInvocable<bool(const Instruction *)> on_ecall_;
+  util::MemoryInterface* memory_ = nullptr;
+  util::AtomicMemoryOpInterface* atomic_memory_ = nullptr;
+  RiscVCsrSet* csr_set_ = nullptr;
+  std::vector<absl::AnyInvocable<bool(const Instruction*)>> on_ebreak_;
+  absl::AnyInvocable<bool(const Instruction*)> on_ecall_;
   absl::AnyInvocable<bool(bool, uint64_t, uint64_t, uint64_t,
-                          const Instruction *)>
+                          const Instruction*)>
       on_trap_;
-  absl::AnyInvocable<bool(const Instruction *)> on_wfi_;
-  absl::AnyInvocable<bool(const Instruction *)> on_cease_;
-  std::vector<RiscVCsrInterface *> csr_vec_;
+  absl::AnyInvocable<bool(const Instruction*)> on_wfi_;
+  absl::AnyInvocable<bool(const Instruction*)> on_cease_;
+  std::vector<RiscVCsrInterface*> csr_vec_;
   // For interrupt handling.
   bool is_interrupt_available_ = false;
   InterruptCode available_interrupt_code_ = InterruptCode::kNone;
@@ -412,36 +412,36 @@
   // Flag set on branch instructions.
   bool branch_ = false;
   // Handles to frequently used CSRs.
-  RiscVMStatus *mstatus_ = nullptr;
-  RiscVMIsa *misa_ = nullptr;
-  RiscVMIp *mip_ = nullptr;
-  RiscVMIe *mie_ = nullptr;
-  RiscVPmp *pmp_ = nullptr;
-  RiscVCsrInterface *jvt_ = nullptr;
-  RiscVCsrInterface *mtvec_ = nullptr;
-  RiscVCsrInterface *mepc_ = nullptr;
-  RiscVCsrInterface *mcause_ = nullptr;
-  RiscVCsrInterface *medeleg_ = nullptr;
-  RiscVCsrInterface *mideleg_ = nullptr;
-  RiscVSIp *sip_ = nullptr;
-  RiscVSIe *sie_ = nullptr;
-  RiscVCsrInterface *stvec_ = nullptr;
-  RiscVCsrInterface *sepc_ = nullptr;
-  RiscVCsrInterface *scause_ = nullptr;
-  RiscVCsrInterface *sideleg_ = nullptr;
+  RiscVMStatus* mstatus_ = nullptr;
+  RiscVMIsa* misa_ = nullptr;
+  RiscVMIp* mip_ = nullptr;
+  RiscVMIe* mie_ = nullptr;
+  RiscVPmp* pmp_ = nullptr;
+  RiscVCsrInterface* jvt_ = nullptr;
+  RiscVCsrInterface* mtvec_ = nullptr;
+  RiscVCsrInterface* mepc_ = nullptr;
+  RiscVCsrInterface* mcause_ = nullptr;
+  RiscVCsrInterface* medeleg_ = nullptr;
+  RiscVCsrInterface* mideleg_ = nullptr;
+  RiscVSIp* sip_ = nullptr;
+  RiscVSIe* sie_ = nullptr;
+  RiscVCsrInterface* stvec_ = nullptr;
+  RiscVCsrInterface* sepc_ = nullptr;
+  RiscVCsrInterface* scause_ = nullptr;
+  RiscVCsrInterface* sideleg_ = nullptr;
   generic::SimpleCounter<int64_t> counter_interrupts_taken_;
   generic::SimpleCounter<int64_t> counter_interrupt_returns_;
 };
 
 // Specialization for RiscV vector registers.
 template <>
-inline std::pair<RVVectorRegister *, bool>
+inline std::pair<RVVectorRegister*, bool>
 RiscVState::GetRegister<RVVectorRegister>(absl::string_view name) {
   int vector_byte_width = vector_register_width();
   if (vector_byte_width == 0) return std::make_pair(nullptr, false);
   auto ptr = registers()->find(std::string(name));
   if (ptr != registers()->end())
-    return std::make_pair(static_cast<RVVectorRegister *>(ptr->second), false);
+    return std::make_pair(static_cast<RVVectorRegister*>(ptr->second), false);
   // Create a new register and return a pointer to the object.
   return std::make_pair(AddRegister<RVVectorRegister>(name, vector_byte_width),
                         true);
diff --git a/riscv/riscv_test_mem_watcher.cc b/riscv/riscv_test_mem_watcher.cc
index ff1c4bf..0a21504 100644
--- a/riscv/riscv_test_mem_watcher.cc
+++ b/riscv/riscv_test_mem_watcher.cc
@@ -14,7 +14,12 @@
 
 #include "riscv/riscv_test_mem_watcher.h"
 
+#include <cstdint>
+
 #include "absl/strings/str_cat.h"
+#include "mpact/sim/generic/data_buffer.h"
+#include "mpact/sim/generic/instruction.h"
+#include "mpact/sim/generic/ref_count.h"
 
 namespace mpact {
 namespace sim {
@@ -24,26 +29,26 @@
 // support for vector loads/stores will be added later as necessary, when full
 // support for RiscV vector instructions 1.0 is added to the RiscV torture test.
 
-void RiscVTestMemWatcher::Load(uint64_t address, generic::DataBuffer *db,
-                               generic::Instruction *inst,
-                               generic::ReferenceCount *context) {
+void RiscVTestMemWatcher::Load(uint64_t address, generic::DataBuffer* db,
+                               generic::Instruction* inst,
+                               generic::ReferenceCount* context) {
   absl::StrAppend(&trace_str_, " mem 0x", absl::Hex(address, absl::kZeroPad16));
   memory_->Load(address, db, inst, context);
 }
 
-void RiscVTestMemWatcher::Load(generic::DataBuffer *address_db,
-                               generic::DataBuffer *mask_db, int el_size,
-                               generic::DataBuffer *db,
-                               generic::Instruction *inst,
-                               generic::ReferenceCount *context) {
-  for (auto const &address : address_db->Get<uint64_t>()) {
+void RiscVTestMemWatcher::Load(generic::DataBuffer* address_db,
+                               generic::DataBuffer* mask_db, int el_size,
+                               generic::DataBuffer* db,
+                               generic::Instruction* inst,
+                               generic::ReferenceCount* context) {
+  for (auto const& address : address_db->Get<uint64_t>()) {
     absl::StrAppend(&trace_str_, " mem 0x",
                     absl::Hex(address, absl::kZeroPad16));
   }
   memory_->Load(address_db, mask_db, el_size, db, inst, context);
 }
 
-void RiscVTestMemWatcher::Store(uint64_t address, generic::DataBuffer *db) {
+void RiscVTestMemWatcher::Store(uint64_t address, generic::DataBuffer* db) {
   absl::StrAppend(&trace_str_, " mem 0x", absl::Hex(address, absl::kZeroPad16));
   switch (db->size<uint8_t>()) {
     case 1:
@@ -68,10 +73,10 @@
   memory_->Store(address, db);
 }
 
-void RiscVTestMemWatcher::Store(generic::DataBuffer *address_db,
-                                generic::DataBuffer *mask_db, int el_size,
-                                generic::DataBuffer *db) {
-  for (auto const &address : address_db->Get<uint64_t>()) {
+void RiscVTestMemWatcher::Store(generic::DataBuffer* address_db,
+                                generic::DataBuffer* mask_db, int el_size,
+                                generic::DataBuffer* db) {
+  for (auto const& address : address_db->Get<uint64_t>()) {
     absl::StrAppend(&trace_str_, " mem 0x",
                     absl::Hex(address, absl::kZeroPad16));
     switch (el_size) {
diff --git a/riscv/riscv_test_mem_watcher.h b/riscv/riscv_test_mem_watcher.h
index 5d73dc1..e106ef3 100644
--- a/riscv/riscv_test_mem_watcher.h
+++ b/riscv/riscv_test_mem_watcher.h
@@ -15,8 +15,12 @@
 #ifndef MPACT_RISCV_RISCV_RISCV_TEST_MEM_WATCHER_H_
 #define MPACT_RISCV_RISCV_RISCV_TEST_MEM_WATCHER_H_
 
+#include <cstdint>
 #include <string>
 
+#include "mpact/sim/generic/data_buffer.h"
+#include "mpact/sim/generic/instruction.h"
+#include "mpact/sim/generic/ref_count.h"
 #include "mpact/sim/util/memory/memory_interface.h"
 
 namespace mpact {
@@ -34,24 +38,24 @@
 
 class RiscVTestMemWatcher : public util::MemoryInterface {
  public:
-  explicit RiscVTestMemWatcher(util::MemoryInterface *memory)
+  explicit RiscVTestMemWatcher(util::MemoryInterface* memory)
       : memory_(memory) {}
 
-  void Load(uint64_t address, generic::DataBuffer *db,
-            generic::Instruction *inst,
-            generic::ReferenceCount *context) override;
-  void Load(generic::DataBuffer *address_db, generic::DataBuffer *mask_db,
-            int el_size, generic::DataBuffer *db, generic::Instruction *inst,
-            generic::ReferenceCount *context) override;
-  void Store(uint64_t address, generic::DataBuffer *db) override;
-  void Store(generic::DataBuffer *address_db, generic::DataBuffer *mask_db,
-             int el_size, generic::DataBuffer *db) override;
+  void Load(uint64_t address, generic::DataBuffer* db,
+            generic::Instruction* inst,
+            generic::ReferenceCount* context) override;
+  void Load(generic::DataBuffer* address_db, generic::DataBuffer* mask_db,
+            int el_size, generic::DataBuffer* db, generic::Instruction* inst,
+            generic::ReferenceCount* context) override;
+  void Store(uint64_t address, generic::DataBuffer* db) override;
+  void Store(generic::DataBuffer* address_db, generic::DataBuffer* mask_db,
+             int el_size, generic::DataBuffer* db) override;
 
-  const std::string &trace_str() const { return trace_str_; }
+  const std::string& trace_str() const { return trace_str_; }
   void clear_trace_str() { trace_str_.clear(); }
 
  private:
-  util::MemoryInterface *memory_;
+  util::MemoryInterface* memory_;
   std::string trace_str_;
 };
 
diff --git a/riscv/riscv_top.cc b/riscv/riscv_top.cc
index 83ffb8e..1f96b13 100644
--- a/riscv/riscv_top.cc
+++ b/riscv/riscv_top.cc
@@ -60,7 +60,7 @@
 using ::mpact::sim::generic::BreakpointManager;
 
 // Local helper function used to execute instructions.
-static inline bool ExecuteInstruction(Instruction *inst) {
+static inline bool ExecuteInstruction(Instruction* inst) {
   // The following code can be used to model stalls due to latency of operand
   // writes that are used by subsequent instructions. Instruction latencies
   // are defined in the .isa file.
@@ -81,8 +81,8 @@
   return true;
 }
 
-RiscVTop::RiscVTop(std::string name, RiscVState *state,
-                   generic::DecoderInterface *decoder)
+RiscVTop::RiscVTop(std::string name, RiscVState* state,
+                   generic::DecoderInterface* decoder)
     : Component(name),
       state_(state),
       rv_decoder_(decoder),
@@ -149,32 +149,32 @@
   CHECK_OK(csr_res.status()) << "Failed to get minstret CSR";
   if (state_->xlen() == RiscVXlen::RV32) {
     // Minstret/minstreth.
-    auto *minstret = reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState> *>(
+    auto* minstret = reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState>*>(
         csr_res.value());
     minstret->set_counter(&counter_num_instructions_);
     csr_res = state_->csr_set()->GetCsr("minstreth");
     CHECK_OK(csr_res.status()) << "Failed to get minstret CSR";
-    auto *minstreth =
-        reinterpret_cast<RiscVCounterCsrHigh<RiscVState> *>(csr_res.value());
+    auto* minstreth =
+        reinterpret_cast<RiscVCounterCsrHigh<RiscVState>*>(csr_res.value());
     minstreth->set_counter(&counter_num_instructions_);
     // Mcycle/mcycleh.
     csr_res = state_->csr_set()->GetCsr("mcycle");
     CHECK_OK(csr_res.status()) << "Failed to get mcycle CSR";
-    auto *mcycle = reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState> *>(
+    auto* mcycle = reinterpret_cast<RiscVCounterCsr<uint32_t, RiscVState>*>(
         csr_res.value());
     mcycle->set_counter(&counter_num_cycles_);
     csr_res = state_->csr_set()->GetCsr("mcycleh");
     CHECK_OK(csr_res.status()) << "Failed to get mcycleh CSR";
-    auto *mcycleh =
-        reinterpret_cast<RiscVCounterCsrHigh<RiscVState> *>(csr_res.value());
+    auto* mcycleh =
+        reinterpret_cast<RiscVCounterCsrHigh<RiscVState>*>(csr_res.value());
     mcycleh->set_counter(&counter_num_cycles_);
   } else {
     // Minstret/minstreth.
-    auto *minstret = reinterpret_cast<RiscVCounterCsr<uint64_t, RiscVState> *>(
+    auto* minstret = reinterpret_cast<RiscVCounterCsr<uint64_t, RiscVState>*>(
         csr_res.value());
     minstret->set_counter(&counter_num_instructions_);
     // Mcycle/mcycleh.
-    auto *mcycle = reinterpret_cast<RiscVCounterCsr<uint64_t, RiscVState> *>(
+    auto* mcycle = reinterpret_cast<RiscVCounterCsr<uint64_t, RiscVState>*>(
         csr_res.value());
     mcycle->set_counter(&counter_num_cycles_);
   }
@@ -190,7 +190,7 @@
       [this]() { RequestHalt(HaltReason::kSoftwareBreakpoint, nullptr); });
 
   // Set the ebreak handler callback.
-  state_->AddEbreakHandler([this](const Instruction *inst) {
+  state_->AddEbreakHandler([this](const Instruction* inst) {
     if (rv_action_point_manager_->IsActionPointActive(inst->address())) {
       // Need to request a halt so that the action point can be stepped past
       // after executing the actions. However, an action may override the
@@ -205,13 +205,13 @@
   // Branch trace.
   branch_trace_db_ = db_factory_.Allocate<BranchTraceEntry>(kBranchTraceSize);
   branch_trace_ =
-      reinterpret_cast<BranchTraceEntry *>(branch_trace_db_->raw_ptr());
+      reinterpret_cast<BranchTraceEntry*>(branch_trace_db_->raw_ptr());
   for (int i = 0; i < kBranchTraceSize; i++) {
     branch_trace_[i] = {0, 0, 0};
   }
 }
 
-void RiscVTop::ConfigureCache(Cache *&cache, Config<std::string> &config) {
+void RiscVTop::ConfigureCache(Cache*& cache, Config<std::string>& config) {
   if (cache != nullptr) {
     LOG(WARNING) << "Cache already configured - ignored";
     return;
@@ -322,7 +322,7 @@
   pc = next_pc;
   while (!halted_ && (count < num)) {
     SetPc(pc);
-    auto *inst = rv_decode_cache_->GetDecodedInstruction(pc);
+    auto* inst = rv_decode_cache_->GetDecodedInstruction(pc);
     // Set the next_pc to the next sequential instruction.
     next_pc = pc + inst->size();
     bool executed = false;
@@ -416,7 +416,7 @@
     // the most recently executed instruction.
     uint64_t pc = next_pc;
     while (!halted_) {
-      auto *inst = rv_decode_cache_->GetDecodedInstruction(pc);
+      auto* inst = rv_decode_cache_->GetDecodedInstruction(pc);
       SetPc(pc);
       next_pc = pc + inst->size();
       bool executed = false;
@@ -506,7 +506,7 @@
   return halt_reason_;
 }
 
-absl::StatusOr<uint64_t> RiscVTop::ReadRegister(const std::string &name) {
+absl::StatusOr<uint64_t> RiscVTop::ReadRegister(const std::string& name) {
   auto iter = state_->registers()->find(name);
 
   // Was the register found? If not try CSRs.
@@ -519,7 +519,7 @@
       return absl::NotFoundError(
           absl::StrCat("Register '", name, "' not found"));
     }
-    auto *csr = *result;
+    auto* csr = *result;
     auto xlen = state_->xlen();
     switch (xlen) {
       case RiscVXlen::RV32:
@@ -531,7 +531,7 @@
     }
   }
 
-  auto *db = (iter->second)->data_buffer();
+  auto* db = (iter->second)->data_buffer();
   uint64_t value;
   switch (db->size<uint8_t>()) {
     case 1:
@@ -552,7 +552,7 @@
   return value;
 }
 
-absl::Status RiscVTop::WriteRegister(const std::string &name, uint64_t value) {
+absl::Status RiscVTop::WriteRegister(const std::string& name, uint64_t value) {
   // The registers aren't protected by a mutex, so let's not write them while
   // the simulator is running.
   if (run_status_ != RunStatus::kHalted) {
@@ -569,7 +569,7 @@
       return absl::NotFoundError(
           absl::StrCat("Register '", name, "' not found"));
     }
-    auto *csr = *result;
+    auto* csr = *result;
     auto xlen = state_->xlen();
     switch (xlen) {
       case RiscVXlen::RV32:
@@ -589,7 +589,7 @@
     halt_reason_ = *HaltReason::kNone;
   }
 
-  auto *db = (iter->second)->data_buffer();
+  auto* db = (iter->second)->data_buffer();
   switch (db->size<uint8_t>()) {
     case 1:
       db->Set<uint8_t>(0, static_cast<uint8_t>(value));
@@ -609,8 +609,8 @@
   return absl::OkStatus();
 }
 
-absl::StatusOr<DataBuffer *> RiscVTop::GetRegisterDataBuffer(
-    const std::string &name) {
+absl::StatusOr<DataBuffer*> RiscVTop::GetRegisterDataBuffer(
+    const std::string& name) {
   // The registers aren't protected by a mutex, so let's not access them while
   // the simulator is running.
   if (run_status_ != RunStatus::kHalted) {
@@ -625,7 +625,7 @@
   return iter->second->data_buffer();
 }
 
-absl::StatusOr<size_t> RiscVTop::ReadMemory(uint64_t address, void *buffer,
+absl::StatusOr<size_t> RiscVTop::ReadMemory(uint64_t address, void* buffer,
                                             size_t length) {
   if (run_status_ != RunStatus::kHalted) {
     return absl::FailedPreconditionError("ReadMemory: Core must be halted");
@@ -635,7 +635,7 @@
   }
   uint64_t length64 = static_cast<uint64_t>(length);
   length = std::min(length64, state_->max_physical_address() - address + 1);
-  auto *db = db_factory_.Allocate(length);
+  auto* db = db_factory_.Allocate(length);
   // Load bypassing any watch points/semihosting.
   state_->memory()->Load(address, db, nullptr, nullptr);
   std::memcpy(buffer, db->raw_ptr(), length);
@@ -644,7 +644,7 @@
 }
 
 absl::StatusOr<size_t> RiscVTop::WriteMemory(uint64_t address,
-                                             const void *buffer,
+                                             const void* buffer,
                                              size_t length) {
   if (run_status_ != RunStatus::kHalted) {
     return absl::FailedPreconditionError("WriteMemory: Core must be halted");
@@ -654,7 +654,7 @@
   }
   uint64_t length64 = static_cast<uint64_t>(length);
   length = std::min(length64, state_->max_physical_address() - address + 1);
-  auto *db = db_factory_.Allocate(length);
+  auto* db = db_factory_.Allocate(length);
   std::memcpy(db->raw_ptr(), buffer, length);
   // Store bypassing any watch points/semihosting.
   state_->memory()->Store(address, db);
@@ -784,7 +784,7 @@
   return absl::OkStatus();
 }
 
-absl::StatusOr<Instruction *> RiscVTop::GetInstruction(uint64_t address) {
+absl::StatusOr<Instruction*> RiscVTop::GetInstruction(uint64_t address) {
   // If requesting the instruction at an action point, we need to write the
   // original instruction back to memory before getting the disassembly.
   bool inst_swap = rv_action_point_manager_->IsActionPointActive(address);
@@ -793,7 +793,7 @@
         ->WriteOriginalInstruction(address);
   }
   // Get the decoded instruction.
-  Instruction *inst = rv_decode_cache_->GetDecodedInstruction(address);
+  Instruction* inst = rv_decode_cache_->GetDecodedInstruction(address);
   inst->IncRef();
   // Swap back if required.
   if (inst_swap) {
@@ -811,14 +811,14 @@
 
   auto res = GetInstruction(address);
   if (!res.ok()) return res.status();
-  Instruction *inst = res.value();
+  Instruction* inst = res.value();
   auto disasm = inst != nullptr ? inst->AsString() : "Invalid instruction";
   inst->DecRef();
   return disasm;
 }
 
 void RiscVTop::RequestHalt(HaltReasonValueType halt_reason,
-                           const Instruction *inst) {
+                           const Instruction* inst) {
   // First set the halt_reason_, then the halt flag.
   halt_reason_ = halt_reason;
   halted_ = true;
@@ -830,7 +830,7 @@
   }
 }
 
-void RiscVTop::RequestHalt(HaltReason halt_reason, const Instruction *inst) {
+void RiscVTop::RequestHalt(HaltReason halt_reason, const Instruction* inst) {
   RequestHalt(*halt_reason, inst);
 }
 
@@ -846,8 +846,8 @@
   if (absl::popcount(size) != 1) {
     return absl::InvalidArgumentError("Invalid size - must be a power of 2");
   }
-  auto *new_db = db_factory_.Allocate<BranchTraceEntry>(size);
-  auto *new_trace = reinterpret_cast<BranchTraceEntry *>(new_db->raw_ptr());
+  auto* new_db = db_factory_.Allocate<BranchTraceEntry>(size);
+  auto* new_trace = reinterpret_cast<BranchTraceEntry*>(new_db->raw_ptr());
   if (new_db == nullptr) {
     return absl::InternalError("Failed to allocate new branch trace buffer");
   }
@@ -882,7 +882,7 @@
 
 void RiscVTop::AddToBranchTrace(uint64_t from, uint64_t to) {
   // Get the most recent entry.
-  auto &entry = branch_trace_[branch_trace_head_];
+  auto& entry = branch_trace_[branch_trace_head_];
   // If the branch is the same as the previous, just increment its count.
   if ((from == entry.from) && (to == entry.to)) {
     entry.count++;
@@ -894,14 +894,14 @@
 }
 
 void RiscVTop::EnableStatistics() {
-  for (auto &[unused, counter_ptr] : counter_map()) {
+  for (auto& [unused, counter_ptr] : counter_map()) {
     if (counter_ptr->GetName() == "pc") continue;
     counter_ptr->SetIsEnabled(true);
   }
 }
 
 void RiscVTop::DisableStatistics() {
-  for (auto &[unused, counter_ptr] : counter_map()) {
+  for (auto& [unused, counter_ptr] : counter_map()) {
     if (counter_ptr->GetName() == "pc") continue;
     counter_ptr->SetIsEnabled(false);
   }
diff --git a/riscv/riscv_top.h b/riscv/riscv_top.h
index 7786ff2..e51ad42 100644
--- a/riscv/riscv_top.h
+++ b/riscv/riscv_top.h
@@ -69,11 +69,11 @@
   using RunStatus = generic::CoreDebugInterface::RunStatus;
   using HaltReason = generic::CoreDebugInterface::HaltReason;
 
-  RiscVTop(std::string name, RiscVState *state,
-           generic::DecoderInterface *decoder);
+  RiscVTop(std::string name, RiscVState* state,
+           generic::DecoderInterface* decoder);
   RiscVTop() = delete;
-  RiscVTop(const RiscVTop &) = delete;
-  RiscVTop &operator=(const RiscVTop &) = delete;
+  RiscVTop(const RiscVTop&) = delete;
+  RiscVTop& operator=(const RiscVTop&) = delete;
   ~RiscVTop() override;
 
   // Methods inherited from CoreDebugInterface.
@@ -88,14 +88,14 @@
   absl::StatusOr<HaltReasonValueType> GetLastHaltReason() override;
 
   // Register access by register name.
-  absl::StatusOr<uint64_t> ReadRegister(const std::string &name) override;
-  absl::Status WriteRegister(const std::string &name, uint64_t value) override;
-  absl::StatusOr<generic::DataBuffer *> GetRegisterDataBuffer(
-      const std::string &name) override;
+  absl::StatusOr<uint64_t> ReadRegister(const std::string& name) override;
+  absl::Status WriteRegister(const std::string& name, uint64_t value) override;
+  absl::StatusOr<generic::DataBuffer*> GetRegisterDataBuffer(
+      const std::string& name) override;
   // Read and Write memory methods bypass any semihosting.
-  absl::StatusOr<size_t> ReadMemory(uint64_t address, void *buf,
+  absl::StatusOr<size_t> ReadMemory(uint64_t address, void* buf,
                                     size_t length) override;
-  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void *buf,
+  absl::StatusOr<size_t> WriteMemory(uint64_t address, const void* buf,
                                      size_t length) override;
   // Breakpoints.
   bool HasBreakpoint(uint64_t address) override;
@@ -119,12 +119,12 @@
   // If successful, returns a pointer to the instruction at the given address.
   // The instruction object is IncRef'ed, and the caller must DecRef the object
   // when it is done with it.
-  absl::StatusOr<Instruction *> GetInstruction(uint64_t address) override;
+  absl::StatusOr<Instruction*> GetInstruction(uint64_t address) override;
   absl::StatusOr<std::string> GetDisassembly(uint64_t address) override;
 
   // Called when a halt is requested.
-  void RequestHalt(HaltReason halt_reason, const Instruction *inst);
-  void RequestHalt(HaltReasonValueType halt_reason, const Instruction *inst);
+  void RequestHalt(HaltReason halt_reason, const Instruction* inst);
+  void RequestHalt(HaltReasonValueType halt_reason, const Instruction* inst);
 
   // Resize branch trace.
   absl::Status ResizeBranchTrace(size_t size);
@@ -134,31 +134,31 @@
   void DisableStatistics();
 
   // Accessors.
-  RiscVState *state() const { return state_; }
+  RiscVState* state() const { return state_; }
 
   // The following are not const as callers may need to call non-const methods
   // of the counter.
-  generic::SimpleCounter<uint64_t> *counter_num_instructions() {
+  generic::SimpleCounter<uint64_t>* counter_num_instructions() {
     return &counter_num_instructions_;
   }
-  generic::SimpleCounter<uint64_t> *counter_num_cycles() {
+  generic::SimpleCounter<uint64_t>* counter_num_cycles() {
     return &counter_num_cycles_;
   }
-  generic::SimpleCounter<uint64_t> *counter_pc() { return &counter_pc_; }
+  generic::SimpleCounter<uint64_t>* counter_pc() { return &counter_pc_; }
   // Memory watchers used for data watch points.
-  util::MemoryWatcher *memory_watcher() { return memory_watcher_; }
+  util::MemoryWatcher* memory_watcher() { return memory_watcher_; }
 
-  const std::string &halt_string() const { return halt_string_; }
+  const std::string& halt_string() const { return halt_string_; }
   void set_halt_string(std::string halt_string) { halt_string_ = halt_string; }
 
-  Cache *icache() const { return icache_; }
-  Cache *dcache() const { return dcache_; }
+  Cache* icache() const { return icache_; }
+  Cache* dcache() const { return dcache_; }
 
  private:
   // Initialize the top.
   void Initialize();
   // Configure cache helper method.
-  void ConfigureCache(Cache *&cache, Config<std::string> &config);
+  void ConfigureCache(Cache*& cache, Config<std::string>& config);
   // Helper method to step past a breakpoint.
   absl::Status StepPastBreakpoint();
   // Set the pc value.
@@ -176,32 +176,32 @@
   bool halted_ = false;
   // Set to true if the next instruction requires a step-over.
   bool need_to_step_over_ = false;
-  absl::Notification *run_halted_ = nullptr;
-  absl::Notification *run_started_ = nullptr;
+  absl::Notification* run_halted_ = nullptr;
+  absl::Notification* run_started_ = nullptr;
   // The local RiscV32 state.
-  RiscVState *state_;
+  RiscVState* state_;
   // Memory interface used by action point manager.
-  RiscVActionPointMemoryInterface *rv_action_point_memory_interface_ = nullptr;
+  RiscVActionPointMemoryInterface* rv_action_point_memory_interface_ = nullptr;
   // Action point manager.
-  ActionPointManagerBase *rv_action_point_manager_ = nullptr;
+  ActionPointManagerBase* rv_action_point_manager_ = nullptr;
   // Breakpoint manager.
-  BreakpointManager *rv_breakpoint_manager_ = nullptr;
+  BreakpointManager* rv_breakpoint_manager_ = nullptr;
   // Textual description of halt reason.
   std::string halt_string_;
   // The pc register instance.
-  generic::RegisterBase *pc_;
+  generic::RegisterBase* pc_;
   // RiscV32 decoder instance.
-  generic::DecoderInterface *rv_decoder_ = nullptr;
+  generic::DecoderInterface* rv_decoder_ = nullptr;
   // Decode cache, memory and memory watcher.
-  generic::DecodeCache *rv_decode_cache_ = nullptr;
-  util::MemoryWatcher *memory_watcher_ = nullptr;
+  generic::DecodeCache* rv_decode_cache_ = nullptr;
+  util::MemoryWatcher* memory_watcher_ = nullptr;
   // Branch trace info - uses a circular buffer. The size is defined by the
   // constant kBranchTraceSize in the .cc file.
-  BranchTraceEntry *branch_trace_;
+  BranchTraceEntry* branch_trace_;
   // Data buffer used to hold the branch trace info. This is used so that it
   // can be returned to the debug command shell using the GetRegisterDataBuffer
   // call.
-  DataBuffer *branch_trace_db_ = nullptr;
+  DataBuffer* branch_trace_db_ = nullptr;
   // Points to the most recently written entry in the circular buffer.
   int branch_trace_head_ = 0;
   int branch_trace_mask_ = kBranchTraceSize - 1;
@@ -219,9 +219,9 @@
   Config<std::string> icache_config_;
   Config<std::string> dcache_config_;
   // ICache & DCache.
-  Cache *dcache_ = nullptr;
-  Cache *icache_ = nullptr;
-  DataBuffer *inst_db_ = nullptr;
+  Cache* dcache_ = nullptr;
+  Cache* icache_ = nullptr;
+  DataBuffer* inst_db_ = nullptr;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv_vector_basic_bit_manipulation_instructions.cc b/riscv/riscv_vector_basic_bit_manipulation_instructions.cc
index d6d8273..6f90aad 100644
--- a/riscv/riscv_vector_basic_bit_manipulation_instructions.cc
+++ b/riscv/riscv_vector_basic_bit_manipulation_instructions.cc
@@ -31,8 +31,8 @@
 namespace sim {
 namespace riscv {
 
-void RV32VUnimplementedInstruction(const Instruction *inst) {
-  auto *state = static_cast<RiscVState *>(inst->state());
+void RV32VUnimplementedInstruction(const Instruction* inst) {
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
               *ExceptionCode::kIllegalInstruction,
               /*epc*/ inst->address(), inst);
@@ -61,8 +61,8 @@
 }
 }  // namespace
 
-void Vandn(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vandn(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -88,8 +88,8 @@
   }
 }
 
-void Vbrev8(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vbrev8(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -100,8 +100,8 @@
       return RiscVUnaryVectorOp<uint16_t, uint16_t>(
           rv_vector, inst, [](uint16_t vs2) -> uint16_t {
             absl::Span<uint8_t> span =
-                absl::MakeSpan(reinterpret_cast<uint8_t *>(&vs2), sizeof(vs2));
-            for (uint8_t &byte : span) {
+                absl::MakeSpan(reinterpret_cast<uint8_t*>(&vs2), sizeof(vs2));
+            for (uint8_t& byte : span) {
               byte = BitReverse(byte);
             }
             return vs2;
@@ -110,8 +110,8 @@
       return RiscVUnaryVectorOp<uint32_t, uint32_t>(
           rv_vector, inst, [](uint32_t vs2) -> uint32_t {
             absl::Span<uint8_t> span =
-                absl::MakeSpan(reinterpret_cast<uint8_t *>(&vs2), sizeof(vs2));
-            for (uint8_t &byte : span) {
+                absl::MakeSpan(reinterpret_cast<uint8_t*>(&vs2), sizeof(vs2));
+            for (uint8_t& byte : span) {
               byte = BitReverse(byte);
             }
             return vs2;
@@ -120,8 +120,8 @@
       return RiscVUnaryVectorOp<uint64_t, uint64_t>(
           rv_vector, inst, [](uint64_t vs2) -> uint64_t {
             absl::Span<uint8_t> span =
-                absl::MakeSpan(reinterpret_cast<uint8_t *>(&vs2), sizeof(vs2));
-            for (uint8_t &byte : span) {
+                absl::MakeSpan(reinterpret_cast<uint8_t*>(&vs2), sizeof(vs2));
+            for (uint8_t& byte : span) {
               byte = BitReverse(byte);
             }
             return vs2;
@@ -133,8 +133,8 @@
   }
 }
 
-void Vrev8(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrev8(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -159,8 +159,8 @@
   }
 }
 
-void Vrol(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrol(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -194,8 +194,8 @@
   }
 }
 
-void Vror(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vror(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -231,8 +231,8 @@
 
 // Instructions that are only in Zvbb
 
-void Vbrev(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vbrev(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -258,8 +258,8 @@
   }
 }
 
-void Vclz(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vclz(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -285,8 +285,8 @@
   }
 }
 
-void Vctz(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vctz(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -312,8 +312,8 @@
   }
 }
 
-void VectorVcpop(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VectorVcpop(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -339,8 +339,8 @@
   }
 }
 
-void Vwsll(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwsll(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
diff --git a/riscv/riscv_vector_basic_bit_manipulation_instructions.h b/riscv/riscv_vector_basic_bit_manipulation_instructions.h
index 9c4f1c6..271be40 100644
--- a/riscv/riscv_vector_basic_bit_manipulation_instructions.h
+++ b/riscv/riscv_vector_basic_bit_manipulation_instructions.h
@@ -23,26 +23,26 @@
 
 using Instruction = ::mpact::sim::generic::Instruction;
 
-void RV32VUnimplementedInstruction(const Instruction *inst);
+void RV32VUnimplementedInstruction(const Instruction* inst);
 
 // Vector bit manipulation instructions.
 
 // Zvkb subset of instructions
-void Vandn(Instruction *);
-void Vbrev8(Instruction *);
-void Vrev8(Instruction *);
-void Vrol(Instruction *);
-void Vror(Instruction *);
+void Vandn(Instruction*);
+void Vbrev8(Instruction*);
+void Vrev8(Instruction*);
+void Vrol(Instruction*);
+void Vror(Instruction*);
 
 // Zvbb instructions
-void Vbrev(Instruction *);
-void Vclz(Instruction *);
-void Vctz(Instruction *);
+void Vbrev(Instruction*);
+void Vclz(Instruction*);
+void Vctz(Instruction*);
 // There is a name collision with an existing Vcpop instruction that stores the
 // result in a scalar register. This implementation stores the result in a
 // vector register.
-void VectorVcpop(Instruction *);
-void Vwsll(Instruction *);
+void VectorVcpop(Instruction*);
+void Vwsll(Instruction*);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_fp_compare_instructions.cc b/riscv/riscv_vector_fp_compare_instructions.cc
index b734145..2d6b1a3 100644
--- a/riscv/riscv_vector_fp_compare_instructions.cc
+++ b/riscv/riscv_vector_fp_compare_instructions.cc
@@ -15,7 +15,6 @@
 #include "riscv/riscv_vector_fp_compare_instructions.h"
 
 #include "absl/log/log.h"
-#include "mpact/sim/generic/instruction.h"
 #include "riscv/riscv_state.h"
 #include "riscv/riscv_vector_instruction_helpers.h"
 #include "riscv/riscv_vector_state.h"
@@ -25,8 +24,8 @@
 namespace riscv {
 
 // Vector floating point compare equal.
-void Vmfeq(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmfeq(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -45,8 +44,8 @@
 }
 
 // Vector floating point compare less than or equal.
-void Vmfle(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmfle(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -65,8 +64,8 @@
 }
 
 // Vector floating compare less than.
-void Vmflt(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmflt(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -85,8 +84,8 @@
 }
 
 // Vector floating point compare not equal.
-void Vmfne(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmfne(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -105,8 +104,8 @@
 }
 
 // Vector floating point compare greater than.
-void Vmfgt(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmfgt(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -125,8 +124,8 @@
 }
 
 // Vector floating point compare greater than or equal.
-void Vmfge(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmfge(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
diff --git a/riscv/riscv_vector_fp_compare_instructions.h b/riscv/riscv_vector_fp_compare_instructions.h
index 1e6eb64..1975ea6 100644
--- a/riscv/riscv_vector_fp_compare_instructions.h
+++ b/riscv/riscv_vector_fp_compare_instructions.h
@@ -31,12 +31,12 @@
 // Vmfge only take the scalar register), source operand 2 is the vector mask
 // register. Destination operand 0 is a vector register treated as the
 // destination mask register.
-void Vmfeq(const Instruction *inst);
-void Vmfle(const Instruction *inst);
-void Vmflt(const Instruction *inst);
-void Vmfne(const Instruction *inst);
-void Vmfgt(const Instruction *inst);
-void Vmfge(const Instruction *inst);
+void Vmfeq(const Instruction* inst);
+void Vmfle(const Instruction* inst);
+void Vmflt(const Instruction* inst);
+void Vmfne(const Instruction* inst);
+void Vmfgt(const Instruction* inst);
+void Vmfge(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_fp_instructions.cc b/riscv/riscv_vector_fp_instructions.cc
index dc1c9df..5fec18f 100644
--- a/riscv/riscv_vector_fp_instructions.cc
+++ b/riscv/riscv_vector_fp_instructions.cc
@@ -35,9 +35,9 @@
 using ::mpact::sim::generic::FPTypeInfo;
 
 // Floating point add.
-void Vfadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -62,9 +62,9 @@
 }
 
 // Floating point subtract.
-void Vfsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -89,9 +89,9 @@
 }
 
 // Reverse floating point subtract (rs1 - vs2).
-void Vfrsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfrsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -116,9 +116,9 @@
 }
 
 // Widening floating point add.
-void Vfwadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -142,9 +142,9 @@
 }
 
 // Widening floating point subtract.
-void Vfwsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -168,9 +168,9 @@
 }
 
 // Widening floating point add with wide operand (vs2).
-void Vfwaddw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwaddw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -193,9 +193,9 @@
 }
 
 // Widening floating point subtract with wide operand (vs2).
-void Vfwsubw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwsubw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -218,9 +218,9 @@
 }
 
 // Floating point multiply.
-void Vfmul(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmul(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -245,9 +245,9 @@
 }
 
 // Floating point division vs2/vs1;
-void Vfdiv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfdiv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -272,9 +272,9 @@
 }
 
 // Floating point reverse division vs1/vs2.
-void Vfrdiv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfrdiv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -299,9 +299,9 @@
 }
 
 // Widening floating point multiply.
-void Vfwmul(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwmul(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -325,9 +325,9 @@
 }
 
 // Floating point multiply and add vs2.
-void Vfmadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -354,9 +354,9 @@
 }
 
 // Negated floating point multiply and add vs2.
-void Vfnmadd(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfnmadd(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -383,9 +383,9 @@
 }
 
 // Floating point multiply and subtract vs2.
-void Vfmsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -412,9 +412,9 @@
 }
 
 // Negated floating point multiply and subtract vs2.
-void Vfnmsub(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfnmsub(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -441,9 +441,9 @@
 }
 
 // Floating point multiply and accumulate vd.
-void Vfmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -470,9 +470,9 @@
 }
 
 // Negated floating point multiply and accumulate vd.
-void Vfnmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfnmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -499,9 +499,9 @@
 }
 
 // Floating point multiply and subtract vd.
-void Vfmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -528,9 +528,9 @@
 }
 
 // Negated floating point multiply and subtract vd.
-void Vfnmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfnmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -557,9 +557,9 @@
 }
 
 // Widening floating point multiply and accumulate vd.
-void Vfwmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -583,9 +583,9 @@
 }
 
 // Widening negated floating point multiply and accumulate vd.
-void Vfwnmacc(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwnmacc(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -609,9 +609,9 @@
 }
 
 // Widening floating point multiply and subtract vd.
-void Vfwmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -635,9 +635,9 @@
 }
 
 // Widening negated floating point multiply and subtract vd.
-void Vfwnmsac(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwnmsac(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -661,8 +661,8 @@
 }
 
 // Change the sign of vs2 to the sign of vs1.
-void Vfsgnj(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfsgnj(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -684,8 +684,8 @@
 }
 
 // Change the sign of vs2 to the negation of the sign of vs1.
-void Vfsgnjn(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfsgnjn(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -707,8 +707,8 @@
 }
 
 // Change the sign of vs2 to the xor of the sign of the two operands.
-void Vfsgnjx(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfsgnjx(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -741,7 +741,7 @@
   }
   if (FPTypeInfo<T>::IsNaN(vs2) && FPTypeInfo<T>::IsNaN(vs1)) {
     auto c_nan = FPTypeInfo<T>::kCanonicalNaN;
-    return std::make_tuple(*reinterpret_cast<T *>(&c_nan), flag);
+    return std::make_tuple(*reinterpret_cast<T*>(&c_nan), flag);
   }
   // If either operand is a NaN return the other.
   if (FPTypeInfo<T>::IsNaN(vs2)) return std::tie(vs1, flag);
@@ -756,8 +756,8 @@
 }
 
 // Vector floating point min.
-void Vfmin(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmin(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -786,8 +786,8 @@
 }
 
 // Vector floating point max.
-void Vfmax(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmax(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -816,8 +816,8 @@
 }
 
 // Vector fp merge.
-void Vfmerge(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmerge(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
diff --git a/riscv/riscv_vector_fp_instructions.h b/riscv/riscv_vector_fp_instructions.h
index fe7e7a7..8304ff0 100644
--- a/riscv/riscv_vector_fp_instructions.h
+++ b/riscv/riscv_vector_fp_instructions.h
@@ -31,52 +31,52 @@
 // register group, source 1 is either a vector register group or a scalar
 // register, and source 2 is the mask register. Destination 0 is a vector
 // register group.
-void Vfadd(const Instruction *inst);
-void Vfsub(const Instruction *inst);
-void Vfrsub(const Instruction *inst);
-void Vfwadd(const Instruction *inst);
-void Vfwsub(const Instruction *inst);
-void Vfwaddw(const Instruction *inst);
-void Vfwsubw(const Instruction *inst);
-void Vfmul(const Instruction *inst);
-void Vfdiv(const Instruction *inst);
-void Vfrdiv(const Instruction *inst);
-void Vfwmul(const Instruction *inst);
+void Vfadd(const Instruction* inst);
+void Vfsub(const Instruction* inst);
+void Vfrsub(const Instruction* inst);
+void Vfwadd(const Instruction* inst);
+void Vfwsub(const Instruction* inst);
+void Vfwaddw(const Instruction* inst);
+void Vfwsubw(const Instruction* inst);
+void Vfmul(const Instruction* inst);
+void Vfdiv(const Instruction* inst);
+void Vfrdiv(const Instruction* inst);
+void Vfwmul(const Instruction* inst);
 
 // Vector floating point multiply and add/subtract instructions. Each of these
 // instructions take four source operands and one destination operand. Source 0
 // is a vector register group, source 1 is either a vector register group or a
 // scalar register, source 2 is a vector register group, and source 3 is the
 // mask register. Destination 0 is a vector register group.
-void Vfmadd(const Instruction *inst);
-void Vfnmadd(const Instruction *inst);
-void Vfmsub(const Instruction *inst);
-void Vfnmsub(const Instruction *inst);
-void Vfmacc(const Instruction *inst);
-void Vfnmacc(const Instruction *inst);
-void Vfmsac(const Instruction *inst);
-void Vfnmsac(const Instruction *inst);
-void Vfwmacc(const Instruction *inst);
-void Vfwnmacc(const Instruction *inst);
-void Vfwmsac(const Instruction *inst);
-void Vfwnmsac(const Instruction *inst);
+void Vfmadd(const Instruction* inst);
+void Vfnmadd(const Instruction* inst);
+void Vfmsub(const Instruction* inst);
+void Vfnmsub(const Instruction* inst);
+void Vfmacc(const Instruction* inst);
+void Vfnmacc(const Instruction* inst);
+void Vfmsac(const Instruction* inst);
+void Vfnmsac(const Instruction* inst);
+void Vfwmacc(const Instruction* inst);
+void Vfwnmacc(const Instruction* inst);
+void Vfwmsac(const Instruction* inst);
+void Vfwnmsac(const Instruction* inst);
 
 // Vector floating point sign modification instructions. Each of these
 // instructions take three source operands and one destination operand. Source 0
 // is a vector register group, source 1 is either a vector register group or a
 // scalar register, and source 2 is the mask register. Destination 0 is a vector
 // register group.
-void Vfsgnj(const Instruction *inst);
-void Vfsgnjn(const Instruction *inst);
-void Vfsgnjx(const Instruction *inst);
+void Vfsgnj(const Instruction* inst);
+void Vfsgnjn(const Instruction* inst);
+void Vfsgnjx(const Instruction* inst);
 
 // Vector selection instructions. Each of these instructions take three source
 // operands and one destination operand. Source 0 is a vector register group,
 // source 1 is either a vector register group or a scalar register, and source 2
 // is the mask register. Destination 0 is a vector register group.
-void Vfmin(const Instruction *inst);
-void Vfmax(const Instruction *inst);
-void Vfmerge(const Instruction *inst);
+void Vfmin(const Instruction* inst);
+void Vfmax(const Instruction* inst);
+void Vfmerge(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_fp_reduction_instructions.cc b/riscv/riscv_vector_fp_reduction_instructions.cc
index cf494e8..d2cab08 100644
--- a/riscv/riscv_vector_fp_reduction_instructions.cc
+++ b/riscv/riscv_vector_fp_reduction_instructions.cc
@@ -35,9 +35,9 @@
 // separate entry in the destination vector.
 
 // Sum reduction.
-void Vfredosum(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfredosum(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -63,9 +63,9 @@
   }
 }
 
-void Vfwredosum(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwredosum(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -95,7 +95,7 @@
   if (FPTypeInfo<T>::IsSNaN(vs1) || FPTypeInfo<T>::IsSNaN(vs2) ||
       (FPTypeInfo<T>::IsNaN(vs2) && FPTypeInfo<T>::IsNaN(vs1))) {
     typename FPTypeInfo<T>::UIntType c_nan = FPTypeInfo<T>::kCanonicalNaN;
-    return *reinterpret_cast<T *>(&c_nan);
+    return *reinterpret_cast<T*>(&c_nan);
   }
   // If either operand is a NaN return the other.
   if (FPTypeInfo<T>::IsNaN(vs2)) return vs1;
@@ -105,9 +105,9 @@
 }
 
 // FP min reduction.
-void Vfredmin(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfredmin(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -141,9 +141,9 @@
 }
 
 // FP max reduction.
-void Vfredmax(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfredmax(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
diff --git a/riscv/riscv_vector_fp_reduction_instructions.h b/riscv/riscv_vector_fp_reduction_instructions.h
index a997632..f84b409 100644
--- a/riscv/riscv_vector_fp_reduction_instructions.h
+++ b/riscv/riscv_vector_fp_reduction_instructions.h
@@ -30,10 +30,10 @@
 // destination operand. Source 0 is a vector register group, source 1 is a
 // vector register, and source 2 is the vector mask register. Destination
 // operand 0 is a vector register group.
-void Vfredosum(const Instruction *inst);
-void Vfwredosum(const Instruction *inst);
-void Vfredmin(const Instruction *inst);
-void Vfredmax(const Instruction *inst);
+void Vfredosum(const Instruction* inst);
+void Vfwredosum(const Instruction* inst);
+void Vfredmin(const Instruction* inst);
+void Vfredmax(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_fp_unary_instructions.cc b/riscv/riscv_vector_fp_unary_instructions.cc
index 822f99a..c777429 100644
--- a/riscv/riscv_vector_fp_unary_instructions.cc
+++ b/riscv/riscv_vector_fp_unary_instructions.cc
@@ -61,15 +61,15 @@
     4,   3,   3,   2,   2,   1,   1,   0};
 
 // Move float from scalar fp register to vector register(all elements).
-void Vfmvvf(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmvvf(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   const int vl = rv_vector->vector_length();
   if (rv_vector->vstart() > 0) return;
   if (vl == 0) return;
 
   const int sew = rv_vector->selected_element_width();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   switch (sew) {
     case 4:
@@ -95,13 +95,13 @@
 }
 
 // Move float from vector to scalar fp register(first element).
-void Vfmvsf(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmvsf(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart() > 0) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   switch (sew) {
     case 4:
@@ -123,8 +123,8 @@
 }
 
 // Move scalar floating point value to element 0 of vector register.
-void Vfmvfs(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfmvfs(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto dest_op = inst->Destination(0);
   auto dest_db = dest_op->AllocateDataBuffer();
@@ -157,9 +157,9 @@
 }
 
 // Convert floating point to unsigned integer.
-void Vfcvtxufv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfcvtxufv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -185,9 +185,9 @@
 }
 
 // Convert floating point to signed integer.
-void Vfcvtxfv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfcvtxfv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -213,9 +213,9 @@
 }
 
 // Convert unsigned integer to floating point.
-void Vfcvtfxuv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfcvtfxuv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -240,9 +240,9 @@
 }
 
 // Convert signed integer to floating point.
-void Vfcvtfxv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfcvtfxv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -267,9 +267,9 @@
 }
 
 // Convert floating point to unsigned integer with truncation.
-void Vfcvtrtzxufv(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfcvtrtzxufv(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -290,9 +290,9 @@
 }
 
 // Convert floating point to signed integer with truncation.
-void Vfcvtrtzxfv(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfcvtrtzxfv(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -313,9 +313,9 @@
 }
 
 // Widening conversion of floating point to unsigned integer.
-void Vfwcvtxufv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwcvtxufv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -336,9 +336,9 @@
 }
 
 // Widening conversion of floating point to signed integer.
-void Vfwcvtxfv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwcvtxfv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -359,8 +359,8 @@
 }
 
 // Wideing conversion of floating point to floating point.
-void Vfwcvtffv(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwcvtffv(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -375,9 +375,9 @@
 }
 
 // Widening conversion of unsigned integer to floating point.
-void Vfwcvtfxuv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwcvtfxuv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -402,9 +402,9 @@
 }
 
 // Widening conversion of signed integer to floating point.
-void Vfwcvtfxv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfwcvtfxv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -429,9 +429,9 @@
 }
 
 // Widening conversion of floating point to unsigned integer with truncation.
-void Vfwcvtrtzxufv(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfwcvtrtzxufv(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -447,9 +447,9 @@
 }
 
 // Widening conversion of floating point to signed integer with truncation.
-void Vfwcvtrtzxfv(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfwcvtrtzxfv(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -465,9 +465,9 @@
 }
 
 // Narrowing conversion of floating point to unsigned integer.
-void Vfncvtxufw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtxufw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -493,9 +493,9 @@
 }
 
 // Narrowing conversion of floating point to signed integer.
-void Vfncvtxfw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtxfw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -521,9 +521,9 @@
 }
 
 // Narrowing conversion of floating point to floating point.
-void Vfncvtffw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtffw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -544,9 +544,9 @@
 }
 
 // Narrowing conversion of floating point to floating point rounding to odd.
-void Vfncvtrodffw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtrodffw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -566,16 +566,16 @@
             }
             using UIntD = typename FPTypeInfo<double>::UIntType;
             using UIntF = typename FPTypeInfo<float>::UIntType;
-            UIntD uval = *reinterpret_cast<UIntD *>(&vs2);
+            UIntD uval = *reinterpret_cast<UIntD*>(&vs2);
             int sig_diff =
                 FPTypeInfo<double>::kSigSize - FPTypeInfo<float>::kSigSize;
             UIntD mask = (1ULL << sig_diff) - 1;
             UIntF bit = (mask & uval) != 0;
             auto res = static_cast<float>(vs2);
             if (FPTypeInfo<float>::IsInf(res)) return res;
-            UIntF ures = *reinterpret_cast<UIntF *>(&res);
+            UIntF ures = *reinterpret_cast<UIntF*>(&res);
             ures |= bit;
-            return *reinterpret_cast<float *>(&ures);
+            return *reinterpret_cast<float*>(&ures);
           });
     default:
       LOG(ERROR) << "Vfwcvt.rod.f.fw: Illegal sew (" << sew << ")";
@@ -585,9 +585,9 @@
 }
 
 // Narrowing conversion of unsigned integer to floating point.
-void Vfncvtfxuw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtfxuw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -608,9 +608,9 @@
 }
 
 // Narrowing conversion of signed integeer to floating point.
-void Vfncvtfxw(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfncvtfxw(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -631,9 +631,9 @@
 }
 
 // Narrowing conversion of floating point to unsigned integer with truncation.
-void Vfncvtrtzxufw(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfncvtrtzxufw(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -654,9 +654,9 @@
 }
 
 // Narrowing conversion of floating point to signed integer with truncation.
-void Vfncvtrtzxfw(const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vfncvtrtzxfw(const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -683,7 +683,7 @@
   T res;
   if (FPTypeInfo<T>::IsNaN(vs2) || vs2 < 0.0) {
     auto value = FPTypeInfo<T>::kCanonicalNaN;
-    res = *reinterpret_cast<T *>(&value);
+    res = *reinterpret_cast<T*>(&value);
     flags = *FPExceptions::kInvalidOp;
     return std::tie(res, flags);
   }
@@ -693,9 +693,9 @@
 }
 
 // Square root.
-void Vfsqrtv(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfsqrtv(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (!rv_fp->rounding_mode_valid()) {
     LOG(ERROR) << "Invalid rounding mode";
     rv_vector->set_vector_exception();
@@ -728,7 +728,7 @@
         return;
     }
   }
-  auto *fflags = rv_fp->fflags();
+  auto* fflags = rv_fp->fflags();
   fflags->Write(flags | fflags->AsUint32());
 }
 
@@ -737,7 +737,7 @@
 template <typename T>
 inline T RecipSqrt7(T value) {
   using Uint = typename FPTypeInfo<T>::UIntType;
-  Uint uint_value = *reinterpret_cast<Uint *>(&value);
+  Uint uint_value = *reinterpret_cast<Uint*>(&value);
   // The input value is positive. Negative values are already handled.
   int norm_exponent =
       (uint_value & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
@@ -760,7 +760,7 @@
                       << (FPTypeInfo<T>::kSigSize - 7);
   Uint new_exponent = (3 * FPTypeInfo<T>::kExpBias - 1 - norm_exponent) / 2;
   Uint new_value = (new_exponent << FPTypeInfo<T>::kSigSize) | new_mantissa;
-  T new_fp_value = *reinterpret_cast<T *>(&new_value);
+  T new_fp_value = *reinterpret_cast<T*>(&new_value);
   return new_fp_value;
 }
 
@@ -804,9 +804,9 @@
 }
 
 // Approximation of reciprocal square root to 7 bits mantissa.
-void Vfrsqrt7v(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfrsqrt7v(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -834,7 +834,7 @@
 inline T Recip7(T value, FPRoundingMode rm) {
   using Uint = typename FPTypeInfo<T>::UIntType;
   using Int = typename FPTypeInfo<T>::IntType;
-  Uint uint_value = *reinterpret_cast<Uint *>(&value);
+  Uint uint_value = *reinterpret_cast<Uint*>(&value);
   Int norm_exponent =
       (uint_value & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
   Uint norm_mantissa = uint_value & FPTypeInfo<T>::kSigMask;
@@ -888,7 +888,7 @@
     new_mantissa &= 0b111'1111;
   }
   Uint new_value = (new_exponent << FPTypeInfo<T>::kSigSize) | new_mantissa;
-  T new_fp_value = *reinterpret_cast<T *>(&new_value);
+  T new_fp_value = *reinterpret_cast<T*>(&new_value);
   return value < 0.0 ? -new_fp_value : new_fp_value;
 }
 
@@ -916,9 +916,9 @@
 }
 
 // Approximate reciprocal to 7 bits of mantissa.
-void Vfrec7v(const Instruction *inst) {
-  auto *rv_fp = static_cast<RiscVState *>(inst->state())->rv_fp();
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfrec7v(const Instruction* inst) {
+  auto* rv_fp = static_cast<RiscVState*>(inst->state())->rv_fp();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   ScopedFPStatus set_fpstatus(rv_fp->host_fp_interface());
   auto rm = rv_fp->GetRoundingMode();
@@ -939,8 +939,8 @@
 }
 
 // Classify floating point value.
-void Vfclassv(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfclassv(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
diff --git a/riscv/riscv_vector_fp_unary_instructions.h b/riscv/riscv_vector_fp_unary_instructions.h
index abd70dd..8648580 100644
--- a/riscv/riscv_vector_fp_unary_instructions.h
+++ b/riscv/riscv_vector_fp_unary_instructions.h
@@ -27,11 +27,11 @@
 using Instruction = ::mpact::sim::generic::Instruction;
 
 // Move a single floating point value from vector[0] to vector[vl-1].
-void Vfmvvf(const Instruction *inst);
+void Vfmvvf(const Instruction* inst);
 // Move a single floating point value from vector[0] to scalar fp register.
-void Vfmvsf(const Instruction *inst);
+void Vfmvsf(const Instruction* inst);
 // Move single floating point value from scalar fp register to vector[0].
-void Vfmvfs(const Instruction *inst);
+void Vfmvfs(const Instruction* inst);
 
 // Each of the following semantic functions take 2 source operands and 1
 // destination operand. Source operand 0 is a vector register group, source
@@ -44,17 +44,17 @@
 // rounding mode.
 
 // FP to unsigned integer.
-void Vfcvtxufv(const Instruction *inst);
+void Vfcvtxufv(const Instruction* inst);
 // FP to signed integer.
-void Vfcvtxfv(const Instruction *inst);
+void Vfcvtxfv(const Instruction* inst);
 // Unsigned integer to FP.
-void Vfcvtfxuv(const Instruction *inst);
+void Vfcvtfxuv(const Instruction* inst);
 // Signed integer to FP.
-void Vfcvtfxv(const Instruction *inst);
+void Vfcvtfxv(const Instruction* inst);
 // FP to unsigned integer using round to zero.
-void Vfcvtrtzxufv(const Instruction *inst);
+void Vfcvtrtzxufv(const Instruction* inst);
 // FP to signed integer using round to zero.
-void Vfcvtrtzxfv(const Instruction *inst);
+void Vfcvtrtzxfv(const Instruction* inst);
 
 // Vector element widening conversion instructions. These convert values from/to
 // signed/unsigned integer and floating point, where the resulting value is 2x
@@ -62,19 +62,19 @@
 // zero), whereas the others use the dynamically set rounding mode.
 
 // FP to wider unsigned integer.
-void Vfwcvtxufv(const Instruction *inst);
+void Vfwcvtxufv(const Instruction* inst);
 // FP to wider signed integer.
-void Vfwcvtxfv(const Instruction *inst);
+void Vfwcvtxfv(const Instruction* inst);
 // FP to next wider FP.
-void Vfwcvtffv(const Instruction *inst);
+void Vfwcvtffv(const Instruction* inst);
 // Unsigned integer to wider FP.
-void Vfwcvtfxuv(const Instruction *inst);
+void Vfwcvtfxuv(const Instruction* inst);
 // Signed integer to wider FP.
-void Vfwcvtfxv(const Instruction *inst);
+void Vfwcvtfxv(const Instruction* inst);
 // FP to wider unsigned integer using round to zero.
-void Vfwcvtrtzxufv(const Instruction *inst);
+void Vfwcvtrtzxufv(const Instruction* inst);
 // FP to wider signed integer using round to zero.
-void Vfwcvtrtzxfv(const Instruction *inst);
+void Vfwcvtrtzxfv(const Instruction* inst);
 
 // Vector element widening conversion instructions. These convert values from/to
 // signed/unsigned integer and floating point, where the resulting value is 1/2x
@@ -83,30 +83,30 @@
 // dynamically set rounding mode.
 
 // FP to narrower unsigned integer.
-void Vfncvtxufw(const Instruction *inst);
+void Vfncvtxufw(const Instruction* inst);
 // FP to narrower signed integer.
-void Vfncvtxfw(const Instruction *inst);
+void Vfncvtxfw(const Instruction* inst);
 // FP to next narrower FP.
-void Vfncvtffw(const Instruction *inst);
+void Vfncvtffw(const Instruction* inst);
 // FP to next narrower FP with round to odd.
-void Vfncvtrodffw(const Instruction *inst);
+void Vfncvtrodffw(const Instruction* inst);
 // Unsigned integer to narrower FP.
-void Vfncvtfxuw(const Instruction *inst);
+void Vfncvtfxuw(const Instruction* inst);
 // Signed integer to narrower FP.
-void Vfncvtfxw(const Instruction *inst);
+void Vfncvtfxw(const Instruction* inst);
 // FP to narrower unsigned integer using round to zero.
-void Vfncvtrtzxufw(const Instruction *inst);
+void Vfncvtrtzxufw(const Instruction* inst);
 // FP to narrower signed integer using round to zero.
-void Vfncvtrtzxfw(const Instruction *inst);
+void Vfncvtrtzxfw(const Instruction* inst);
 
 // Vector element square root instruction.
-void Vfsqrtv(const Instruction *inst);
+void Vfsqrtv(const Instruction* inst);
 // Vector element approximate reciprocal square root instruction.
-void Vfrsqrt7v(const Instruction *inst);
+void Vfrsqrt7v(const Instruction* inst);
 // Vector element approximate reciprocal instruction.
-void Vfrec7v(const Instruction *inst);
+void Vfrec7v(const Instruction* inst);
 // Vector element floating point value classify instruction.
-void Vfclassv(const Instruction *inst);
+void Vfclassv(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_instruction_helpers.h b/riscv/riscv_vector_instruction_helpers.h
index e411896..e26aebe 100644
--- a/riscv/riscv_vector_instruction_helpers.h
+++ b/riscv/riscv_vector_instruction_helpers.h
@@ -20,9 +20,10 @@
 #include <functional>
 #include <limits>
 #include <optional>
-#include <type_traits>
+#include <tuple>
 
 #include "absl/log/log.h"
+#include "absl/strings/str_cat.h"
 #include "mpact/sim/generic/instruction.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_state.h"
@@ -41,23 +42,23 @@
 // Note that this function will modify masked bits no matter what the mask
 // value is.
 template <typename Vs2, typename Vs1>
-void RiscVSetMaskBinaryVectorMaskOp(RiscVVectorState *rv_vector,
-                                    const Instruction *inst,
+void RiscVSetMaskBinaryVectorMaskOp(RiscVVectorState* rv_vector,
+                                    const Instruction* inst,
                                     std::function<bool(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Get the vector start element index and compute where to start
   // the operation.
   const int num_elements = rv_vector->vector_length();
   const int vector_index = rv_vector->vstart();
   // Allocate data buffer for the new register data.
-  auto *dest_db = dest_op->CopyDataBuffer();
+  auto* dest_db = dest_op->CopyDataBuffer();
   auto dest_span = dest_db->Get<uint8_t>();
   // Determine if it's vector-vector or vector-scalar.
   const bool vector_scalar = inst->Source(1)->shape()[0] == 1;
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   bool vm_unmasked_bit = false;
   if (inst->SourcesSize() > 3) {
     vm_unmasked_bit = GetInstructionSource<bool>(inst, 3);
@@ -87,23 +88,23 @@
 // mask and uses the mask value in the instruction, such as carry generation
 // from add with carry.
 template <typename Vs2, typename Vs1>
-void RiscVMaskBinaryVectorMaskOp(RiscVVectorState *rv_vector,
-                                 const Instruction *inst,
+void RiscVMaskBinaryVectorMaskOp(RiscVVectorState* rv_vector,
+                                 const Instruction* inst,
                                  std::function<bool(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Get the vector start element index and compute where to start
   // the operation.
   int num_elements = rv_vector->vector_length();
   int vector_index = rv_vector->vstart();
   // Allocate data buffer for the new register data.
-  auto *dest_db = dest_op->CopyDataBuffer();
+  auto* dest_db = dest_op->CopyDataBuffer();
   auto dest_span = dest_db->Get<uint8_t>();
   // Determine if it's vector-vector or vector-scalar.
   bool vector_scalar = inst->Source(1)->shape()[0] == 1;
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   bool vm_unmasked_bit = false;
   if (inst->SourcesSize() > 3) {
     vm_unmasked_bit = GetInstructionSource<bool>(inst, 3);
@@ -136,8 +137,8 @@
 // This helper function handles the case of vector mask
 // operations.
 template <typename Vs2, typename Vs1>
-void RiscVBinaryVectorMaskOp(RiscVVectorState *rv_vector,
-                             const Instruction *inst,
+void RiscVBinaryVectorMaskOp(RiscVVectorState* rv_vector,
+                             const Instruction* inst,
                              std::function<bool(Vs2, Vs1)> op) {
   RiscVMaskBinaryVectorMaskOp<Vs2, Vs1>(
       rv_vector, inst, [op](Vs2 vs2, Vs1 vs1, bool mask_value) -> bool {
@@ -152,16 +153,16 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd>
-void RiscVMaskNullaryVectorOp(RiscVVectorState *rv_vector,
-                              const Instruction *inst,
+void RiscVMaskNullaryVectorOp(RiscVVectorState* rv_vector,
+                              const Instruction* inst,
                               std::function<Vd(bool)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -173,13 +174,13 @@
   // There 2 types of instruction with different number of source operands.
   // 1. inst vd, vs2, vmask (viota instruction)
   // 2. inst vd, vmask (vid instruction)
-  RV32VectorSourceOperand *vs2_op = nullptr;
-  RV32VectorSourceOperand *mask_op = nullptr;
+  RV32VectorSourceOperand* vs2_op = nullptr;
+  RV32VectorSourceOperand* mask_op = nullptr;
   if (inst->SourcesSize() > 1) {
-    vs2_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
-    mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+    vs2_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
+    mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   } else {
-    mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+    mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   }
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
@@ -191,7 +192,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -228,7 +229,7 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd, typename Vs2>
-void RiscVUnaryVectorOp(RiscVVectorState *rv_vector, const Instruction *inst,
+void RiscVUnaryVectorOp(RiscVVectorState* rv_vector, const Instruction* inst,
                         std::function<Vd(Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -249,8 +250,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -260,7 +261,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -271,7 +272,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -300,7 +301,7 @@
 // narrowing operations.
 template <typename Vd, typename Vs2>
 void RiscVUnaryVectorOpWithFflags(
-    RiscVVectorState *rv_vector, const Instruction *inst,
+    RiscVVectorState* rv_vector, const Instruction* inst,
     std::function<std::tuple<Vd, uint32_t>(Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -321,8 +322,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -332,7 +333,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -344,7 +345,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -367,7 +368,7 @@
     dest_db->Submit();
     item_index = 0;
   }
-  auto *flag_db = inst->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = inst->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, fflags);
   flag_db->Submit();
   rv_vector->clear_vstart();
@@ -378,7 +379,7 @@
 // narrowing operations.
 template <typename Vd, typename Vs2, typename Vs1>
 void RiscVMaskBinaryVectorOp(
-    RiscVVectorState *rv_vector, const Instruction *inst,
+    RiscVVectorState* rv_vector, const Instruction* inst,
     std::function<std::optional<Vd>(Vs2, Vs1, bool)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -400,8 +401,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -411,7 +412,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -425,7 +426,7 @@
   for (int reg = start_reg;
        !exception && (reg < max_regs) && (vector_index < num_elements); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -464,7 +465,7 @@
 // operations. It implements all the checking necessary for both widening and
 // narrowing operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVBinaryVectorOp(RiscVVectorState *rv_vector, const Instruction *inst,
+void RiscVBinaryVectorOp(RiscVVectorState* rv_vector, const Instruction* inst,
                          std::function<Vd(Vs2, Vs1)> op) {
   RiscVMaskBinaryVectorOp<Vd, Vs2, Vs1>(
       rv_vector, inst,
@@ -478,7 +479,7 @@
 
 template <typename Vd, typename Vs2, typename Vs1>
 void RiscVBinaryVectorOpWithFflags(
-    RiscVVectorState *rv_vector, const Instruction *inst,
+    RiscVVectorState* rv_vector, const Instruction* inst,
     std::function<std::tuple<Vd, uint32_t>(Vs2, Vs1)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -500,8 +501,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -511,7 +512,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -526,7 +527,7 @@
   for (int reg = start_reg;
        !exception && (reg < max_regs) && (vector_index < num_elements); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -556,7 +557,7 @@
     dest_db->Submit();
     item_index = 0;
   }
-  auto *flag_db = inst->Destination(1)->AllocateDataBuffer();
+  auto* flag_db = inst->Destination(1)->AllocateDataBuffer();
   flag_db->Set<uint32_t>(0, fflags);
   flag_db->Submit();
   rv_vector->clear_vstart();
@@ -566,7 +567,7 @@
 // implements all the checking necessary for both widening and narrowing
 // operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVTernaryVectorOp(RiscVVectorState *rv_vector, const Instruction *inst,
+void RiscVTernaryVectorOp(RiscVVectorState* rv_vector, const Instruction* inst,
                           std::function<Vd(Vs2, Vs1, Vd)> op) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
@@ -588,8 +589,8 @@
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = (num_elements + elements_per_vector - 1) / elements_per_vector;
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -599,7 +600,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute where to start
   // the operation.
@@ -612,7 +613,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -643,8 +644,8 @@
 // masking) from Vs2 and apply the reduction operation to produce a single
 // element that is written to Vd[0].
 template <typename Vd, typename Vs2, typename Vs1>
-void RiscVBinaryReductionVectorOp(RiscVVectorState *rv_vector,
-                                  const Instruction *inst,
+void RiscVBinaryReductionVectorOp(RiscVVectorState* rv_vector,
+                                  const Instruction* inst,
                                   std::function<Vd(Vd, Vs2)> op) {
   if (rv_vector->vector_exception()) return;
   if (rv_vector->vstart()) {
@@ -668,7 +669,7 @@
   }
   int num_elements = rv_vector->vector_length();
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   Vd accumulator =
       static_cast<Vd>(generic::GetInstructionSource<Vs1>(inst, 1, 0));
@@ -681,8 +682,8 @@
           op(accumulator, generic::GetInstructionSource<Vs2>(inst, 0, i));
     }
   }
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   auto dest_db = dest_op->CopyDataBuffer();
   dest_db->Set<Vd>(0, accumulator);
   dest_db->Submit();
@@ -722,7 +723,7 @@
 }
 
 template <typename T>
-T RoundOff(RiscVVectorState *rv_vector, T value, int size) {
+T RoundOff(RiscVVectorState* rv_vector, T value, int size) {
   auto rm = rv_vector->vxrm();
   auto ret = (value >> size) + GetRoundingBit<T>(rm, value, size + 1);
   return ret;
diff --git a/riscv/riscv_vector_memory_instructions.cc b/riscv/riscv_vector_memory_instructions.cc
index 48f9d52..29a1d2b 100644
--- a/riscv/riscv_vector_memory_instructions.cc
+++ b/riscv/riscv_vector_memory_instructions.cc
@@ -36,9 +36,9 @@
 // writes the loaded data into the registers.
 template <typename T>
 absl::Status WriteBackLoadData(int vector_register_byte_length,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
   // Get values from context.
-  auto *context = static_cast<VectorLoadContext *>(inst->context());
+  auto* context = static_cast<VectorLoadContext*>(inst->context());
   auto masks = context->mask_db->Get<bool>();
   auto values = context->value_db->Get<T>();
   int vector_start = context->vstart;
@@ -49,8 +49,8 @@
   int max_regs =
       (vector_length + elements_per_vector - 1) / elements_per_vector;
   // Verify that the dest_op has enough registers. Else signal error.
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (dest_op->size() < max_regs) {
     // TODO: signal error.
     return absl::InternalError("Not enough registers in destination operand");
@@ -70,7 +70,7 @@
   // Iterate over the number of registers to write.
   for (int reg = start_reg; (reg < max_regs) && (value_count > 0); reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<T>();
     // Write data into register subject to masking.
     int count = std::min(elements_per_vector - item_index, value_count);
@@ -91,11 +91,11 @@
 // writes the loaded data into the registers.
 template <typename T>
 absl::Status WriteBackSegmentLoadData(int vector_register_byte_length,
-                                      const Instruction *inst) {
+                                      const Instruction* inst) {
   // The number of fields in each segment.
   int num_fields = GetInstructionSource<uint32_t>(inst, 0) + 1;
   // Get values from context.
-  auto *context = static_cast<VectorLoadContext *>(inst->context());
+  auto* context = static_cast<VectorLoadContext*>(inst->context());
   auto masks = context->mask_db->Get<bool>();
   auto values = context->value_db->Get<T>();
   int start_segment = context->vstart;
@@ -111,8 +111,8 @@
   // Total number of registers written.
   int total_regs = num_fields * num_regs;
   // Verify that the dest_op has enough registers. Else signal error.
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (dest_op->size() < total_regs) {
     return absl::InternalError("Not enough registers in destination operand");
   }
@@ -131,7 +131,7 @@
     int offset = start_segment % max_elements_per_vector;
     int remaining_data = num_segments;
     for (int reg = start_reg; reg < start_reg + num_regs; reg++) {
-      auto *dest_db = dest_op->CopyDataBuffer(reg);
+      auto* dest_db = dest_op->CopyDataBuffer(reg);
       auto span = dest_db->Get<T>();
       int max_entry =
           std::min(remaining_data + offset, max_elements_per_vector);
@@ -152,9 +152,9 @@
 // This models the vsetvl set of instructions. The immediate versus register
 // versions are all modeled by the same function. Flags are bound during decode
 // to the two first parameters to specify if rd or rs1 are x0.
-void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   uint32_t vtype = GetInstructionSource<uint32_t>(inst, 1) & 0b1'1'111'111;
   // Get previous vtype.
   uint32_t prev_vtype = rv_vector->vtype();
@@ -195,7 +195,7 @@
   }
   rv_vector->set_vector_length(vl);
   if (!rd_zero) {  // Update register if there is a writable destination.
-    auto *reg = static_cast<generic::RegisterDestinationOperand<uint32_t> *>(
+    auto* reg = static_cast<generic::RegisterDestinationOperand<uint32_t>*>(
                     inst->Destination(0))
                     ->GetRegister();
     if (rv_state->xlen() == RiscVXlen::RV32) {
@@ -213,8 +213,8 @@
 // Source(1): stride size bytes.
 // Source(2): vector mask register, vector constant {1..} if not masked.
 // Destination(0): vector destination register.
-void VlStrided(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlStrided(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
   int64_t stride = GetInstructionSource<int64_t>(inst, 1);
@@ -231,18 +231,18 @@
   int num_elements_loaded = num_elements - start;
 
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
 
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate(num_elements_loaded * element_width);
+  auto* value_db = db_factory->Allocate(num_elements_loaded * element_width);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Allocate a byte mask data buffer for the load.
-  auto *mask_db = db_factory->Allocate<bool>(num_elements_loaded);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements_loaded);
 
   // Get the spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
@@ -259,9 +259,9 @@
   }
 
   // Set up the context, and submit the load.
-  auto *context = new VectorLoadContext(value_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(value_db, mask_db, element_width, start,
                                         rv_vector->vector_length());
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   value_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width, value_db,
                          inst->child(), context);
@@ -275,20 +275,20 @@
 
 // Source(0): base address.
 // Destination(0): vector destination register (for the child instruction).
-void Vlm(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vlm(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   // Compute base address.
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0) + start;
   // Compute the number of bytes to be loaded.
   int num_bytes = rv_vector->vector_register_byte_length() - start;
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_bytes);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_bytes);
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate<uint8_t>(num_bytes);
+  auto* value_db = db_factory->Allocate<uint8_t>(num_bytes);
   // Allocate a byte mask data buffer.
-  auto *mask_db = db_factory->Allocate<bool>(num_bytes);
+  auto* mask_db = db_factory->Allocate<bool>(num_bytes);
   // Get the spans for addresses and masks.
   auto masks = mask_db->Get<bool>();
   auto addresses = address_db->Get<uint64_t>();
@@ -298,10 +298,10 @@
     masks[i - start] = true;
   }
   // Set up the context, and submit the load.
-  auto *context =
+  auto* context =
       new VectorLoadContext(value_db, mask_db, sizeof(uint8_t), start,
                             rv_vector->vector_register_byte_length());
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   value_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, sizeof(uint8_t), value_db,
                          inst->child(), context);
@@ -322,13 +322,13 @@
 // Source(1) index vector.
 // Source(2) masks.
 // Destination(0): vector destination register (for the child instruction).
-void VlIndexed(int index_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlIndexed(int index_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   int element_width = rv_vector->selected_element_width();
   int lmul = rv_vector->vector_length_multiplier();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   int index_emul = index_width * lmul / element_width;
   // Validate that emul has a legal value.
   if ((index_emul > 64) || (index_emul == 0)) {
@@ -345,19 +345,19 @@
   int num_bytes_loaded = num_elements_loaded * element_width;
 
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements_loaded);
   auto addresses = address_db->Get<uint64_t>();
 
   // Allocate the value data buffer that the loaded data is returned in.
-  auto *value_db = db_factory->Allocate(num_bytes_loaded);
+  auto* value_db = db_factory->Allocate(num_bytes_loaded);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Allocate a byte mask data buffer for the load.
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   auto masks = mask_db->Get<bool>();
 
   // Convert the bit masks to byte masks and compute the element addresses.
@@ -390,9 +390,9 @@
   }
 
   // Set up context and submit load.
-  auto *context = new VectorLoadContext(value_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(value_db, mask_db, element_width, start,
                                         rv_vector->vector_length());
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   value_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width, value_db,
                          inst->child(), context);
@@ -409,17 +409,17 @@
 // Source(0): base address.
 // Destination(0): vector destination register (for the child instruction).
 void VlRegister(int num_regs, int element_width_bytes,
-                const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+                const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   // Get base address.
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
   int num_elements =
       rv_vector->vector_register_byte_length() * num_regs / element_width_bytes;
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width_bytes);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width_bytes);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -436,9 +436,9 @@
   }
 
   // Set up context and submit load.
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width_bytes,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width_bytes,
                                         0, num_elements);
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   data_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width_bytes,
                          data_db, inst->child(), context);
@@ -458,11 +458,11 @@
 // Source(1): mask
 // Source(2): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegment(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlSegment(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 2) + 1;
   // Effective vector length multiplier.
@@ -479,10 +479,10 @@
   int segment_stride = num_fields * element_width;
   int num_elements = num_fields * num_segments;
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -497,9 +497,9 @@
           base + i * segment_stride + field * element_width;
     }
   }
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   data_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
                          inst->child(), context);
@@ -516,12 +516,12 @@
 // Source(2): mask
 // Source(3): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegmentStrided(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlSegmentStrided(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
   int64_t segment_stride = GetInstructionSource<int64_t>(inst, 1);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   // Effective vector length multiplier.
@@ -537,10 +537,10 @@
   int num_segments = rv_vector->vector_length();
   int num_elements = num_fields * num_segments;
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -555,9 +555,9 @@
     }
   }
   // Allocate the context and submit the load.
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   data_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
                          inst->child(), context);
@@ -575,12 +575,12 @@
 // Source(2): mask
 // Source(3): number of fields - 1
 // Destination(0): vector destination register (for the child instruction).
-void VlSegmentIndexed(int index_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlSegmentIndexed(int index_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 0);
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   int element_width = rv_vector->selected_element_width();
@@ -607,10 +607,10 @@
   int num_elements = num_fields * num_segments;
 
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the spans for the addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -647,9 +647,9 @@
       addresses[field * num_segments + i] = base + offset + field;
     }
   }
-  auto *context = new VectorLoadContext(data_db, mask_db, element_width, start,
+  auto* context = new VectorLoadContext(data_db, mask_db, element_width, start,
                                         num_segments);
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   data_db->set_latency(0);
   rv32_state->LoadMemory(inst, address_db, mask_db, element_width, data_db,
                          inst->child(), context);
@@ -662,11 +662,11 @@
 // Child instruction used for non-segment vector loads. This function really
 // only is used to select a type specific version of the helper function to
 // write back the load data.
-void VlChild(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlChild(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   absl::Status status;
   int byte_length = rv_vector->vector_register_byte_length();
-  switch (static_cast<VectorLoadContext *>(inst->context())->element_width) {
+  switch (static_cast<VectorLoadContext*>(inst->context())->element_width) {
     case 1:
       status = WriteBackLoadData<uint8_t>(byte_length, inst);
       break;
@@ -692,11 +692,11 @@
 // Child instruction used for segmen vector loads. This function really only is
 // used to select a type specific version of the helper function to write back
 // the load data.
-void VlSegmentChild(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VlSegmentChild(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   absl::Status status;
   int byte_length = rv_vector->vector_register_byte_length();
-  switch (static_cast<VectorLoadContext *>(inst->context())->element_width) {
+  switch (static_cast<VectorLoadContext*>(inst->context())->element_width) {
     case 1:
       status = WriteBackSegmentLoadData<uint8_t>(byte_length, inst);
       break;
@@ -722,20 +722,20 @@
 // Templated helper function for vector stores.
 template <typename T>
 void StoreVectorStrided(int vector_length, int vstart, int emul,
-                        const Instruction *inst) {
+                        const Instruction* inst) {
   uint64_t base = GetInstructionSource<uint64_t>(inst, 1);
   int64_t stride = GetInstructionSource<int64_t>(inst, 2);
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Compute total number of elements to be stored.
   int num_elements = vector_length;
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
   auto addresses = address_db->Get<uint64_t>();
-  auto *store_data_db = db_factory->Allocate(num_elements * sizeof(T));
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* store_data_db = db_factory->Allocate(num_elements * sizeof(T));
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
 
   // Get the spans for addresses and masks.
   auto store_data = store_data_db->Get<T>();
@@ -750,7 +750,7 @@
     store_data[i - vstart] = GetInstructionSource<T>(inst, 0, i);
   }
   // Perform the store.
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, sizeof(T), store_data_db);
   address_db->DecRef();
   mask_db->DecRef();
@@ -762,8 +762,8 @@
 // Source(1): base address.
 // Source(2): stride.
 // Source(3): vector mask register, vector constant {1..} if not masked.
-void VsStrided(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsStrided(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int emul = element_width * rv_vector->vector_length_multiplier() /
              rv_vector->selected_element_width();
   // Validate that emul has a legal value.
@@ -797,8 +797,8 @@
 // Store vector mask. Single vector register store.
 // Source(0): store data
 // Source(1): base address
-void Vsm(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsm(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   // Compute base address.
   int start = rv_vector->vstart();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 1);
@@ -806,10 +806,10 @@
   int num_bytes = rv_vector->vector_register_byte_length();
   int num_bytes_stored = num_bytes - start;
   // Allocate address data buffer.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_bytes_stored);
-  auto *store_data_db = db_factory->Allocate(num_bytes_stored);
-  auto *mask_db = db_factory->Allocate<uint8_t>(num_bytes_stored);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_bytes_stored);
+  auto* store_data_db = db_factory->Allocate(num_bytes_stored);
+  auto* mask_db = db_factory->Allocate<uint8_t>(num_bytes_stored);
   // Get the spans for addresses, masks, and store data.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -820,7 +820,7 @@
     masks[i - start] = true;
     store_data[i - start] = GetInstructionSource<uint8_t>(inst, 0, i);
   }
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, sizeof(uint8_t),
                           store_data_db);
   address_db->DecRef();
@@ -839,8 +839,8 @@
 // Source(1): base address.
 // Source(2): offset vector.
 // Source(3): mask.
-void VsIndexed(int index_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsIndexed(int index_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   // Compute base address.
   int start = rv_vector->vstart();
   int num_elements = rv_vector->vector_length() - start;
@@ -855,16 +855,16 @@
   }
 
   uint64_t base = GetInstructionSource<uint64_t>(inst, 1);
-  auto *index_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* index_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
 
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *value_db = db_factory->Allocate(num_elements * element_width);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* value_db = db_factory->Allocate(num_elements * element_width);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
 
   // Get the source mask (stored in a single vector register).
-  auto *src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto* src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
 
   // Get the spans for addresses, masks, and data.
@@ -919,7 +919,7 @@
   }
 
   // Set up context and submit store
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, element_width, value_db);
   address_db->DecRef();
   mask_db->DecRef();
@@ -927,16 +927,16 @@
   rv_vector->clear_vstart();
 }
 
-void VsRegister(int num_regs, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsRegister(int num_regs, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   uint64_t base = GetInstructionSource<uint64_t>(inst, 1);
   int num_elements =
       rv_vector->vector_register_byte_length() * num_regs / sizeof(uint64_t);
   // Allocate data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get the address, mask, and data spans.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -946,7 +946,7 @@
     masks[i] = true;
     data[i] = GetInstructionSource<uint64_t>(inst, 0, i);
   }  // Submit store.
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, sizeof(uint64_t), data_db);
   address_db->DecRef();
   mask_db->DecRef();
@@ -956,11 +956,11 @@
 
 // Vector store segment (unit stride). This stores the segments contiguously
 // in memory in a sequential manner.
-void VsSegment(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsSegment(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base_address = GetInstructionSource<uint64_t>(inst, 1);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 3) + 1;
   // Effective vector length multiplier.
@@ -980,10 +980,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, emul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -992,7 +992,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   uint64_t address = base_address;
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
@@ -1016,7 +1016,7 @@
         continue;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);
@@ -1036,7 +1036,7 @@
       count++;
     }
   }
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, element_width, data_db);
   // Release the dbs.
   address_db->DecRef();
@@ -1047,12 +1047,12 @@
 
 // Vector strided segment store. This stores each segment contiguously at
 // locations separated by the segment stride.
-void VsSegmentStrided(int element_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsSegmentStrided(int element_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base_address = GetInstructionSource<uint64_t>(inst, 1);
   int64_t segment_stride = GetInstructionSource<int64_t>(inst, 2);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 4) + 1;
   // Effective vector length multiplier.
@@ -1072,10 +1072,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, emul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1084,7 +1084,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   uint64_t segment_address = base_address;
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
@@ -1109,7 +1109,7 @@
         continue;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);
@@ -1130,7 +1130,7 @@
     }
     segment_address += segment_stride;
   }
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, element_width, data_db);
   // Release the dbs.
   address_db->DecRef();
@@ -1142,11 +1142,11 @@
 // Vector indexted segment store. This instruction stores each segment
 // contiguously at an address formed by adding the index value for that
 // segment (from the index vector source operand) to the base address.
-void VsSegmentIndexed(int index_width, const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VsSegmentIndexed(int index_width, const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int start = rv_vector->vstart();
   uint64_t base_address = GetInstructionSource<uint64_t>(inst, 1);
-  auto src_mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(3));
+  auto src_mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(3));
   auto src_masks = src_mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   int num_fields = GetInstructionSource<int32_t>(inst, 4) + 1;
   int element_width = rv_vector->selected_element_width();
@@ -1175,10 +1175,10 @@
       rv_vector->vector_register_byte_length() / element_width;
   int reg_mul = std::max(1, lmul / 8);
   // Set up data buffers.
-  auto *db_factory = inst->state()->db_factory();
-  auto *data_db = db_factory->Allocate(num_elements * element_width);
-  auto *address_db = db_factory->Allocate<uint64_t>(num_elements);
-  auto *mask_db = db_factory->Allocate<bool>(num_elements);
+  auto* db_factory = inst->state()->db_factory();
+  auto* data_db = db_factory->Allocate(num_elements * element_width);
+  auto* address_db = db_factory->Allocate<uint64_t>(num_elements);
+  auto* mask_db = db_factory->Allocate<bool>(num_elements);
   // Get spans for addresses and masks.
   auto addresses = address_db->Get<uint64_t>();
   auto masks = mask_db->Get<bool>();
@@ -1187,7 +1187,7 @@
   auto data4 = data_db->Get<uint32_t>();
   auto data8 = data_db->Get<uint64_t>();
 
-  auto *data_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* data_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   int count = 0;
   for (int segment = start; segment < num_segments; segment++) {
     // Masks are applied on a segment basis.
@@ -1230,7 +1230,7 @@
         continue;
       }
       // Write store data from register db to data db.
-      auto *reg_db = data_op->GetRegister(reg_no)->data_buffer();
+      auto* reg_db = data_op->GetRegister(reg_no)->data_buffer();
       switch (element_width) {
         case 1:
           data1[count] = reg_db->Get<uint8_t>(segment % num_elements_per_reg);
@@ -1251,7 +1251,7 @@
       count++;
     }
   }
-  auto *rv32_state = static_cast<RiscVState *>(inst->state());
+  auto* rv32_state = static_cast<RiscVState*>(inst->state());
   rv32_state->StoreMemory(inst, address_db, mask_db, element_width, data_db);
   // Release the dbs.
   address_db->DecRef();
diff --git a/riscv/riscv_vector_memory_instructions.h b/riscv/riscv_vector_memory_instructions.h
index 2de7f1d..0479693 100644
--- a/riscv/riscv_vector_memory_instructions.h
+++ b/riscv/riscv_vector_memory_instructions.h
@@ -31,7 +31,7 @@
 // The instruction takes 2 instruction source scalar operands: source operand 0
 // is the requested vector length, source operand 1 is the requested vector
 // configuration value. The destination operand is a scalar.
-void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction *inst);
+void Vsetvl(bool rd_zero, bool rs1_zero, const Instruction* inst);
 
 // Vector load semantic functions.
 // Load with constant stride, the parameter specifies the width of the vector
@@ -40,40 +40,40 @@
 // source operand 2 is the vector mask (either a vector register, or a
 // constant). Destination operand 0 is assigned to the child instruction and
 // is a vector register (group).
-void VlStrided(int element_width, const Instruction *inst);
+void VlStrided(int element_width, const Instruction* inst);
 // Load vector mask. This instruction takes 1 source and 1 destination operand.
 // The source operand is a scalar base address, the destination operand is the
 // vector register to write the mask to.
-void Vlm(const Instruction *inst);
+void Vlm(const Instruction* inst);
 // Indexed vector load (ordered and unordered). This instruction takes 3 source
 // and 1 destination operands. Source operand 0 is a scalar base address, source
 // operand 1 is a vector register (group) of indices, source operand 2 is the
 // vector mask. Destination operand 0 is assigned to the child instruction and
 // is a vector register (group).
-void VlIndexed(int index_width, const Instruction *inst);
+void VlIndexed(int index_width, const Instruction* inst);
 // Load vector register(s). Takes a parameter specifying how many registers to
 // load. This instruction takes 1 source and 1 destination operand. Source
 // operand 0 is a scalar base address. Destination operand 0 is assigned to the
 // child instruction and is a vector register (group).
-void VlRegister(int num_regs, int element_width_bytes, const Instruction *inst);
+void VlRegister(int num_regs, int element_width_bytes, const Instruction* inst);
 // Child instruction semantic functions for non-segment loads responsible for
 // writing load data back to the target register(s). It takes a single
 // destination operand. Destination operand 0 is a vector register (group).
-void VlChild(const Instruction *inst);
+void VlChild(const Instruction* inst);
 // Load segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 3 source operands and 1 destination
 // operand. Source operand 0 is a scalar base address, source operand 1 is
 // the vector mask, and source operand 2 is the number of fields - 1.
 // Destination operand 0 is assigned to the child instruction and is a vector
 // register (group).
-void VlSegment(int element_width, const Instruction *inst);
+void VlSegment(int element_width, const Instruction* inst);
 // Load segment strided. The function takes one parameter that specifies
 // the element width. The instruction takes 4 source operands and 1 destination
 // operand. Source operand 0 is a scalar base address, source operand 1 is a
 // scalar stride, source operand 2 is the vector mask, and source operand 3 is
 // the number of fields - 1. Destination operand 0 is assigned to the child
 // instruction and is a vector register (group).
-void VlSegmentStrided(int element_width, const Instruction *inst);
+void VlSegmentStrided(int element_width, const Instruction* inst);
 // Load segment indexed. The function takes one parameter that specifies
 // the index element width. The instruction takes 4 source operands and 1
 // destination operand. Source operand 0 is a scalar base address, source
@@ -81,11 +81,11 @@
 // vector mask, and source operand 3 is the number of fields - 1. Destination
 // operand 0 is assigned to the child instruction and is a vector register
 // (group).
-void VlSegmentIndexed(int index_width, const Instruction *inst);
+void VlSegmentIndexed(int index_width, const Instruction* inst);
 // Child instruction semantic functions for segment loads responsible for
 // writing load data back to the target register(s). It takes a single
 // destination operand. Destination operand 0 is a vector register (group).
-void VlSegmentChild(int element_width, const Instruction *inst);
+void VlSegmentChild(int element_width, const Instruction* inst);
 
 // Vector store semantic functions.
 
@@ -93,39 +93,39 @@
 // width. The instruction takes 4 source parameters. Source 0 is the store data
 // vector register (group), source 1 is the scalar base address, source 2 is the
 // stride, and source 3 is the vector mask.
-void VsStrided(int element_width, const Instruction *inst);
+void VsStrided(int element_width, const Instruction* inst);
 // Store vector mask. This instruction takes 2 source operands. Source 0 is the
 // vector mask register to be stored, the second is the scalar base address.
-void Vsm(const Instruction *inst);
+void Vsm(const Instruction* inst);
 // Store indexed. The function takes one parameter that specifies the element
 // width. The instruction takes 4 source parameters. Source 0 is the store data
 // vector register (group), source 1 is a vector (group) of indices, source 2 is
 // the stride, and source 3 is the vector mask.
-void VsIndexed(int index_width, const Instruction *inst);
+void VsIndexed(int index_width, const Instruction* inst);
 // Store vector register (group). This function takes one parameter that
 // specifies the number of registers to store. The instruction takes 2 source
 // operands. Source 0 is the source vector register (group), the second is the
 // scalar base address.
-void VsRegister(int num_regs, const Instruction *inst);
+void VsRegister(int num_regs, const Instruction* inst);
 // Store segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 4 source operands. Source operand 0
 // is the store data, source operand 1 is the scalar base address, source
 // operand 2 is the vector mask, and source operand 3 is the number of fields
 // - 1.
-void VsSegment(int element_width, const Instruction *inst);
+void VsSegment(int element_width, const Instruction* inst);
 // Store segment, unit stride. The function takes one parameter that specifies
 // the element width. The instruction takes 5 source operands. Source operand 0
 // is the store data, source operand 1 is the scalar base address, source
 // operand 2 is the segment stride, source operand 3 is the vector mask, and
 // source operand 4 is the number of fields
 // - 1.
-void VsSegmentStrided(int element_width, const Instruction *inst);
+void VsSegmentStrided(int element_width, const Instruction* inst);
 // Load segment indexed. The function takes one parameter that specifies
 // the index element width. The instruction takes 5 source operands. Source
 // operand 0 is the store data, source operand 1 is a scalar base address,
 // source operand 2 is a vector register (group) of indices, source operand 3 is
 // the vector mask, and source operand 4 is the number of fields - 1.
-void VsSegmentIndexed(int index_width, const Instruction *inst);
+void VsSegmentIndexed(int index_width, const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_opi_instructions.cc b/riscv/riscv_vector_opi_instructions.cc
index 5a9bdc9..692356e 100644
--- a/riscv/riscv_vector_opi_instructions.cc
+++ b/riscv/riscv_vector_opi_instructions.cc
@@ -21,7 +21,6 @@
 #include <type_traits>
 
 #include "absl/log/log.h"
-#include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv/riscv_register.h"
 #include "riscv/riscv_state.h"
@@ -44,8 +43,8 @@
 // Vector arithmetic operations.
 
 // Vector add.
-void Vadd(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vadd(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -72,8 +71,8 @@
 }
 
 // Vector subtract.
-void Vsub(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsub(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -100,8 +99,8 @@
 }
 
 // Vector reverse subtract.
-void Vrsub(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrsub(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -130,8 +129,8 @@
 // Vector logical operations.
 
 // Vector and.
-void Vand(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vand(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -158,8 +157,8 @@
 }
 
 // Vector or.
-void Vor(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vor(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -186,8 +185,8 @@
 }
 
 // Vector xor.
-void Vxor(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vxor(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -216,8 +215,8 @@
 // Vector shift operations.
 
 // Vector shift left logical.
-void Vsll(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsll(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -248,8 +247,8 @@
 }
 
 // Vector shift right logical.
-void Vsrl(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsrl(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -280,8 +279,8 @@
 }
 
 // Vector shift right arithmetic.
-void Vsra(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsra(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -315,8 +314,8 @@
 
 // Vector narrowing shift right logical. Source op 0 is shifted right
 // by source op 1 and the result is 1/2 the size of source op 0.
-void Vnsrl(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnsrl(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -349,8 +348,8 @@
 
 // Vector narrowing shift right arithmetic. Source op 0 is shifted right
 // by source op 1 and the result is 1/2 the size of source op 0.
-void Vnsra(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnsra(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // If the vector length multiplier (x8) is greater than 32, that means that
   // the source values (sew * 2) would exceed the available register group.
@@ -385,8 +384,8 @@
 }
 
 // Vector unsigned min.
-void Vminu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vminu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -417,8 +416,8 @@
 }
 
 // Vector signed min.
-void Vmin(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmin(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -448,8 +447,8 @@
 }
 
 // Vector unsigned max.
-void Vmaxu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmaxu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -480,8 +479,8 @@
 }
 
 // Vector signed max.
-void Vmax(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmax(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -511,8 +510,8 @@
 }
 
 // Set equal.
-void Vmseq(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmseq(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -541,8 +540,8 @@
 // Vector compare instructions.
 
 // Set not equal.
-void Vmsne(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsne(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -569,8 +568,8 @@
 }
 
 // Set less than unsigned.
-void Vmsltu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsltu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -597,8 +596,8 @@
 }
 
 // Set less than.
-void Vmslt(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmslt(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -625,8 +624,8 @@
 }
 
 // Set less than or equal unsigned.
-void Vmsleu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsleu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -653,8 +652,8 @@
 }
 
 // Set less than or equal.
-void Vmsle(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsle(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -681,8 +680,8 @@
 }
 
 // Set greater than unsigned.
-void Vmsgtu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsgtu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -709,8 +708,8 @@
 }
 
 // Set greater than.
-void Vmsgt(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsgt(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -737,8 +736,8 @@
 }
 
 // Saturated unsigned addition.
-void Vsaddu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsaddu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -792,7 +791,7 @@
 // Uses unsigned arithmetic for the addition to avoid signed overflow, which,
 // when compiled with --config=asan, will trigger an exception.
 template <typename T>
-inline T VsaddHelper(T vs2, T vs1, RiscVVectorState *rv_vector) {
+inline T VsaddHelper(T vs2, T vs1, RiscVVectorState* rv_vector) {
   using UT = typename std::make_unsigned<T>::type;
   UT uvs2 = static_cast<UT>(vs2);
   UT uvs1 = static_cast<UT>(vs1);
@@ -806,8 +805,8 @@
 }
 
 // Saturated signed addition.
-void Vsadd(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsadd(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -838,8 +837,8 @@
 }
 
 // Saturated unsigned subtract.
-void Vssubu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vssubu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -890,7 +889,7 @@
 }
 
 template <typename T>
-T VssubHelper(T vs2, T vs1, RiscVVectorState *rv_vector) {
+T VssubHelper(T vs2, T vs1, RiscVVectorState* rv_vector) {
   using UT = typename std::make_unsigned<T>::type;
   UT uvs2 = static_cast<UT>(vs2);
   UT uvs1 = static_cast<UT>(vs1);
@@ -904,8 +903,8 @@
 }
 
 // Saturated signed subtract.
-void Vssub(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vssub(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -936,8 +935,8 @@
 }
 
 // Add/Subtract with carry, carry generation.
-void Vadc(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vadc(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -971,8 +970,8 @@
 }
 
 // Add with carry - carry generation.
-void Vmadc(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmadc(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1024,8 +1023,8 @@
 }
 
 // Subtract with borrow.
-void Vsbc(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsbc(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1059,8 +1058,8 @@
 }
 
 // Subtract with borrow - borrow generation.
-void Vmsbc(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsbc(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1096,8 +1095,8 @@
 }
 
 // Vector merge.
-void Vmerge(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmerge(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1131,13 +1130,13 @@
 }
 
 // Vector move register(s).
-void Vmvr(int num_regs, Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmvr(int num_regs, Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vector_exception()) return;
 
-  auto *src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   if (src_op->size() < num_regs) {
     LOG(ERROR) << "Vmvr: source operand has fewer registers than requested";
     rv_vector->set_vector_exception();
@@ -1154,8 +1153,8 @@
   int vstart = rv_vector->vstart();
   int start_reg = vstart / num_elements_per_vector;
   for (int i = start_reg; i < num_regs; i++) {
-    auto *src_db = src_op->GetRegister(i)->data_buffer();
-    auto *dest_db = dest_op->AllocateDataBuffer(i);
+    auto* src_db = src_op->GetRegister(i)->data_buffer();
+    auto* dest_db = dest_op->AllocateDataBuffer(i);
     std::memcpy(dest_db->raw_ptr(), src_db->raw_ptr(),
                 dest_db->size<uint8_t>());
     dest_db->Submit();
@@ -1165,7 +1164,7 @@
 
 // Templated helper function for shift right with rounding.
 template <typename T>
-T VssrHelper(RiscVVectorState *rv_vector, T vs2, T vs1) {
+T VssrHelper(RiscVVectorState* rv_vector, T vs2, T vs1) {
   using UT = typename MakeUnsigned<T>::type;
   int rm = rv_vector->vxrm();
   int max_shift = (sizeof(T) << 3) - 1;
@@ -1183,8 +1182,8 @@
 }
 
 // Logical shift right with rounding.
-void Vssrl(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vssrl(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1215,8 +1214,8 @@
 }
 
 // Arithmetic shift right with rounding.
-void Vssra(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vssra(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -1248,7 +1247,7 @@
 
 // Templated helper function for shift right with rounding and saturation.
 template <typename DT, typename WT, typename T>
-T VnclipHelper(RiscVVectorState *rv_vector, WT vs2, T vs1) {
+T VnclipHelper(RiscVVectorState* rv_vector, WT vs2, T vs1) {
   using WUT = typename std::make_unsigned<WT>::type;
   int rm = rv_vector->vxrm();
   int max_shift = (sizeof(WT) << 3) - 1;
@@ -1276,8 +1275,8 @@
 
 // Arithmetic shift right and narrowing from 2*sew to sew with rounding and
 // signed saturation.
-void Vnclip(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnclip(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int lmul8 = rv_vector->vector_length_multiplier();
   // This is a narrowing operation and sew is that of the narrow data type.
   // Thus if lmul > 32, then emul for the wider data type is illegal.
@@ -1314,8 +1313,8 @@
 
 // Logical shift right and narrowing from 2*sew to sew with rounding and
 // unsigned saturation.
-void Vnclipu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnclipu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int lmul8 = rv_vector->vector_length_multiplier();
   // This is a narrowing operation and sew is that of the narrow data type.
   // Thus if lmul > 32, then emul for the wider data type is illegal.
@@ -1356,7 +1355,7 @@
 // Perform a signed multiply from T to wider int type. Shift that result
 // right by sizeof(T) * 8 - 1 and round. Saturate if needed to fit into T.
 template <typename T>
-T VsmulHelper(RiscVVectorState *rv_vector, T vs2, T vs1) {
+T VsmulHelper(RiscVVectorState* rv_vector, T vs2, T vs1) {
   using WT = typename WideType<T>::type;
   WT vd_w;
   WT vs2_w = static_cast<WT>(vs2);
@@ -1375,8 +1374,8 @@
 }
 
 // Vector fractional multiply with rounding and saturation.
-void Vsmul(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsmul(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
diff --git a/riscv/riscv_vector_opi_instructions.h b/riscv/riscv_vector_opi_instructions.h
index 622786d..e9a7461 100644
--- a/riscv/riscv_vector_opi_instructions.h
+++ b/riscv/riscv_vector_opi_instructions.h
@@ -34,200 +34,200 @@
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vadd(Instruction *inst);
+void Vadd(Instruction* inst);
 // Element wide vector subtract. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector) or rs1 (scalar). Source 2 is a vector
 // mask operand.
-void Vsub(Instruction *inst);
+void Vsub(Instruction* inst);
 // Element wide vector reverse subtract. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vrsub(Instruction *inst);
+void Vrsub(Instruction* inst);
 // Element wide bitwise and. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vand(Instruction *inst);
+void Vand(Instruction* inst);
 // Element wide bitwise or. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vor(Instruction *inst);
+void Vor(Instruction* inst);
 // Element wide bitwise xor. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vxor(Instruction *inst);
+void Vxor(Instruction* inst);
 // Element wide logical left shift. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsll(Instruction *inst);
+void Vsll(Instruction* inst);
 // Element wide logical right shift. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vsrl(Instruction *inst);
+void Vsrl(Instruction* inst);
 // Element wide arithmetic right shift. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vsra(Instruction *inst);
+void Vsra(Instruction* inst);
 // Element wide narrowing logical right shift. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnsrl(Instruction *inst);
+void Vnsrl(Instruction* inst);
 // Element wide narrowing arithmetic right shift. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnsra(Instruction *inst);
+void Vnsra(Instruction* inst);
 // Vector signed min (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmin(Instruction *inst);
+void Vmin(Instruction* inst);
 // Vector unsigned min (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vminu(Instruction *inst);
+void Vminu(Instruction* inst);
 // Vector signed max (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmax(Instruction *inst);
+void Vmax(Instruction* inst);
 // Vector unsigned max (pairwise). This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vmaxu(Instruction *inst);
+void Vmaxu(Instruction* inst);
 // Vector mask set equal. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmseq(Instruction *inst);
+void Vmseq(Instruction* inst);
 // Vector mask set not equal.  This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsne(Instruction *inst);
+void Vmsne(Instruction* inst);
 // Vector mask set less than unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vmsltu(Instruction *inst);
+void Vmsltu(Instruction* inst);
 // Vector mask set less than signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector mask
 // operand.
-void Vmslt(Instruction *inst);
+void Vmslt(Instruction* inst);
 // Vector mask set less or equal unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector mask
 // operand.
-void Vmsleu(Instruction *inst);
+void Vmsleu(Instruction* inst);
 // Vector mask set less or equal signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vmsle(Instruction *inst);
+void Vmsle(Instruction* inst);
 // Vector mask set greater than unsigned. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsgtu(Instruction *inst);
+void Vmsgtu(Instruction* inst);
 // Vector mask set greater than signed. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vmsgt(Instruction *inst);
+void Vmsgt(Instruction* inst);
 // Vector saturating unsigned add. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsaddu(Instruction *inst);
+void Vsaddu(Instruction* inst);
 // Vector saturating signed add. This instruction takes three source operands
 // and a vector destination operand. Source 0 is the vs2 vector source. Source 1
 // is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector
 // mask operand.
-void Vsadd(Instruction *inst);
+void Vsadd(Instruction* inst);
 // Vector saturating unsigned subtrract. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand.
-void Vssubu(Instruction *inst);
+void Vssubu(Instruction* inst);
 // Vector saturating subtract. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand.
-void Vssub(Instruction *inst);
+void Vssub(Instruction* inst);
 // Vector add with carry. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand that contains the carry in values.
-void Vadc(Instruction *inst);
+void Vadc(Instruction* inst);
 // Vector add with carry - carry generate. This instruction takes three source
 // operands and a vector destination operand. Source 0 is the vs2 vector source.
 // Source 1 is either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a
 // vector mask operand that contains the carry in values. The output of this
 // instruction is the carry outs of each element wise addition. It is stored in
 // the format of the vector flags.
-void Vmadc(Instruction *inst);
+void Vmadc(Instruction* inst);
 // Vector subtract with borrow. This instruction takes three source operands and
 // a vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand that contains the borrow values.
-void Vsbc(Instruction *inst);
+void Vsbc(Instruction* inst);
 // Vector subtract with borrow - borrow generate. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand that contains the borrow values. The output
 // of this instruction is the borrow outs of each element wise subtraction. It
 // is stored in the format of the vector flags.
-void Vmsbc(Instruction *inst);
+void Vmsbc(Instruction* inst);
 // Vector pairwise merge. This instruction takes three source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. Source 1 is
 // either vs1 (vector), rs1 (scalar), or an immediate. Source 2 is a vector mask
 // operand. This semantic function also captures the functionality of vmv.vv,
 // vmv.vx, and vmv.vi, in which case vs2 is register group v0, and the mask
 // is all ones.
-void Vmerge(Instruction *inst);
+void Vmerge(Instruction* inst);
 // Vector register move. This instruction takes one source operands and a
 // vector destination operand. Source 0 is the vs2 vector source. The num_regs
 // value is part of the opcode and should be bound to the semantic function at
 // decode.
-void Vmvr(int num_regs, Instruction *inst);
+void Vmvr(int num_regs, Instruction* inst);
 // Vector logical right shift with rounding. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vssrl(Instruction *inst);
+void Vssrl(Instruction* inst);
 // Vector arithmetic right shift with rounding. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vssra(Instruction *inst);
+void Vssra(Instruction* inst);
 // Vector logical right shift with rounding and (unsigned) saturation from SEW *
 // 2 to SEW wide elements. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnclipu(Instruction *inst);
+void Vnclipu(Instruction* inst);
 // Vector arithmetic right shift with rounding and (signed) saturation from SEW
 // * 2 to SEW wide elements. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector), rs1 (scalar), or an immediate.
 // Source 2 is a vector mask operand.
-void Vnclip(Instruction *inst);
+void Vnclip(Instruction* inst);
 // Vector fractional multiply. This instruction takes three
 // source operands and a vector destination operand. Source 0 is the vs2 vector
 // source. Source 1 is either vs1 (vector) or rs1 (scalar). Source 2 is a vector
 // mask operand.
-void Vsmul(Instruction *inst);
+void Vsmul(Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_opm_instructions.cc b/riscv/riscv_vector_opm_instructions.cc
index 32c1217..21e3157 100644
--- a/riscv/riscv_vector_opm_instructions.cc
+++ b/riscv/riscv_vector_opm_instructions.cc
@@ -17,7 +17,6 @@
 #include <cstdint>
 #include <functional>
 #include <limits>
-#include <optional>
 #include <type_traits>
 
 #include "absl/log/log.h"
@@ -34,7 +33,7 @@
 
 // Helper function used to factor out some code from Vaadd* instructions.
 template <typename T>
-inline T VaaddHelper(RiscVVectorState *rv_vector, T vs2, T vs1) {
+inline T VaaddHelper(RiscVVectorState* rv_vector, T vs2, T vs1) {
   // Perform the addition using a wider type, then shift and round.
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
@@ -45,8 +44,8 @@
 
 // Average unsigned add. The two sources are added, then shifted right by one
 // and rounded.
-void Vaaddu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vaaddu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -78,8 +77,8 @@
 
 // Average signed add. The two sources are added, then shifted right by one and
 // rounded.
-void Vaadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vaadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -112,7 +111,7 @@
 // Helper function for Vasub* instructions. Subract using a wider type, then
 // round.
 template <typename T>
-inline T VasubHelper(RiscVVectorState *rv_vector, T vs2, T vs1) {
+inline T VasubHelper(RiscVVectorState* rv_vector, T vs2, T vs1) {
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
   WT vs1_w = static_cast<WT>(vs1);
@@ -121,8 +120,8 @@
 }
 
 // Averaging unsigned subtract - subtract then shift right by 1 and round.
-void Vasubu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vasubu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -153,8 +152,8 @@
 }
 
 // Averaging signed subtract. Subtract then shift right by 1 and round.
-void Vasub(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vasub(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -188,19 +187,19 @@
 // is used by the following bitwise mask manipulation instruction semantic
 // functions.
 static inline void BitwiseMaskBinaryOp(
-    RiscVVectorState *rv_vector, const Instruction *inst,
+    RiscVVectorState* rv_vector, const Instruction* inst,
     std::function<uint8_t(uint8_t, uint8_t)> op) {
   if (rv_vector->vector_exception()) return;
   int vstart = rv_vector->vstart();
   int vlen = rv_vector->vector_length();
   // Get spans for vector source and destination registers.
-  auto *vs2_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto* vs2_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto vs2_span = vs2_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *vs1_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* vs1_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto vs1_span = vs1_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *vd_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *vd_db = vd_op->CopyDataBuffer();
+  auto* vd_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* vd_db = vd_op->CopyDataBuffer();
   auto vd_span = vd_db->Get<uint8_t>();
   // Compute start and end locations.
   int start_byte = vstart / 8;
@@ -226,51 +225,51 @@
 }
 
 // Bitwise vector mask instructions. The operation is clear by their name.
-void Vmandnot(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmandnot(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 & ~vs1;
   });
 }
 
-void Vmand(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmand(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 & vs1;
   });
 }
-void Vmor(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmor(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 | vs1;
   });
 }
-void Vmxor(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmxor(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 ^ vs1;
   });
 }
-void Vmornot(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmornot(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return vs2 | ~vs1;
   });
 }
-void Vmnand(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmnand(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 & vs1);
   });
 }
-void Vmnor(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmnor(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 | vs1);
   });
 }
-void Vmxnor(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmxnor(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   BitwiseMaskBinaryOp(rv_vector, inst, [](uint8_t vs2, uint8_t vs1) -> uint8_t {
     return ~(vs2 ^ vs1);
   });
@@ -278,8 +277,8 @@
 
 // Vector unsigned divide. Note, just like the scalar divide instruction, a
 // divide by zero does not cause an exception, instead it returns all 1s.
-void Vdivu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vdivu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -315,8 +314,8 @@
 
 // Signed divide. Divide by 0 returns all 1s. If -1 is divided by the largest
 // magnitude negative number, it returns that negative number.
-void Vdiv(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vdiv(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -363,8 +362,8 @@
 }
 
 // Unsigned remainder. If the denominator is 0, it returns the enumerator.
-void Vremu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vremu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -399,8 +398,8 @@
 }
 
 // Signed remainder. If the denominator is 0, it returns the enumerator.
-void Vrem(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrem(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -447,8 +446,8 @@
 }
 
 // Multiply high, unsigned.
-void Vmulhu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmulhu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -480,8 +479,8 @@
 
 // Signed multiply. Note, that signed and unsigned multiply operations have the
 // same result for the low half of the product.
-void Vmul(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmul(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -533,8 +532,8 @@
 }
 
 // Multiply signed unsigned and return the high half.
-void Vmulhsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmulhsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -565,8 +564,8 @@
 }
 
 // Signed multiply, return high half.
-void Vmulh(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmulh(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -597,8 +596,8 @@
 }
 
 // Multiply-add.
-void Vmadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -636,8 +635,8 @@
 }
 
 // Negated multiply and add.
-void Vnmsub(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnmsub(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -674,8 +673,8 @@
 }
 
 // Multiply add overwriting the sum.
-void Vmacc(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmacc(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -712,8 +711,8 @@
 }
 
 // Negated multiply add, overwriting sum.
-void Vnmsac(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vnmsac(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -750,8 +749,8 @@
 }
 
 // Widening unsigned add.
-void Vwaddu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwaddu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -777,8 +776,8 @@
 }
 
 // Widening unsigned subtract.
-void Vwsubu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwsubu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -804,8 +803,8 @@
 }
 
 // Widening signed add.
-void Vwadd(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwadd(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -844,8 +843,8 @@
 }
 
 // Widening signed subtract.
-void Vwsub(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwsub(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -883,8 +882,8 @@
 }
 
 // Widening unsigned add with wide source.
-void Vwadduw(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwadduw(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -917,8 +916,8 @@
 }
 
 // Widening unsigned subtract with wide source.
-void Vwsubuw(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwsubuw(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -951,8 +950,8 @@
 }
 
 // Widening signed add with wide source.
-void Vwaddw(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwaddw(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -985,8 +984,8 @@
 }
 
 // Widening signed subtract with wide source.
-void Vwsubw(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwsubw(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1029,8 +1028,8 @@
 }
 
 // Unsigned widening multiply.
-void Vwmulu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmulu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1076,8 +1075,8 @@
 }
 
 // Widening multiply signed-unsigned.
-void Vwmulsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmulsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1110,8 +1109,8 @@
 }
 
 // Widening signed multiply.
-void Vwmul(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmul(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1155,8 +1154,8 @@
 }
 
 // Unsigned widening multiply and add.
-void Vwmaccu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmaccu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1192,8 +1191,8 @@
 }
 
 // Widening signed multiply and add.
-void Vwmacc(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmacc(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1226,8 +1225,8 @@
 }
 
 // Widening unsigned-signed multiply and add.
-void Vwmaccus(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmaccus(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
@@ -1262,8 +1261,8 @@
 }
 
 // Widening signed-unsigned multiply and add.
-void Vwmaccsu(const Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwmaccsu(const Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   // LMUL8 cannot be 64.
   if (rv_vector->vector_length_multiplier() > 32) {
diff --git a/riscv/riscv_vector_opm_instructions.h b/riscv/riscv_vector_opm_instructions.h
index 7a3844f..a9f8a87 100644
--- a/riscv/riscv_vector_opm_instructions.h
+++ b/riscv/riscv_vector_opm_instructions.h
@@ -27,151 +27,151 @@
 // Integer average unsigned add. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vaaddu(const Instruction *inst);
+void Vaaddu(const Instruction* inst);
 // Integer average signed add. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vaadd(const Instruction *inst);
+void Vaadd(const Instruction* inst);
 // Integer average unsigned subtract. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vasubu(const Instruction *inst);
+void Vasubu(const Instruction* inst);
 // Integer average signed subtract. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vasub(const Instruction *inst);
+void Vasub(const Instruction* inst);
 // The following instructions are vector mask logical operations. Each takes
 // two source operands, vs2 and vs1 vector registers, and one destination
 // operand, vd vector destination register.
-void Vmandnot(const Instruction *inst);
-void Vmand(const Instruction *inst);
-void Vmor(const Instruction *inst);
-void Vmxor(const Instruction *inst);
-void Vmornot(const Instruction *inst);
-void Vmnand(const Instruction *inst);
-void Vmnor(const Instruction *inst);
-void Vmxnor(const Instruction *inst);
+void Vmandnot(const Instruction* inst);
+void Vmand(const Instruction* inst);
+void Vmor(const Instruction* inst);
+void Vmxor(const Instruction* inst);
+void Vmornot(const Instruction* inst);
+void Vmnand(const Instruction* inst);
+void Vmnor(const Instruction* inst);
+void Vmxnor(const Instruction* inst);
 // Integer unsigned division. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vdivu(const Instruction *inst);
+void Vdivu(const Instruction* inst);
 // Integer signed division. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vdiv(const Instruction *inst);
+void Vdiv(const Instruction* inst);
 // Integer unsigned remainder. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vremu(const Instruction *inst);
+void Vremu(const Instruction* inst);
 // Integer signed remainder. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vrem(const Instruction *inst);
+void Vrem(const Instruction* inst);
 // Integer unsigned multiply high. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmulhu(const Instruction *inst);
+void Vmulhu(const Instruction* inst);
 // Integer signed multiply. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmul(const Instruction *inst);
+void Vmul(const Instruction* inst);
 // Integer signed-unsigned multiply high. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vmulhsu(const Instruction *inst);
+void Vmulhsu(const Instruction* inst);
 // Integer signed multiply high. This instruction takes 3 source operands and
 // one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vmulh(const Instruction *inst);
+void Vmulh(const Instruction* inst);
 // Integer multiply add (vs1 * vd) + vs2. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vmadd(const Instruction *inst);
+void Vmadd(const Instruction* inst);
 // Integer multiply subtract -(vs1 * vd) + vs2. This instruction takes 4
 // source operands and one destination operand. Source 0 is vs2, source 1 is vs1
 // (or rs1), source 2 is Vd as a source operand, and source 4 is vector mask.
 // The destination operand is the Vd register group.
-void Vnmsub(const Instruction *inst);
+void Vnmsub(const Instruction* inst);
 // Integer multiply add (vs1 * vs2) + vd. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vmacc(const Instruction *inst);
+void Vmacc(const Instruction* inst);
 // Integer multiply subtract -(vs1 * vs2) + vd. This instruction takes 4 source
 // operands and one destination operand. Source 0 is vs2, source 1 is vs1 (or
 // rs1), source 2 is Vd as a source operand, and source 4 is vector mask. The
 // destination operand is the Vd register group.
-void Vnmsac(const Instruction *inst);
+void Vnmsac(const Instruction* inst);
 // Integer widening unsigned addition. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwaddu(const Instruction *inst);
+void Vwaddu(const Instruction* inst);
 // Integer widening signed addition. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwadd(const Instruction *inst);
+void Vwadd(const Instruction* inst);
 // Integer widening unsigned subtraction. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwsubu(const Instruction *inst);
+void Vwsubu(const Instruction* inst);
 // Integer widening signed subtraction. This instruction takes 3 source operands
 // and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and source 2
 // is vector mask. The destination operand is a vector register group.
-void Vwsub(const Instruction *inst);
+void Vwsub(const Instruction* inst);
 // Integer widening unsigned addition with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwadduw(const Instruction *inst);
+void Vwadduw(const Instruction* inst);
 // Integer widening signed addition with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwaddw(const Instruction *inst);
+void Vwaddw(const Instruction* inst);
 // Integer widening unsigned subtraction with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwsubuw(const Instruction *inst);
+void Vwsubuw(const Instruction* inst);
 // Integer widening signed subtraction with one wide source operand. This
 // instruction takes 3 source operands and one destination. Source 0 is vs2
 // (wide), source 1 is vs1 (or rs1), and source 2 is vector mask. The
 // destination operand is a vector register group.
-void Vwsubw(const Instruction *inst);
+void Vwsubw(const Instruction* inst);
 // Integer widening unsigned multiplication. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwmulu(const Instruction *inst);
+void Vwmulu(const Instruction* inst);
 // Integer widening signed by unsigned multiplication. This instruction takes 3
 // source operands and one destination. Source 0 is vs2, source 1 is vs1 (or
 // rs1), and source 2 is vector mask. The destination operand is a vector
 // register group.
-void Vwmulsu(const Instruction *inst);
+void Vwmulsu(const Instruction* inst);
 // Integer widening signed multiplication. This instruction takes 3 source
 // operands and one destination. Source 0 is vs2, source 1 is vs1 (or rs1), and
 // source 2 is vector mask. The destination operand is a vector register group.
-void Vwmul(const Instruction *inst);
+void Vwmul(const Instruction* inst);
 // Integer widening signed multiply and add (vs2 * vs1) + vd. This instruction
 // takes 4 source operands and one destination operand. Source 0 is vs2, source
 // 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source 4 is vector
 // mask. The destination operand is the Vd register group.
-void Vwmaccu(const Instruction *inst);
+void Vwmaccu(const Instruction* inst);
 // Integer widening unsigned multiply and add (vs2 * vs1) + vd. This instruction
 // takes 4 source operands and one destination operand. Source 0 is vs2, source
 // 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source 4 is vector
 // mask. The destination operand is the Vd register group.
-void Vwmacc(const Instruction *inst);
+void Vwmacc(const Instruction* inst);
 // Integer widening unsigned by signed multiply and add (vs2 * vs1) + vd. This
 // instruction takes 4 source operands and one destination operand. Source 0 is
 // vs2, source 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source
 // 4 is vector mask. The destination operand is the Vd register group.
-void Vwmaccus(const Instruction *inst);
+void Vwmaccus(const Instruction* inst);
 // Integer widening signed by unsigned multiply and add (vs2 * vs1) + vd. This
 // instruction takes 4 source operands and one destination operand. Source 0 is
 // vs2, source 1 is vs1 (or rs1), source 2 is Vd as a source operand, and source
 // 4 is vector mask. The destination operand is the Vd register group.
-void Vwmaccsu(const Instruction *inst);
+void Vwmaccsu(const Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_permute_instructions.cc b/riscv/riscv_vector_permute_instructions.cc
index bf993d7..090fb5a 100644
--- a/riscv/riscv_vector_permute_instructions.cc
+++ b/riscv/riscv_vector_permute_instructions.cc
@@ -32,7 +32,7 @@
 
 // This helper function handles the vector gather operations.
 template <typename Vd, typename Vs2, typename Vs1>
-void VrgatherHelper(RiscVVectorState *rv_vector, Instruction *inst) {
+void VrgatherHelper(RiscVVectorState* rv_vector, Instruction* inst) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
@@ -46,8 +46,8 @@
   }
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -57,7 +57,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -66,13 +66,13 @@
   int item_index = vector_index % elements_per_vector;
   // Determine if it's vector-vector or vector-scalar.
   bool vector_scalar = inst->Source(1)->shape()[0] == 1;
-  auto src0_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src0_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   int max_index = src0_op->size() * elements_per_vector;
   // Iterate over the number of registers to write.
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -107,8 +107,8 @@
 }
 
 // Vector register gather.
-void Vrgather(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrgather(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -127,8 +127,8 @@
 }
 
 // Vector register gather with 16 bit indices.
-void Vrgatherei16(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vrgatherei16(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -148,15 +148,15 @@
 
 // This helper function handles the vector slide up/down instructions.
 template <typename Vd>
-void VSlideHelper(RiscVVectorState *rv_vector, Instruction *inst, int offset) {
+void VSlideHelper(RiscVVectorState* rv_vector, Instruction* inst, int offset) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -166,7 +166,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -177,7 +177,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -205,9 +205,9 @@
   rv_vector->clear_vstart();
 }
 
-void Vslideup(Instruction *inst) {
+void Vslideup(Instruction* inst) {
   using ValueType = RV32Register::ValueType;
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto offset = generic::GetInstructionSource<ValueType>(inst, 1, 0);
   int int_offset = static_cast<int>(offset);
@@ -229,9 +229,9 @@
   }
 }
 
-void Vslidedown(Instruction *inst) {
+void Vslidedown(Instruction* inst) {
   using ValueType = RV32Register::ValueType;
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   auto offset = generic::GetInstructionSource<ValueType>(inst, 1, 0);
   // Slide down amount is negative.
@@ -254,15 +254,15 @@
 
 // This helper function handles the vector slide up/down 1 instructions.
 template <typename Vd>
-void VSlide1Helper(RiscVVectorState *rv_vector, Instruction *inst, int offset) {
+void VSlide1Helper(RiscVVectorState* rv_vector, Instruction* inst, int offset) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -272,7 +272,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(2));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(2));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -284,7 +284,7 @@
   for (int reg = start_reg; (reg < max_regs) && (vector_index < num_elements);
        reg++) {
     // Allocate data buffer for the new register data.
-    auto *dest_db = dest_op->CopyDataBuffer(reg);
+    auto* dest_db = dest_op->CopyDataBuffer(reg);
     auto dest_span = dest_db->Get<Vd>();
     // Write data into register subject to masking.
     int element_count = std::min(elements_per_vector, num_elements);
@@ -312,8 +312,8 @@
   rv_vector->clear_vstart();
 }
 
-void Vslide1up(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vslide1up(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -331,8 +331,8 @@
   }
 }
 
-void Vslide1down(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vslide1down(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -350,8 +350,8 @@
   }
 }
 
-void Vfslide1up(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfslide1up(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -365,8 +365,8 @@
   }
 }
 
-void Vfslide1down(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfslide1down(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -381,15 +381,15 @@
 }
 
 template <typename Vd>
-void VCompressHelper(RiscVVectorState *rv_vector, Instruction *inst) {
+void VCompressHelper(RiscVVectorState* rv_vector, Instruction* inst) {
   if (rv_vector->vector_exception()) return;
   int num_elements = rv_vector->vector_length();
   int elements_per_vector =
       rv_vector->vector_register_byte_length() / sizeof(Vd);
   int max_regs = std::max(
       1, (num_elements + elements_per_vector - 1) / elements_per_vector);
-  auto *dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
+  auto* dest_op =
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
   // Verify that there are enough registers in the destination operand.
   if (dest_op->size() < max_regs) {
     rv_vector->set_vector_exception();
@@ -399,7 +399,7 @@
     return;
   }
   // Get the vector mask.
-  auto *mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto* mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   // Get the vector start element index and compute the where to start
   // the operation.
@@ -407,7 +407,7 @@
   int dest_index = 0;
   int prev_reg = -1;
   absl::Span<Vd> dest_span;
-  generic::DataBuffer *dest_db = nullptr;
+  generic::DataBuffer* dest_db = nullptr;
   // Iterate over the input elements.
   for (int i = vector_index; i < num_elements; i++) {
     // Get mask value.
@@ -435,8 +435,8 @@
   rv_vector->clear_vstart();
 }
 
-void Vcompress(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vcompress(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
diff --git a/riscv/riscv_vector_permute_instructions.h b/riscv/riscv_vector_permute_instructions.h
index 4aa1577..7807e33 100644
--- a/riscv/riscv_vector_permute_instructions.h
+++ b/riscv/riscv_vector_permute_instructions.h
@@ -27,60 +27,60 @@
 // operands and one destination operand. Source 0 is the vector from which
 // elements are gathered, source 1 is the index vector, and source 2 is the
 // vector mask register. The destination operand is the target vector register.
-void Vrgather(Instruction *inst);
+void Vrgather(Instruction* inst);
 // Vector register gather instruction with 16 bit indices. This instruction
 // takes three source operands and one destination operand. Source 0 is the
 // vector from which elements are gathered, source 1 is the index vector, and
 // source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vrgatherei16(Instruction *inst);
+void Vrgatherei16(Instruction* inst);
 // Vector slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up. Source 1 is a scalar register or
 // immediate that specifies the number of 'entries' by which source 0 values
 // are slid up. Source 2 is the vector mask register. The destination operand
 // is the target vector register.
-void Vslideup(Instruction *inst);
+void Vslideup(Instruction* inst);
 // Vector slide down instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' down. Source 1 is a scalar register or
 // immediate that specifies the number of 'entries' by which source 0 values
 // are slid down. Source 2 is the vector mask register. The destination operand
 // is the target vector register.
-void Vslidedown(Instruction *inst);
+void Vslidedown(Instruction* inst);
 // Vector slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up by 1. Source 1 is a scalar register or
 // immediate that specifies the value written into the 'empty' slot. Source 2 is
 // the vector mask register. The destination operand is the target vector
 // register.
-void Vslide1up(Instruction *inst);
+void Vslide1up(Instruction* inst);
 // Vector slide down instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' down. Source 1 is a scalar register or
 // immediate that specifies the value written into the 'empty' slot. Source 2 is
 // the vector mask register. The destination operand is the target vector
 // register.
-void Vslide1down(Instruction *inst);
+void Vslide1down(Instruction* inst);
 // Vector fp slide up instruction. This instruction takes three source operands
 // and one destination operand. Source 0 is the vector source register that
 // contains the values that are 'slid' up by 1. Source 1 is a floating point
 // register or immediate that specifies the value written into the 'empty' slot.
 // Source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vfslide1up(Instruction *inst);
+void Vfslide1up(Instruction* inst);
 // Vector fp slide down instruction. This instruction takes three source
 // operands and one destination operand. Source 0 is the vector source register
 // that contains the values that are 'slid' down. Source 1 is a floating point
 // register or immediate that specifies the value written into the 'empty' slot.
 // Source 2 is the vector mask register. The destination operand is the target
 // vector register.
-void Vfslide1down(Instruction *inst);
+void Vfslide1down(Instruction* inst);
 // Vector compress instruction. This instruction takes two source operands and
 // one destination operand. Source 0 is the source value vector register. Source
 // 1 is a mask register, with specifies which elements of source 0 should be
 // selected and packed into the destination register.
-void Vcompress(Instruction *inst);
+void Vcompress(Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_reduction_instructions.cc b/riscv/riscv_vector_reduction_instructions.cc
index 787034c..53d099f 100644
--- a/riscv/riscv_vector_reduction_instructions.cc
+++ b/riscv/riscv_vector_reduction_instructions.cc
@@ -15,8 +15,10 @@
 #include "riscv/riscv_vector_reduction_instructions.h"
 
 #include <algorithm>
+#include <cstdint>
 
 #include "absl/log/log.h"
+#include "riscv/riscv_state.h"
 #include "riscv/riscv_vector_instruction_helpers.h"
 
 namespace mpact {
@@ -24,8 +26,8 @@
 namespace riscv {
 
 // Sum reduction.
-void Vredsum(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredsum(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -55,8 +57,8 @@
 }
 
 // And reduction.
-void Vredand(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredand(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -86,8 +88,8 @@
 }
 
 // Or reduction.
-void Vredor(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredor(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -117,8 +119,8 @@
 }
 
 // Xor reduction.
-void Vredxor(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredxor(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -148,8 +150,8 @@
 }
 
 // Unsigned min reduction.
-void Vredminu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredminu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -183,8 +185,8 @@
 }
 
 // Signed min reduction.
-void Vredmin(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredmin(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -217,8 +219,8 @@
 }
 
 // Unsigned max reduction.
-void Vredmaxu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredmaxu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -252,8 +254,8 @@
 }
 
 // Signed max reduction.
-void Vredmax(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vredmax(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -286,8 +288,8 @@
 }
 
 // Unsigned widening (SEW->SEW * 2) reduction.
-void Vwredsumu(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwredsumu(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
@@ -316,8 +318,8 @@
 }
 
 // Signed widening (SEW->SEW * 2) reduction.
-void Vwredsum(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vwredsum(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 1:
diff --git a/riscv/riscv_vector_reduction_instructions.h b/riscv/riscv_vector_reduction_instructions.h
index 4531e63..f84d0ad 100644
--- a/riscv/riscv_vector_reduction_instructions.h
+++ b/riscv/riscv_vector_reduction_instructions.h
@@ -31,25 +31,25 @@
 // result is written to the 0 element of destination operand vd.
 
 // Vector sum reduction.
-void Vredsum(Instruction *inst);
+void Vredsum(Instruction* inst);
 // Vector and reduction.
-void Vredand(Instruction *inst);
+void Vredand(Instruction* inst);
 // Vector or reduction.
-void Vredor(Instruction *inst);
+void Vredor(Instruction* inst);
 // Vector xor reduction.
-void Vredxor(Instruction *inst);
+void Vredxor(Instruction* inst);
 // Vector unsigned min reduction.
-void Vredminu(Instruction *inst);
+void Vredminu(Instruction* inst);
 // Vector signed min reduction.
-void Vredmin(Instruction *inst);
+void Vredmin(Instruction* inst);
 // Vector unsigned max reduction.
-void Vredmaxu(Instruction *inst);
+void Vredmaxu(Instruction* inst);
 // Vector signed max reduction.
-void Vredmax(Instruction *inst);
+void Vredmax(Instruction* inst);
 // Vector unsigned widening sum reduction. The result is 2 * SEW.
-void Vwredsumu(Instruction *inst);
+void Vwredsumu(Instruction* inst);
 // vector signed widening sum reduction. The result is 2 * SEW.
-void Vwredsum(Instruction *inst);
+void Vwredsum(Instruction* inst);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_vector_unary_instructions.cc b/riscv/riscv_vector_unary_instructions.cc
index 318ad24..9183614 100644
--- a/riscv/riscv_vector_unary_instructions.cc
+++ b/riscv/riscv_vector_unary_instructions.cc
@@ -36,12 +36,12 @@
                                           int64_t>::type;
 
 // Move scalar to vector register.
-void VmvToScalar(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VmvToScalar(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
-  auto *dest_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* dest_db = inst->Destination(0)->AllocateDataBuffer();
   SignedXregType value;
   switch (sew) {
     case 1:
@@ -69,12 +69,12 @@
   dest_db->Submit();
 }
 
-void VmvFromScalar(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void VmvFromScalar(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) return;
   if (rv_vector->vector_length() == 0) return;
   int sew = rv_vector->selected_element_width();
-  auto *dest_db = inst->Destination(0)->CopyDataBuffer();
+  auto* dest_db = inst->Destination(0)->CopyDataBuffer();
   switch (sew) {
     case 1:
       dest_db->Set<int8_t>(0, generic::GetInstructionSource<int8_t>(inst, 0));
@@ -98,19 +98,19 @@
 
 // Population count of vector mask register. The value is written to a scalar
 // register.
-void Vcpop(Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = rv_state->rv_vector();
+void Vcpop(Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = rv_state->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *dest_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* dest_db = inst->Destination(0)->AllocateDataBuffer();
   uint64_t count = 0;
   for (int i = 0; i < vlen; i++) {
     int index = i >> 3;
@@ -136,18 +136,18 @@
 
 // Find first set of vector mask register. The value is written to a scalar
 // register.
-void Vfirst(Instruction *inst) {
-  auto *rv_state = static_cast<RiscVState *>(inst->state());
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vfirst(Instruction* inst) {
+  auto* rv_state = static_cast<RiscVState*>(inst->state());
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto *dest_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* dest_db = inst->Destination(0)->AllocateDataBuffer();
   // Initialize the element index to -1.
   uint64_t element_index = -1LL;
   int vlen = rv_vector->vector_length();
@@ -176,8 +176,8 @@
 }
 
 // Vector integer sign and zero extension instructions.
-void Vzext2(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vzext2(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 2:
@@ -199,8 +199,8 @@
   }
 }
 
-void Vsext2(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsext2(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 2:
@@ -222,8 +222,8 @@
   }
 }
 
-void Vzext4(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vzext4(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -241,8 +241,8 @@
   }
 }
 
-void Vsext4(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsext4(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 4:
@@ -260,8 +260,8 @@
   }
 }
 
-void Vzext8(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vzext8(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 8:
@@ -275,8 +275,8 @@
   }
 }
 
-void Vsext8(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vsext8(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   switch (sew) {
     case 8:
@@ -291,20 +291,20 @@
 }
 
 // Vector mask set-before-first mask bit.
-void Vmsbf(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsbf(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   bool before_first = true;
   int last = 0;
@@ -333,20 +333,20 @@
 }
 
 // Vector mask set-including-first mask bit.
-void Vmsif(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsif(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   uint8_t value = 1;
   for (int i = 0; i < vlen; i++) {
@@ -370,20 +370,20 @@
 }
 
 // Vector maks set-only-first mask bit.
-void Vmsof(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vmsof(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   if (rv_vector->vstart()) {
     rv_vector->set_vector_exception();
     return;
   }
   int vlen = rv_vector->vector_length();
-  auto src_op = static_cast<RV32VectorSourceOperand *>(inst->Source(0));
+  auto src_op = static_cast<RV32VectorSourceOperand*>(inst->Source(0));
   auto src_span = src_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
-  auto mask_op = static_cast<RV32VectorSourceOperand *>(inst->Source(1));
+  auto mask_op = static_cast<RV32VectorSourceOperand*>(inst->Source(1));
   auto mask_span = mask_op->GetRegister(0)->data_buffer()->Get<uint8_t>();
   auto dest_op =
-      static_cast<RV32VectorDestinationOperand *>(inst->Destination(0));
-  auto *dest_db = dest_op->CopyDataBuffer(0);
+      static_cast<RV32VectorDestinationOperand*>(inst->Destination(0));
+  auto* dest_db = dest_op->CopyDataBuffer(0);
   auto dest_span = dest_db->Get<uint8_t>();
   bool first = true;
   for (int i = 0; i < vlen; i++) {
@@ -408,8 +408,8 @@
 // writes to each element of the destination vector register group the sum
 // of all bits of elements in the mask register whose index is less than the
 // element. This is subject to masking.
-void Viota(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Viota(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   int count = 0;
   switch (sew) {
@@ -446,8 +446,8 @@
 
 // Writes the index of each active (mask true) element to the destination
 // vector elements.
-void Vid(Instruction *inst) {
-  auto *rv_vector = static_cast<RiscVState *>(inst->state())->rv_vector();
+void Vid(Instruction* inst) {
+  auto* rv_vector = static_cast<RiscVState*>(inst->state())->rv_vector();
   int sew = rv_vector->selected_element_width();
   int index = 0;
   switch (sew) {
diff --git a/riscv/riscv_vector_unary_instructions.h b/riscv/riscv_vector_unary_instructions.h
index 6881608..3b4025d 100644
--- a/riscv/riscv_vector_unary_instructions.h
+++ b/riscv/riscv_vector_unary_instructions.h
@@ -29,46 +29,46 @@
 // Moves a value from index 0 element of a vector register to a scalar register.
 // This instruction takes 1 source and 1 destination. One is a vector register,
 // the other is a scalar (x) register.
-void VmvToScalar(Instruction *inst);
+void VmvToScalar(Instruction* inst);
 // Moves a scalar to index 0 element of a vector register. This instruction
 // takes 1 source and 1 destination. One is a vector register, the other is
 // a scalar (x) register.
-void VmvFromScalar(Instruction *inst);
+void VmvFromScalar(Instruction* inst);
 // Does a population count on the vector mask in the source operand 0 (subject
 // to masking), and writes the result to the scalar register in the destination
 // operand. Operand 1 is a mask register. Only vlen bits are considered.
-void Vcpop(Instruction *inst);
+void Vcpop(Instruction* inst);
 // Computes the index of the first set bit of the vector mask in the source
 // operand 0 (subject ot masking), and writes the result to the scalar register
 // in the destination operand. Operand 1 is a mask register. Only vlen bits
 // are considered.
-void Vfirst(Instruction *inst);
+void Vfirst(Instruction* inst);
 
 // VXUNARY0
 // Element wide zero extend from SEW/2 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext2(Instruction *inst);
+void Vzext2(Instruction* inst);
 // Element wide sign extend from SEW/2 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext2(Instruction *inst);
+void Vsext2(Instruction* inst);
 // Element wide zero extend from SEW/4 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext4(Instruction *inst);
+void Vzext4(Instruction* inst);
 // Element wide sign extend from SEW/4 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext4(Instruction *inst);
+void Vsext4(Instruction* inst);
 // Element wide zero extend from SEW/8 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vzext8(Instruction *inst);
+void Vzext8(Instruction* inst);
 // Element wide sign extend from SEW/8 to SEW. This instruction takes two source
 // operands, and a vector destination operand. Source 0 is the vs2 vector
 // source, and source 1 is a vector mask operand.
-void Vsext8(Instruction *inst);
+void Vsext8(Instruction* inst);
 
 // VMUNARY0
 // Set before first mask bit. Takes a vector mask stored in a vector register
@@ -76,32 +76,32 @@
 // bit in the source mask set to 1. This instruction takes one vector source
 // operands, a mask register, and a vector destination operand. Source 0 is the
 // vs2 register source, source 1 is the vector mask operand.
-void Vmsbf(Instruction *inst);
+void Vmsbf(Instruction* inst);
 // Set only first mask bit. Takes a vector mask stored in a vector register
 // and produces a mask register with only the bit set that corresponds to the
 // the first set active bit in the source mask set to 1. This instruction takes
 // one vector source operands, a mask register, and a vector destination
 // operand. Source 0 is the vs2 register source, source 1 is the vector mask
 // operand.
-void Vmsof(Instruction *inst);
+void Vmsof(Instruction* inst);
 // Set including first mask bit. Takes a vector mask stored in a vector register
 // and produces a mask register with all active bits before and including the
 // first set active bit in the source mask set to 1. This instruction takes one
 // vector source operands, a mask register, and a vector destination operand.
 // Source 0 is the vs2 register source, source 1 is the vector mask operand.
-void Vmsif(Instruction *inst);
+void Vmsif(Instruction* inst);
 // Vector Iota instruction. Takes a vector mask stored in a vector register
 // and writes to each element of the destination vector register group the sum
 // of all bits of elements in the mask register whose index is less than the
 // element (parallel prefix sum). This instruction takes two sources and one
 // destination. Source 0 is the vs2 register source, source 1 is the vector
 // mask operand.
-void Viota(Instruction *inst);
+void Viota(Instruction* inst);
 // Vector element index instruction. Writes the element index to the destination
 // vector element group (masking does not change the value written to active
 // elements, only which elements are written to). This instruction takes 1
 // source (mask register) and one destination.
-void Vid(Instruction *inst);
+void Vid(Instruction* inst);
 }  // namespace riscv
 }  // namespace sim
 }  // namespace mpact
diff --git a/riscv/riscv_xip_xie.cc b/riscv/riscv_xip_xie.cc
index daac170..608c7c1 100644
--- a/riscv/riscv_xip_xie.cc
+++ b/riscv/riscv_xip_xie.cc
@@ -24,7 +24,7 @@
 namespace riscv {
 
 // Machine Interrupt Pending methods.
-RiscVMIp::RiscVMIp(uint32_t initial_value, ArchState *state)
+RiscVMIp::RiscVMIp(uint32_t initial_value, ArchState* state)
     : RiscVSimpleCsr<uint32_t>("mip", RiscVCsrEnum::kMIp, initial_value,
                                kReadMask, kWriteMask, state) {}
 void RiscVMIp::Set(uint32_t value) {
@@ -43,7 +43,7 @@
 uint64_t RiscVMIp::GetUint64() { return GetUint32(); }
 
 // Supervisor Interrupt Pending methods.
-RiscVSIp::RiscVSIp(RiscVMIp *mip, RiscVCsrInterface *mideleg, ArchState *state)
+RiscVSIp::RiscVSIp(RiscVMIp* mip, RiscVCsrInterface* mideleg, ArchState* state)
     : RiscVSimpleCsr<uint32_t>("sip", RiscVCsrEnum::kSIp, kReadMask, kWriteMask,
                                state),
       mip_(mip),
@@ -57,7 +57,7 @@
 void RiscVSIp::Set(uint64_t value) { Set(static_cast<uint32_t>(value)); }
 
 // Machine Interrupt Enable methods.
-RiscVMIe::RiscVMIe(uint32_t initial_value, ArchState *state)
+RiscVMIe::RiscVMIe(uint32_t initial_value, ArchState* state)
     : RiscVSimpleCsr<uint32_t>("mie", RiscVCsrEnum::kMIe, initial_value,
                                kReadMask, kWriteMask, state) {}
 void RiscVMIe::Set(uint32_t value) {
@@ -78,7 +78,7 @@
 }
 
 // Supervisor Interrupt Enable methods.
-RiscVSIe::RiscVSIe(RiscVMIe *mie, RiscVCsrInterface *mideleg, ArchState *state)
+RiscVSIe::RiscVSIe(RiscVMIe* mie, RiscVCsrInterface* mideleg, ArchState* state)
     : RiscVSimpleCsr<uint32_t>("sie", RiscVCsrEnum::kSIe, kReadMask, kWriteMask,
                                state),
       mie_(mie),
diff --git a/riscv/riscv_xstatus.cc b/riscv/riscv_xstatus.cc
index 7108f8e..8a4d83e 100644
--- a/riscv/riscv_xstatus.cc
+++ b/riscv/riscv_xstatus.cc
@@ -16,7 +16,6 @@
 
 #include <cstdint>
 
-#include "absl/log/log.h"
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv/riscv_csr.h"
 #include "riscv/riscv_misa.h"
@@ -42,17 +41,17 @@
 
 // Constructors.
 
-RiscVMStatus::RiscVMStatus(uint32_t initial_value, ArchState *state,
-                           RiscVMIsa *misa)
+RiscVMStatus::RiscVMStatus(uint32_t initial_value, ArchState* state,
+                           RiscVMIsa* misa)
     : RiscVMStatus(StretchMStatus32(initial_value), state, RiscVXlen::RV32,
                    misa) {}
 
-RiscVMStatus::RiscVMStatus(uint64_t initial_value, ArchState *state,
-                           RiscVMIsa *misa)
+RiscVMStatus::RiscVMStatus(uint64_t initial_value, ArchState* state,
+                           RiscVMIsa* misa)
     : RiscVMStatus(initial_value, state, RiscVXlen::RV64, misa) {}
 
-RiscVMStatus::RiscVMStatus(uint64_t initial_value, ArchState *state,
-                           RiscVXlen xlen, RiscVMIsa *misa)
+RiscVMStatus::RiscVMStatus(uint64_t initial_value, ArchState* state,
+                           RiscVXlen xlen, RiscVMIsa* misa)
     : RiscVSimpleCsr<uint64_t>("mstatus", RiscVCsrEnum::kMStatus, initial_value,
                                kReadMask, kWriteMask, state),
       misa_(misa) {
@@ -123,7 +122,7 @@
 
 // RiscVSStatus methods.
 
-RiscVSStatus::RiscVSStatus(RiscVMStatus *mstatus, RiscVState *state)
+RiscVSStatus::RiscVSStatus(RiscVMStatus* mstatus, RiscVState* state)
     : RiscVSimpleCsr<uint64_t>("sstatus", RiscVCsrEnum::kSStatus, kReadMask,
                                kWriteMask, state),
       mstatus_(mstatus) {
@@ -165,7 +164,7 @@
 
 // RiscVUStatus methods.
 
-RiscVUStatus::RiscVUStatus(RiscVMStatus *mstatus, RiscVState *state)
+RiscVUStatus::RiscVUStatus(RiscVMStatus* mstatus, RiscVState* state)
     : RiscVSimpleCsr<uint64_t>("ustatus", RiscVCsrEnum::kUStatus, kReadMask,
                                kWriteMask, state),
       mstatus_(mstatus) {
diff --git a/riscv/riscv_xstatus.h b/riscv/riscv_xstatus.h
index f14724e..9d7354d 100644
--- a/riscv/riscv_xstatus.h
+++ b/riscv/riscv_xstatus.h
@@ -38,8 +38,8 @@
   static constexpr uint64_t kWriteMask = 0x0000'0000'007f'f9bbULL;
   // Disable default constructor.
   RiscVMStatus() = delete;
-  RiscVMStatus(uint32_t initial_value, ArchState *state, RiscVMIsa *misa);
-  RiscVMStatus(uint64_t initial_value, ArchState *state, RiscVMIsa *misa);
+  RiscVMStatus(uint32_t initial_value, ArchState* state, RiscVMIsa* misa);
+  RiscVMStatus(uint64_t initial_value, ArchState* state, RiscVMIsa* misa);
 
   ~RiscVMStatus() override = default;
 
@@ -116,8 +116,8 @@
 
  private:
   // Private constructor.
-  RiscVMStatus(uint64_t initial_value, ArchState *state, RiscVXlen xlen,
-               RiscVMIsa *misa);
+  RiscVMStatus(uint64_t initial_value, ArchState* state, RiscVXlen xlen,
+               RiscVMIsa* misa);
   // Template function to help implement the getters.
   template <int Shift, uint64_t BitMask>
   inline int GetterHelper() {
@@ -130,7 +130,7 @@
     buffer_mask_ |= BitMask << Shift;
   }
 
-  RiscVMIsa *misa_;
+  RiscVMIsa* misa_;
   uint64_t buffer_ = 0;
   uint64_t buffer_mask_ = 0;
   uint32_t read_mask_32_;
@@ -147,7 +147,7 @@
   static constexpr uint64_t kWriteMask = 0x0000'0000'000d'e133ULL;
 
   RiscVSStatus() = delete;
-  RiscVSStatus(RiscVMStatus *mstatus, RiscVState *state);
+  RiscVSStatus(RiscVMStatus* mstatus, RiscVState* state);
 
   // Overrides.
   uint64_t AsUint64() override;
@@ -199,7 +199,7 @@
   uint32_t read_mask_32_;
   uint32_t write_mask_32_;
   uint64_t set_mask_from_32_;
-  RiscVMStatus *mstatus_;
+  RiscVMStatus* mstatus_;
 };
 
 // The ustatus register is a further restricted view of sstatus.
@@ -209,7 +209,7 @@
   static constexpr uint64_t kWriteMask = 0x11ULL;
 
   RiscVUStatus() = delete;
-  RiscVUStatus(RiscVMStatus *mstatus, RiscVState *state);
+  RiscVUStatus(RiscVMStatus* mstatus, RiscVState* state);
   // Overrides.
   uint64_t AsUint64() override;
   uint32_t AsUint32() override;
@@ -229,7 +229,7 @@
   uint32_t read_mask_32_;
   uint32_t write_mask_32_;
   uint64_t set_mask_from_32_;
-  RiscVMStatus *mstatus_;
+  RiscVMStatus* mstatus_;
 };
 
 }  // namespace riscv
diff --git a/riscv/riscv_zc_getters.h b/riscv/riscv_zc_getters.h
index 8525582..827f439 100644
--- a/riscv/riscv_zc_getters.h
+++ b/riscv/riscv_zc_getters.h
@@ -50,8 +50,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcaSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVEncodingCommon *common) {
+void AddRiscVZcaSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3rs1, [common]() {
     auto num = Extractors::CS::ExtractCsRs1(common->inst_word());
     return GetRegisterSourceOp<IntRegister>(
@@ -98,11 +98,10 @@
     return new ImmediateOperand<uint32_t>(
         Extractors::Inst16Format::ExtractUimm6(common->inst_word()));
   });
-  Insert(getter_map, *Enum::kICiUimm6x4,
-         [common]() -> SourceOperandInterface * {
-           return new ImmediateOperand<uint32_t>(
-               Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
-         });
+  Insert(getter_map, *Enum::kICiUimm6x4, [common]() -> SourceOperandInterface* {
+    return new ImmediateOperand<uint32_t>(
+        Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
+  });
   Insert(getter_map, *Enum::kICiwUimm8x4, [common]() {
     return new ImmediateOperand<uint32_t>(
         Extractors::Inst16Format::ExtractCiwImm10(common->inst_word()));
@@ -116,7 +115,7 @@
         Extractors::Inst16Format::ExtractClImmW(common->inst_word()));
   });
   Insert(getter_map, *Enum::kICssUimm6x4,
-         [common]() -> SourceOperandInterface * {
+         [common]() -> SourceOperandInterface* {
            return new ImmediateOperand<uint32_t>(
                Extractors::Inst16Format::ExtractCssImmW(common->inst_word()));
          });
@@ -133,8 +132,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcaDestGetters(SourceOpGetterMap &getter_map,
-                            RiscVEncodingCommon *common) {
+void AddRiscVZcaDestGetters(SourceOpGetterMap& getter_map,
+                            RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3rd, [common](int latency) {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return GetRegisterDestinationOp<IntRegister>(
@@ -146,8 +145,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcbSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVEncodingCommon *common) {
+void AddRiscVZcbSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kUimm2b, [common]() {
     auto num = Extractors::CLB::ExtractUimm2(common->inst_word());
     return new ImmediateOperand<uint32_t>(num);
@@ -162,8 +161,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcbDestGetters(DestOpGetterMap &getter_map,
-                            RiscVEncodingCommon *common) {
+void AddRiscVZcbDestGetters(DestOpGetterMap& getter_map,
+                            RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3rs2, [common](int latency) {
     int num = Extractors::CLB::ExtractClRd(common->inst_word());
     return GetRegisterDestinationOp<IntRegister>(
@@ -175,8 +174,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcfSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVEncodingCommon *common) {
+void AddRiscVZcfSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3frs2, [common]() {
     auto num = Extractors::CS::ExtractCsRs2(common->inst_word());
     return GetRegisterSourceOp<FpRegister>(
@@ -195,11 +194,10 @@
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kICiUimm6x4,
-         [common]() -> SourceOperandInterface * {
-           return new ImmediateOperand<uint32_t>(
-               Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
-         });
+  Insert(getter_map, *Enum::kICiUimm6x4, [common]() -> SourceOperandInterface* {
+    return new ImmediateOperand<uint32_t>(
+        Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
+  });
   Insert(getter_map, *Enum::kIClUimm5x4, [common]() {
     return new ImmediateOperand<uint32_t>(
         Extractors::Inst16Format::ExtractClImmW(common->inst_word()));
@@ -219,8 +217,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcfDestGetters(DestOpGetterMap &getter_map,
-                            RiscVEncodingCommon *common) {
+void AddRiscVZcfDestGetters(DestOpGetterMap& getter_map,
+                            RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3frd, [common](int latency) {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return GetRegisterDestinationOp<FpRegister>(
@@ -232,8 +230,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcdSourceGetters(SourceOpGetterMap &getter_map,
-                              RiscVEncodingCommon *common) {
+void AddRiscVZcdSourceGetters(SourceOpGetterMap& getter_map,
+                              RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3drs2, [common]() {
     auto num = Extractors::CS::ExtractCsRs2(common->inst_word());
     return GetRegisterSourceOp<FpRegister>(
@@ -252,11 +250,10 @@
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kICiUimm6x8,
-         [common]() -> SourceOperandInterface * {
-           return new ImmediateOperand<uint32_t>(
-               Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
-         });
+  Insert(getter_map, *Enum::kICiUimm6x8, [common]() -> SourceOperandInterface* {
+    return new ImmediateOperand<uint32_t>(
+        Extractors::Inst16Format::ExtractCiImmW(common->inst_word()));
+  });
   Insert(getter_map, *Enum::kIClUimm5x8, [common]() {
     return new ImmediateOperand<uint32_t>(
         Extractors::Inst16Format::ExtractClImmW(common->inst_word()));
@@ -276,8 +273,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcdDestGetters(DestOpGetterMap &getter_map,
-                            RiscVEncodingCommon *common) {
+void AddRiscVZcdDestGetters(DestOpGetterMap& getter_map,
+                            RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kC3drd, [common](int latency) {
     int num = Extractors::CL::ExtractClRd(common->inst_word());
     return GetRegisterDestinationOp<IntRegister>(
@@ -292,8 +289,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcmpSourceGetters(SourceOpGetterMap &getter_map,
-                               RiscVEncodingCommon *common) {
+void AddRiscVZcmpSourceGetters(SourceOpGetterMap& getter_map,
+                               RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kRlist, [common]() {
     return new ImmediateOperand<uint32_t>(
         Extractors::CMMP::ExtractRlist(common->inst_word()));
@@ -337,8 +334,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcmpDestGetters(DestOpGetterMap &getter_map,
-                             RiscVEncodingCommon *common) {
+void AddRiscVZcmpDestGetters(DestOpGetterMap& getter_map,
+                             RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kSreg1, [common](int latency) {
     int num =
         kSRegToXRegMap[Extractors::CMMV::ExtractRs1p(common->inst_word())];
@@ -369,10 +366,10 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcmpListSourceGetters(ListSourceOpGetterMap &getter_map,
-                                   RiscVEncodingCommon *common) {
+void AddRiscVZcmpListSourceGetters(ListSourceOpGetterMap& getter_map,
+                                   RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kRlist, [common]() {
-    std::vector<SourceOperandInterface *> result;
+    std::vector<SourceOperandInterface*> result;
     int rlist = Extractors::CMMP::ExtractRlist(common->inst_word());
     // Get the value of 'rlist', and add source operands accordingly.
     if (rlist < 4) return result;
@@ -408,10 +405,10 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcmpListDestGetters(ListDestOpGetterMap &getter_map,
-                                 RiscVEncodingCommon *common) {
+void AddRiscVZcmpListDestGetters(ListDestOpGetterMap& getter_map,
+                                 RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kRlist, [common](std::vector<int> latency) {
-    std::vector<DestinationOperandInterface *> result;
+    std::vector<DestinationOperandInterface*> result;
     int rlist = Extractors::CMMP::ExtractRlist(common->inst_word());
     // Get the value of 'rlist', and add destination operands accordingly.
     int size = latency.size();
@@ -459,8 +456,8 @@
 
 template <typename Enum, typename Extractors, typename IntRegister,
           typename FpRegister>
-void AddRiscVZcmtSourceGetters(SourceOpGetterMap &getter_map,
-                               RiscVEncodingCommon *common) {
+void AddRiscVZcmtSourceGetters(SourceOpGetterMap& getter_map,
+                               RiscVEncodingCommon* common) {
   Insert(getter_map, *Enum::kJtIndex, [common](int latency) {
     int num = Extractors::CMJT::ExtractIndex(common->inst_word());
     return new ImmediateOperand<uint32_t>(num);
diff --git a/riscv/riscv_zc_instructions.cc b/riscv/riscv_zc_instructions.cc
index 02ce209..410cd5e 100644
--- a/riscv/riscv_zc_instructions.cc
+++ b/riscv/riscv_zc_instructions.cc
@@ -43,10 +43,10 @@
 using IntReg = typename std::make_signed<UIntReg>::type;
 
 // Zcmp instructions.
-void RiscVZCmpPush(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVZCmpPush(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   int num_regs = inst->SourcesSize() - 3;
-  auto *db = state->db_factory()->Allocate<UIntReg>(num_regs);
+  auto* db = state->db_factory()->Allocate<UIntReg>(num_regs);
   auto db_span = db->Get<UIntReg>();
   // Get the register values and put them in the data buffer.
   for (int i = 0; i < num_regs; ++i) {
@@ -70,13 +70,13 @@
 
 // This helper pops the number of registers specified into the appropriate
 // destination operands, and then adjusts the stack pointer.
-void RiscVZCmpPopHelper(const Instruction *inst, int size) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVZCmpPopHelper(const Instruction* inst, int size) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   // Compute the stack adjustment.
   auto spimm6 = generic::GetInstructionSource<UIntReg>(inst, 1);
   auto rlist = generic::GetInstructionSource<UIntReg>(inst, 2);
   auto sp_adjustment = spimm6 + kStackAdjBase[rlist];
-  auto *db = state->db_factory()->Allocate<UIntReg>(size);
+  auto* db = state->db_factory()->Allocate<UIntReg>(size);
   // Load registers from the stack.
   auto sp = generic::GetInstructionSource<UIntReg>(inst, 0);
   // Start address = sp + sp_adjustment - sizeof(UIntReg) * size;
@@ -93,25 +93,25 @@
 
 }  // namespace
 
-void RiscVZCmpPop(const Instruction *inst) {
+void RiscVZCmpPop(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 1;
   RiscVZCmpPopHelper(inst, size);
 }
 
-void RiscVZCmpPopRet(const Instruction *inst) {
+void RiscVZCmpPopRet(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 2;  // x2 and next_pc.
   RiscVZCmpPopHelper(inst, size);
   // Now perform the return.
   UIntReg target = generic::GetInstructionSource<UIntReg>(inst, 3);
-  auto *db = inst->Destination(size + 1)->AllocateDataBuffer();
+  auto* db = inst->Destination(size + 1)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->set_branch(true);
 }
 
-void RiscVZCmpPopRetz(const Instruction *inst) {
+void RiscVZCmpPopRetz(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 3;  // x2, x10, and next_pc.
   RiscVZCmpPopHelper(inst, size);
@@ -119,13 +119,13 @@
   RiscVWriteReg<RegType, UIntReg>(inst, size + 1, 0);
   // Now perform the return.
   UIntReg target = generic::GetInstructionSource<UIntReg>(inst, 3);
-  auto *db = inst->Destination(size + 2)->AllocateDataBuffer();
+  auto* db = inst->Destination(size + 2)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->set_branch(true);
 }
 
-void RiscVZCmpMvTwoRegs(const Instruction *inst) {
+void RiscVZCmpMvTwoRegs(const Instruction* inst) {
   RiscVWriteReg<RegType, UIntReg>(
       inst, 0, generic::GetInstructionSource<UIntReg>(inst, 0));
   RiscVWriteReg<RegType, UIntReg>(
@@ -135,9 +135,9 @@
 // Zcmt instructions.
 namespace {
 
-void RiscVZCmtJtHelper(const Instruction *inst, int dest_index) {
+void RiscVZCmtJtHelper(const Instruction* inst, int dest_index) {
   int index = generic::GetInstructionSource<UIntReg>(inst, 0);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   auto jvt_value = state->jvt()->AsUint64();
   auto mode = jvt_value & 0x3f;
   if (mode != 0) {
@@ -147,21 +147,21 @@
   }
   // Load target address from the jump table.
   UIntReg entry_address = (jvt_value & ~0x3f) + (index * sizeof(UIntReg));
-  auto *db = state->db_factory()->Allocate<UIntReg>(1);
+  auto* db = state->db_factory()->Allocate<UIntReg>(1);
   state->LoadMemory(inst, entry_address, db, nullptr, nullptr);
   UIntReg target_address = db->Get<UIntReg>(0);
   db->DecRef();
   // Write the target address to the next pc operand.
-  auto *target_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* target_db = inst->Destination(0)->AllocateDataBuffer();
   target_db->SetSubmit<UIntReg>(0, target_address);
   state->set_branch(true);
 }
 
 }  // namespace
 
-void RiscVZCmtJt(const Instruction *inst) { RiscVZCmtJtHelper(inst, 0); }
+void RiscVZCmtJt(const Instruction* inst) { RiscVZCmtJtHelper(inst, 0); }
 
-void RiscVZCmtJalt(const Instruction *inst) {
+void RiscVZCmtJalt(const Instruction* inst) {
   RiscVZCmtJtHelper(inst, 1);
   // Write the return address to the x1 (ra) operand.
   RiscVWriteReg<RegType, UIntReg>(inst, 1, inst->address() + inst->size());
@@ -184,10 +184,10 @@
 using IntReg = typename std::make_signed<UIntReg>::type;
 
 // Zcmp instructions.
-void RiscVZCmpPush(const Instruction *inst) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVZCmpPush(const Instruction* inst) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   int num_regs = inst->SourcesSize() - 3;
-  auto *db = state->db_factory()->Allocate<UIntReg>(num_regs);
+  auto* db = state->db_factory()->Allocate<UIntReg>(num_regs);
   auto db_span = db->Get<UIntReg>();
   // Get the register values and put them in the data buffer.
   for (int i = 0; i < num_regs; ++i) {
@@ -211,13 +211,13 @@
 
 // This helper pops the number of registers specified into the appropriate
 // destination operands, and then adjusts the stack pointer.
-void RiscVZCmpPopHelper(const Instruction *inst, int size) {
-  RiscVState *state = static_cast<RiscVState *>(inst->state());
+void RiscVZCmpPopHelper(const Instruction* inst, int size) {
+  RiscVState* state = static_cast<RiscVState*>(inst->state());
   // Compute the stack adjustment.
   auto spimm6 = generic::GetInstructionSource<UIntReg>(inst, 1);
   auto rlist = generic::GetInstructionSource<UIntReg>(inst, 2);
   auto sp_adjustment = spimm6 + kStackAdjBase[rlist];
-  auto *db = state->db_factory()->Allocate<UIntReg>(size);
+  auto* db = state->db_factory()->Allocate<UIntReg>(size);
   // Load registers from the stack.
   auto sp = generic::GetInstructionSource<UIntReg>(inst, 0);
   // Start address = sp + sp_adjustment - sizeof(UIntReg) * size;
@@ -234,25 +234,25 @@
 
 }  // namespace
 
-void RiscVZCmpPop(const Instruction *inst) {
+void RiscVZCmpPop(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 1;
   RiscVZCmpPopHelper(inst, size);
 }
 
-void RiscVZCmpPopRet(const Instruction *inst) {
+void RiscVZCmpPopRet(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 2;  // x2 and next_pc.
   RiscVZCmpPopHelper(inst, size);
   // Now perform the return.
   UIntReg target = generic::GetInstructionSource<UIntReg>(inst, 3);
-  auto *db = inst->Destination(size + 1)->AllocateDataBuffer();
+  auto* db = inst->Destination(size + 1)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->set_branch(true);
 }
 
-void RiscVZCmpPopRetz(const Instruction *inst) {
+void RiscVZCmpPopRetz(const Instruction* inst) {
   // Size is the number of registers to pop.
   int size = inst->DestinationsSize() - 3;  // x2, x10, and next_pc.
   RiscVZCmpPopHelper(inst, size);
@@ -260,13 +260,13 @@
   RiscVWriteReg<RegType, UIntReg>(inst, size + 1, 0);
   // Now perform the return.
   UIntReg target = generic::GetInstructionSource<UIntReg>(inst, 3);
-  auto *db = inst->Destination(size + 2)->AllocateDataBuffer();
+  auto* db = inst->Destination(size + 2)->AllocateDataBuffer();
   db->SetSubmit<UIntReg>(0, target);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   state->set_branch(true);
 }
 
-void RiscVZCmpMvTwoRegs(const Instruction *inst) {
+void RiscVZCmpMvTwoRegs(const Instruction* inst) {
   RiscVWriteReg<RegType, UIntReg>(
       inst, 0, generic::GetInstructionSource<UIntReg>(inst, 0));
   RiscVWriteReg<RegType, UIntReg>(
@@ -276,9 +276,9 @@
 // Zcmt instructions.
 namespace {
 
-void RiscVZCmtJtHelper(const Instruction *inst, int dest_index) {
+void RiscVZCmtJtHelper(const Instruction* inst, int dest_index) {
   int index = generic::GetInstructionSource<UIntReg>(inst, 0);
-  auto *state = static_cast<RiscVState *>(inst->state());
+  auto* state = static_cast<RiscVState*>(inst->state());
   auto jvt_value = state->jvt()->AsUint64();
   auto mode = jvt_value & 0x3f;
   if (mode != 0) {
@@ -288,21 +288,21 @@
   }
   // Load target address from the jump table.
   UIntReg entry_address = (jvt_value & ~0x3f) + (index * sizeof(UIntReg));
-  auto *db = state->db_factory()->Allocate<UIntReg>(1);
+  auto* db = state->db_factory()->Allocate<UIntReg>(1);
   state->LoadMemory(inst, entry_address, db, nullptr, nullptr);
   UIntReg target_address = db->Get<UIntReg>(0);
   db->DecRef();
   // Write the target address to the next pc operand.
-  auto *target_db = inst->Destination(0)->AllocateDataBuffer();
+  auto* target_db = inst->Destination(0)->AllocateDataBuffer();
   target_db->SetSubmit<UIntReg>(0, target_address);
   state->set_branch(true);
 }
 
 }  // namespace
 
-void RiscVZCmtJt(const Instruction *inst) { RiscVZCmtJtHelper(inst, 0); }
+void RiscVZCmtJt(const Instruction* inst) { RiscVZCmtJtHelper(inst, 0); }
 
-void RiscVZCmtJalt(const Instruction *inst) {
+void RiscVZCmtJalt(const Instruction* inst) {
   RiscVZCmtJtHelper(inst, 1);
   // Write the return address to the x1 (ra) operand.
   RiscVWriteReg<RegType, UIntReg>(inst, 1, inst->address() + inst->size());
diff --git a/riscv/riscv_zc_instructions.h b/riscv/riscv_zc_instructions.h
index 005a707..82d123a 100644
--- a/riscv/riscv_zc_instructions.h
+++ b/riscv/riscv_zc_instructions.h
@@ -26,30 +26,30 @@
 namespace RV32 {
 
 // Zcmp instructions.
-void RiscVZCmpPush(const Instruction *inst);
-void RiscVZCmpPop(const Instruction *inst);
-void RiscVZCmpPopRet(const Instruction *inst);
-void RiscVZCmpPopRetz(const Instruction *inst);
-void RiscVZCmpMvTwoRegs(const Instruction *inst);
+void RiscVZCmpPush(const Instruction* inst);
+void RiscVZCmpPop(const Instruction* inst);
+void RiscVZCmpPopRet(const Instruction* inst);
+void RiscVZCmpPopRetz(const Instruction* inst);
+void RiscVZCmpMvTwoRegs(const Instruction* inst);
 
 // Zcmt instructions.
-void RiscVZCmtJt(const Instruction *inst);
-void RiscVZCmtJalt(const Instruction *inst);
+void RiscVZCmtJt(const Instruction* inst);
+void RiscVZCmtJalt(const Instruction* inst);
 
 }  // namespace RV32
 
 namespace RV64 {
 
 // Zcmp instructions.
-void RiscVZCmpPush(const Instruction *inst);
-void RiscVZCmpPop(const Instruction *inst);
-void RiscVZCmpPopRet(const Instruction *inst);
-void RiscVZCmpPopRetz(const Instruction *inst);
-void RiscVZCmpMvTwoRegs(const Instruction *inst);
+void RiscVZCmpPush(const Instruction* inst);
+void RiscVZCmpPop(const Instruction* inst);
+void RiscVZCmpPopRet(const Instruction* inst);
+void RiscVZCmpPopRetz(const Instruction* inst);
+void RiscVZCmpMvTwoRegs(const Instruction* inst);
 
 // Zcmt instructions.
-void RiscVZCmtJt(const Instruction *inst);
-void RiscVZCmtJalt(const Instruction *inst);
+void RiscVZCmtJt(const Instruction* inst);
+void RiscVZCmtJalt(const Instruction* inst);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_zfencei_instructions.cc b/riscv/riscv_zfencei_instructions.cc
index 28eb635..5983fbe 100644
--- a/riscv/riscv_zfencei_instructions.cc
+++ b/riscv/riscv_zfencei_instructions.cc
@@ -21,8 +21,8 @@
 namespace sim {
 namespace riscv {
 
-void RiscVZFencei(Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RiscVZFencei(Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->FenceI(instruction);
 }
 
diff --git a/riscv/riscv_zfencei_instructions.h b/riscv/riscv_zfencei_instructions.h
index a58b1f7..d5045be 100644
--- a/riscv/riscv_zfencei_instructions.h
+++ b/riscv/riscv_zfencei_instructions.h
@@ -24,7 +24,7 @@
 using ::mpact::sim::generic::Instruction;
 
 // This instruction has no source or destination operands.
-void RiscVZFencei(Instruction *instruction);
+void RiscVZFencei(Instruction* instruction);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_zfh_instructions.cc b/riscv/riscv_zfh_instructions.cc
index fc8baac..0a47069 100644
--- a/riscv/riscv_zfh_instructions.cc
+++ b/riscv/riscv_zfh_instructions.cc
@@ -86,7 +86,7 @@
 
 // Convert from half precision to single or double precision.
 template <typename T>
-inline T ConvertFromHalfFP(HalfFP half_fp, uint32_t &fflags) {
+inline T ConvertFromHalfFP(HalfFP half_fp, uint32_t& fflags) {
   using UIntType = typename FPTypeInfo<T>::UIntType;
   using HalfFPUIntType = typename FPTypeInfo<HalfFP>::UIntType;
   HalfFPUIntType in_int = half_fp.value;
@@ -144,7 +144,7 @@
 // This is done to get the correct rounding behavior for free from the FPU.
 template <typename T>
 inline HalfFP ConvertToHalfFP(T input_value, FPRoundingMode rm,
-                              uint32_t &fflags) {
+                              uint32_t& fflags) {
   using UIntType = typename FPTypeInfo<T>::UIntType;
   using IntType = typename FPTypeInfo<T>::IntType;
   UIntType in_int = absl::bit_cast<UIntType>(input_value);
@@ -293,10 +293,10 @@
 
 template <typename Result, typename Argument>
 void RiscVZfhCvtHelper(
-    const Instruction *instruction,
-    std::function<Result(Argument, FPRoundingMode, uint32_t &)> operation) {
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+    const Instruction* instruction,
+    std::function<Result(Argument, FPRoundingMode, uint32_t&)> operation) {
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   using DstRegValue = typename DataTypeRegValue<Result>::type;
   uint32_t fflags = 0;
 
@@ -312,7 +312,7 @@
   // Get the rounding mode.
   int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
-  auto *rv_fp = static_cast<RiscVState *>(instruction->state())->rv_fp();
+  auto* rv_fp = static_cast<RiscVState*>(instruction->state())->rv_fp();
   // If the rounding mode is dynamic, read it from the current state.
   if (rm_value == *FPRoundingMode::kDynamic) {
     if (!rv_fp->rounding_mode_valid()) {
@@ -328,7 +328,7 @@
     dest_value = operation(lhs, static_cast<FPRoundingMode>(rm_value), fflags);
   }
   fflags_dest->GetRiscVCsr()->SetBits(fflags);
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
 
@@ -337,7 +337,7 @@
     // bits have to be set to all ones.
     using UReg = typename std::make_unsigned<DstRegValue>::type;
     using UInt = typename FPTypeInfo<Result>::UIntType;
-    auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+    auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
     UReg reg_value = std::numeric_limits<UReg>::max();
     int shift = 8 * sizeof(Result);
     reg_value = (reg_value << shift) | dest_u_value;
@@ -350,16 +350,16 @@
 // Generic helper function enabling HalfFP operations in native datatypes.
 template <typename Argument, typename IntermediateType>
 void RiscVZfhUnaryHelper(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<IntermediateType(IntermediateType)> operation) {
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   uint32_t fflags = 0;
   RiscVUnaryFloatNaNBoxOp<RVFpRegister::ValueType, RVFpRegister::ValueType,
                           HalfFP, Argument>(
       instruction, [instruction, &operation, &fflags](Argument a) -> HalfFP {
-        RiscVFPState *rv_fp =
-            static_cast<RiscVState *>(instruction->state())->rv_fp();
+        RiscVFPState* rv_fp =
+            static_cast<RiscVState*>(instruction->state())->rv_fp();
         int rm_value = generic::GetInstructionSource<int>(instruction, 1);
 
         // If the rounding mode is dynamic, read it from the current state.
@@ -394,17 +394,17 @@
 // Generic helper function enabling HalfFP operations in native datatypes.
 template <typename Argument, typename IntermediateType>
 void RiscVZfhBinaryHelper(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<IntermediateType(IntermediateType, IntermediateType)>
         operation) {
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   uint32_t fflags = 0;
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, HalfFP, Argument>(
       instruction,
       [instruction, &operation, &fflags](Argument a, Argument b) -> HalfFP {
-        RiscVFPState *rv_fp =
-            static_cast<RiscVState *>(instruction->state())->rv_fp();
+        RiscVFPState* rv_fp =
+            static_cast<RiscVState*>(instruction->state())->rv_fp();
         int rm_value = generic::GetInstructionSource<int>(instruction, 2);
         // If the rounding mode is dynamic, read it from the current state.
         if (rm_value == *FPRoundingMode::kDynamic) {
@@ -440,12 +440,12 @@
 // Generic helper function enabling HalfFP operations in native datatypes.
 template <typename Argument, typename IntermediateType>
 void RiscVZfhTernaryHelper(
-    const Instruction *instruction,
+    const Instruction* instruction,
     std::function<IntermediateType(IntermediateType, IntermediateType,
                                    IntermediateType)>
         operation) {
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   uint32_t fflags = 0;
   // RiscVTernaryFloatNaNBoxOp will handle the register NaN boxed reads and
   // write. The operation is in a native datatype so we will handle conversions
@@ -454,8 +454,8 @@
       instruction,
       [instruction, &operation, &fflags](Argument a, Argument b,
                                          Argument c) -> HalfFP {
-        RiscVFPState *rv_fp =
-            static_cast<RiscVState *>(instruction->state())->rv_fp();
+        RiscVFPState* rv_fp =
+            static_cast<RiscVState*>(instruction->state())->rv_fp();
         int rm_value = generic::GetInstructionSource<int>(instruction, 3);
         // If the rounding mode is dynamic, read it from the current state.
         if (rm_value == *FPRoundingMode::kDynamic) {
@@ -492,7 +492,7 @@
 
 // Move a half precision value from a float register to an integer register.
 template <typename XRegister>
-void RiscVZfhFMvxhHelper(const Instruction *instruction) {
+void RiscVZfhFMvxhHelper(const Instruction* instruction) {
   using XRegValue = typename XRegister::ValueType;
   RiscVUnaryFloatOp<XRegValue, HalfFP>(instruction, [](HalfFP a) -> XRegValue {
     if (FPTypeInfo<HalfFP>::SignBit(a)) {
@@ -505,20 +505,20 @@
 
 // Move a half precision value from an integer register to a float register
 template <typename XRegister>
-inline void RiscVZfhFMvhxHelper(const Instruction *instruction) {
+inline void RiscVZfhFMvhxHelper(const Instruction* instruction) {
   using DstRegValue = typename RVFpRegister::ValueType;
   using SrcRegValue = typename XRegister::ValueType;
   SrcRegValue lhs = generic::GetInstructionSource<SrcRegValue>(instruction, 0);
   HalfFP dest_value = {.value = static_cast<uint16_t>(lhs)};
 
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
 
   // NaN box the value.
   using UReg = typename std::make_unsigned<DstRegValue>::type;
   using UInt = typename FPTypeInfo<HalfFP>::UIntType;
-  auto dest_u_value = *reinterpret_cast<UInt *>(&dest_value);
+  auto dest_u_value = *reinterpret_cast<UInt*>(&dest_value);
   UReg reg_value = std::numeric_limits<UReg>::max();
   int shift = 8 * sizeof(HalfFP);
   reg_value = (reg_value << shift) | dest_u_value;
@@ -527,7 +527,7 @@
 
 // Compare two half precision values for equality.
 template <typename XRegister>
-inline void RiscVZfhFcmpeqHelper(const Instruction *instruction) {
+inline void RiscVZfhFcmpeqHelper(const Instruction* instruction) {
   using DstRegValue = typename XRegister::ValueType;
   uint32_t fflags = 0;
   HalfFP lhs =
@@ -538,19 +538,19 @@
   float rhs_f = ConvertFromHalfFP<float>(rhs, fflags);
 
   DstRegValue result = lhs_f == rhs_f ? 1 : 0;
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<DstRegValue>(0, result);
 
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   fflags_dest->GetRiscVCsr()->SetBits(fflags & *FPExceptions::kInvalidOp);
 }
 
 // Compare two half precision values for less than.
 template <typename XRegister>
-inline void RiscVZfhFcmpltHelper(const Instruction *instruction) {
+inline void RiscVZfhFcmpltHelper(const Instruction* instruction) {
   using DstRegValue = typename XRegister::ValueType;
   uint32_t unused_fflags = 0;
   HalfFP lhs =
@@ -561,13 +561,13 @@
   float rhs_f = ConvertFromHalfFP<float>(rhs, unused_fflags);
 
   DstRegValue result = lhs_f < rhs_f ? 1 : 0;
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<DstRegValue>(0, result);
 
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   if (std::isnan(lhs_f) || std::isnan(rhs_f)) {
     fflags_dest->GetRiscVCsr()->SetBits(*FPExceptions::kInvalidOp);
   }
@@ -575,7 +575,7 @@
 
 // Compare two half precision values for less than or equal to.
 template <typename XRegister>
-void RiscVZfhFcmpleHelper(const Instruction *instruction) {
+void RiscVZfhFcmpleHelper(const Instruction* instruction) {
   using DstRegValue = typename XRegister::ValueType;
   uint32_t unused_fflags = 0;
   HalfFP lhs =
@@ -586,13 +586,13 @@
   float rhs_f = ConvertFromHalfFP<float>(rhs, unused_fflags);
 
   DstRegValue result = lhs_f <= rhs_f ? 1 : 0;
-  auto *reg = static_cast<generic::RegisterDestinationOperand<DstRegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<DstRegValue>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<DstRegValue>(0, result);
 
-  RiscVCsrDestinationOperand *fflags_dest =
-      static_cast<RiscVCsrDestinationOperand *>(instruction->Destination(1));
+  RiscVCsrDestinationOperand* fflags_dest =
+      static_cast<RiscVCsrDestinationOperand*>(instruction->Destination(1));
   if (std::isnan(lhs_f) || std::isnan(rhs_f)) {
     fflags_dest->GetRiscVCsr()->SetBits(*FPExceptions::kInvalidOp);
   }
@@ -603,45 +603,45 @@
 namespace RV32 {
 // Move a half precision value from a float register to a 32 bit integer
 // register.
-void RiscVZfhFMvxh(const Instruction *instruction) {
+void RiscVZfhFMvxh(const Instruction* instruction) {
   RiscVZfhFMvxhHelper<RV32Register>(instruction);
 }
 
 // Move a half precision value from an integer register to a float register and
 // NaN box the value.
-void RiscVZfhFMvhx(const Instruction *instruction) {
+void RiscVZfhFMvhx(const Instruction* instruction) {
   RiscVZfhFMvhxHelper<RV32Register>(instruction);
 }
 
 // Convert from half precision to signed 32 bit integer.
-void RiscVZfhCvtWh(const Instruction *instruction) {
+void RiscVZfhCvtWh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV32Register::ValueType, HalfFP,
                                 int32_t>(instruction);
 }
 
 // Convert from half precision to unsigned 32 bit integer.
-void RiscVZfhCvtWuh(const Instruction *instruction) {
+void RiscVZfhCvtWuh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV32Register::ValueType, HalfFP,
                                 uint32_t>(instruction);
 }
 
 // Compare two half precision values for equality.
-void RiscVZfhFcmpeq(const Instruction *instruction) {
+void RiscVZfhFcmpeq(const Instruction* instruction) {
   RiscVZfhFcmpeqHelper<RV32Register>(instruction);
 }
 
 // Compare two half precision values for less than.
-void RiscVZfhFcmplt(const Instruction *instruction) {
+void RiscVZfhFcmplt(const Instruction* instruction) {
   RiscVZfhFcmpltHelper<RV32Register>(instruction);
 }
 
 // Compare two half precision values for less than or equal to.
-void RiscVZfhFcmple(const Instruction *instruction) {
+void RiscVZfhFcmple(const Instruction* instruction) {
   RiscVZfhFcmpleHelper<RV32Register>(instruction);
 }
 
 // Classify a half precision value.
-void RiscVZfhFclass(const Instruction *instruction) {
+void RiscVZfhFclass(const Instruction* instruction) {
   RiscVUnaryOp<RV32Register, uint32_t, HalfFP>(
       instruction, [](HalfFP a) -> uint32_t {
         return static_cast<uint32_t>(ClassifyFP(a));
@@ -653,45 +653,45 @@
 namespace RV64 {
 // Move a half precision value from a float register to a 32 bit integer
 // register.
-void RiscVZfhFMvxh(const Instruction *instruction) {
+void RiscVZfhFMvxh(const Instruction* instruction) {
   RiscVZfhFMvxhHelper<RV64Register>(instruction);
 }
 
 // Move a half precision value from an integer register to a float register and
 // NaN box the value.
-void RiscVZfhFMvhx(const Instruction *instruction) {
+void RiscVZfhFMvhx(const Instruction* instruction) {
   RiscVZfhFMvhxHelper<RV64Register>(instruction);
 }
 
 // Convert from half precision to signed 32 bit integer.
-void RiscVZfhCvtWh(const Instruction *instruction) {
+void RiscVZfhCvtWh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV64Register::ValueType, HalfFP,
                                 int32_t>(instruction);
 }
 
 // Convert from half precision to unsigned 32 bit integer.
-void RiscVZfhCvtWuh(const Instruction *instruction) {
+void RiscVZfhCvtWuh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV64Register::ValueType, HalfFP,
                                 uint32_t>(instruction);
 }
 
 // Compare two half precision values for equality.
-void RiscVZfhFcmpeq(const Instruction *instruction) {
+void RiscVZfhFcmpeq(const Instruction* instruction) {
   RiscVZfhFcmpeqHelper<RV64Register>(instruction);
 }
 
 // Compare two half precision values for less than.
-void RiscVZfhFcmplt(const Instruction *instruction) {
+void RiscVZfhFcmplt(const Instruction* instruction) {
   RiscVZfhFcmpltHelper<RV64Register>(instruction);
 }
 
 // Compare two half precision values for less than or equal to.
-void RiscVZfhFcmple(const Instruction *instruction) {
+void RiscVZfhFcmple(const Instruction* instruction) {
   RiscVZfhFcmpleHelper<RV64Register>(instruction);
 }
 
 // Classify a half precision value.
-void RiscVZfhFclass(const Instruction *instruction) {
+void RiscVZfhFclass(const Instruction* instruction) {
   RiscVUnaryOp<RV64Register, uint64_t, HalfFP>(
       instruction, [](HalfFP a) -> uint64_t {
         return static_cast<uint64_t>(ClassifyFP(a));
@@ -699,44 +699,44 @@
 }
 
 // Converts from half precision to signed 64 bit integer.
-void RiscVZfhCvtLh(const Instruction *instruction) {
+void RiscVZfhCvtLh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV64Register::ValueType, HalfFP,
                                 int64_t>(instruction);
 }
 
 // Converts from half precision to unsigned 64 bit integer.
-void RiscVZfhCvtLuh(const Instruction *instruction) {
+void RiscVZfhCvtLuh(const Instruction* instruction) {
   RiscVConvertFloatWithFflagsOp<typename RV64Register::ValueType, HalfFP,
                                 uint64_t>(instruction);
 }
 
 // Converts from signed 64 bit integer to half precision.
-void RiscVZfhCvtHl(const Instruction *instruction) {
+void RiscVZfhCvtHl(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, int64_t>(
       instruction,
-      [](int64_t a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      [](int64_t a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         return ConvertToHalfFP(static_cast<float>(a), rm, fflags);
       });
 }
 
 // Convert from unsigned 64 bit integer to half precision.
-void RiscVZfhCvtHlu(const Instruction *instruction) {
+void RiscVZfhCvtHlu(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, uint64_t>(
       instruction,
-      [](uint64_t a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      [](uint64_t a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         return ConvertToHalfFP(static_cast<float>(a), rm, fflags);
       });
 }
 
 }  // namespace RV64
 
-void RiscVZfhFlhChild(const Instruction *instruction) {
+void RiscVZfhFlhChild(const Instruction* instruction) {
   using FPUInt = typename FPTypeInfo<HalfFP>::UIntType;
-  LoadContext *context = static_cast<LoadContext *>(instruction->context());
+  LoadContext* context = static_cast<LoadContext*>(instruction->context());
   auto value = context->value_db->Get<FPUInt>(0);
-  auto *reg =
+  auto* reg =
       static_cast<
-          generic::RegisterDestinationOperand<RVFpRegister::ValueType> *>(
+          generic::RegisterDestinationOperand<RVFpRegister::ValueType>*>(
           instruction->Destination(0))
           ->GetRegister();
   if (sizeof(RVFpRegister::ValueType) > sizeof(FPUInt)) {
@@ -751,64 +751,64 @@
 }
 
 // Convert from half precision to single precision.
-void RiscVZfhCvtSh(const Instruction *instruction) {
+void RiscVZfhCvtSh(const Instruction* instruction) {
   RiscVZfhCvtHelper<float, HalfFP>(
-      instruction, [](HalfFP a, FPRoundingMode rm, uint32_t &fflags) -> float {
+      instruction, [](HalfFP a, FPRoundingMode rm, uint32_t& fflags) -> float {
         return ConvertFromHalfFP<float>(a, fflags);
       });
 }
 
 // Convert from single precision to half precision.
-void RiscVZfhCvtHs(const Instruction *instruction) {
+void RiscVZfhCvtHs(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, float>(
-      instruction, [](float a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      instruction, [](float a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         return ConvertToHalfFP(a, rm, fflags);
       });
 }
 
 // Convert from half precision to double precision.
-void RiscVZfhCvtDh(const Instruction *instruction) {
+void RiscVZfhCvtDh(const Instruction* instruction) {
   RiscVZfhCvtHelper<double, HalfFP>(
-      instruction, [](HalfFP a, FPRoundingMode rm, uint32_t &fflags) -> double {
+      instruction, [](HalfFP a, FPRoundingMode rm, uint32_t& fflags) -> double {
         return ConvertFromHalfFP<double>(a, fflags);
       });
 }
 
 // Convert from double precision to half precision.
-void RiscVZfhCvtHd(const Instruction *instruction) {
+void RiscVZfhCvtHd(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, double>(
-      instruction, [](double a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      instruction, [](double a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         return ConvertToHalfFP(a, rm, fflags);
       });
 }
 
 // Add two half precision values. Do the calculation in single precision.
-void RiscVZfhFadd(const Instruction *instruction) {
+void RiscVZfhFadd(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(
       instruction, [](float a, float b) -> float { return a + b; });
 }
 
 // Subtract two half precision values. Do the calculation in single precision.
-void RiscVZfhFsub(const Instruction *instruction) {
+void RiscVZfhFsub(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(
       instruction, [](float a, float b) -> float { return a - b; });
 }
 
 // Multiply two half precision values. Do the calculation in single precision.
-void RiscVZfhFmul(const Instruction *instruction) {
+void RiscVZfhFmul(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(
       instruction, [](float a, float b) -> float { return a * b; });
 }
 
 // Divide two half precision values. Do the calculation in single precision.
-void RiscVZfhFdiv(const Instruction *instruction) {
+void RiscVZfhFdiv(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(
       instruction, [](float a, float b) -> float { return a / b; });
 }
 
 // Take the minimum of two half precision values. Do the operation in single
 // precision.
-void RiscVZfhFmin(const Instruction *instruction) {
+void RiscVZfhFmin(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(instruction,
                                       [](float a, float b) -> float {
                                         // On ARM std::fminf returns NaN if
@@ -826,7 +826,7 @@
 
 // Take the maximum of two half precision values. Do the operation in single
 // precision.
-void RiscVZfhFmax(const Instruction *instruction) {
+void RiscVZfhFmax(const Instruction* instruction) {
   RiscVZfhBinaryHelper<HalfFP, float>(instruction,
                                       [](float a, float b) -> float {
                                         // On ARM std::fmaxf returns NaN if
@@ -844,14 +844,14 @@
 
 // Calculate the square root of a half precision value. Do the operation in
 // single precision and then convert back to half precision.
-void RiscVZfhFsqrt(const Instruction *instruction) {
+void RiscVZfhFsqrt(const Instruction* instruction) {
   RiscVZfhUnaryHelper<HalfFP, float>(
       instruction, [](float a) -> float { return std::sqrt(a); });
 }
 
 // The result is the exponent and significand of the first source with the
 // sign bit of the second source.
-void RiscVZfhFsgnj(const Instruction *instruction) {
+void RiscVZfhFsgnj(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, HalfFP, HalfFP>(
       instruction, [](HalfFP a, HalfFP b) -> HalfFP {
         uint16_t mask =
@@ -863,7 +863,7 @@
 
 // The result is the exponent and significand of the first source with the
 // opposite sign bit of the second source.
-void RiscVZfhFsgnjn(const Instruction *instruction) {
+void RiscVZfhFsgnjn(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, HalfFP, HalfFP>(
       instruction, [](HalfFP a, HalfFP b) -> HalfFP {
         uint16_t mask =
@@ -875,7 +875,7 @@
 
 // The result is the exponent and significand of the first source with the
 // sign bit that is the exclusive or of the two source sign bits.
-void RiscVZfhFsgnjx(const Instruction *instruction) {
+void RiscVZfhFsgnjx(const Instruction* instruction) {
   RiscVBinaryFloatNaNBoxOp<RVFpRegister::ValueType, HalfFP, HalfFP>(
       instruction, [](HalfFP a, HalfFP b) -> HalfFP {
         uint16_t mask =
@@ -887,7 +887,7 @@
 
 // Fused multiply add in half precision. Do the operation in single precision.
 // (rs1 * rs2) + rs3
-void RiscVZfhFmadd(const Instruction *instruction) {
+void RiscVZfhFmadd(const Instruction* instruction) {
   RiscVZfhTernaryHelper<HalfFP, float>(
       instruction,
       [](float a, float b, float c) -> float { return fma(a, b, c); });
@@ -895,7 +895,7 @@
 
 // Fused multiply add in half precision. Do the operation in single precision.
 // (rs1 * rs2) - rs3
-void RiscVZfhFmsub(const Instruction *instruction) {
+void RiscVZfhFmsub(const Instruction* instruction) {
   RiscVZfhTernaryHelper<HalfFP, float>(
       instruction,
       [](float a, float b, float c) -> float { return fma(a, b, -c); });
@@ -903,7 +903,7 @@
 
 // Fused multiply add in half precision. Do the operation in single precision.
 // -(rs1 * rs2) - rs3
-void RiscVZfhFnmadd(const Instruction *instruction) {
+void RiscVZfhFnmadd(const Instruction* instruction) {
   RiscVZfhTernaryHelper<HalfFP, float>(
       instruction,
       [](float a, float b, float c) -> float { return fma(-a, b, -c); });
@@ -911,27 +911,27 @@
 
 // Fused multiply add in half precision. Do the operation in single precision.
 // -(rs1 * rs2) + rs3
-void RiscVZfhFnmsub(const Instruction *instruction) {
+void RiscVZfhFnmsub(const Instruction* instruction) {
   RiscVZfhTernaryHelper<HalfFP, float>(
       instruction,
       [](float a, float b, float c) -> float { return fma(-a, b, c); });
 }
 
 // Convert from signed 32 bit integer to half precision.
-void RiscVZfhCvtHw(const Instruction *instruction) {
+void RiscVZfhCvtHw(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, int32_t>(
       instruction,
-      [](int32_t a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      [](int32_t a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         float input_float = static_cast<float>(a);
         return ConvertToHalfFP(input_float, rm, fflags);
       });
 }
 
 // Convert from unsigned 32 bit integer to half precision.
-void RiscVZfhCvtHwu(const Instruction *instruction) {
+void RiscVZfhCvtHwu(const Instruction* instruction) {
   RiscVZfhCvtHelper<HalfFP, uint32_t>(
       instruction,
-      [](uint32_t a, FPRoundingMode rm, uint32_t &fflags) -> HalfFP {
+      [](uint32_t a, FPRoundingMode rm, uint32_t& fflags) -> HalfFP {
         float input_float = static_cast<float>(a);
         return ConvertToHalfFP(input_float, rm, fflags);
       });
@@ -939,8 +939,8 @@
 
 // TODO(b/409778536): Factor out generic unimplemented instruction semantic
 //                    function.
-void RV32VUnimplementedInstruction(const Instruction *instruction) {
-  auto *state = static_cast<RiscVState *>(instruction->state());
+void RV32VUnimplementedInstruction(const Instruction* instruction) {
+  auto* state = static_cast<RiscVState*>(instruction->state());
   state->Trap(/*is_interrupt*/ false, /*trap_value*/ 0,
               *ExceptionCode::kIllegalInstruction,
               /*epc*/ instruction->address(), instruction);
diff --git a/riscv/riscv_zfh_instructions.h b/riscv/riscv_zfh_instructions.h
index 576d7f2..f26f889 100644
--- a/riscv/riscv_zfh_instructions.h
+++ b/riscv/riscv_zfh_instructions.h
@@ -30,13 +30,13 @@
 //   frs1: Float Register
 // Destination Operands:
 //   rd: Integer Register
-void RiscVZfhFMvxh(const Instruction *instruction);
+void RiscVZfhFMvxh(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFMvhx(const Instruction *instruction);
+void RiscVZfhFMvhx(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -44,7 +44,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtWh(const Instruction *instruction);
+void RiscVZfhCvtWh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -52,7 +52,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtWuh(const Instruction *instruction);
+void RiscVZfhCvtWuh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -60,7 +60,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmpeq(const Instruction *instruction);
+void RiscVZfhFcmpeq(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -68,7 +68,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmplt(const Instruction *instruction);
+void RiscVZfhFcmplt(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -76,13 +76,13 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmple(const Instruction *instruction);
+void RiscVZfhFcmple(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
 // Destination Operands:
 //   rd: Integer Register
-void RiscVZfhFclass(const Instruction *instruction);
+void RiscVZfhFclass(const Instruction* instruction);
 
 }  // namespace RV32
 
@@ -91,13 +91,13 @@
 //   frs1: Float Register
 // Destination Operands:
 //   rd: Integer Register
-void RiscVZfhFMvxh(const Instruction *instruction);
+void RiscVZfhFMvxh(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFMvhx(const Instruction *instruction);
+void RiscVZfhFMvhx(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -105,7 +105,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtWh(const Instruction *instruction);
+void RiscVZfhCvtWh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -113,7 +113,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtWuh(const Instruction *instruction);
+void RiscVZfhCvtWuh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -121,7 +121,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmpeq(const Instruction *instruction);
+void RiscVZfhFcmpeq(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -129,7 +129,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmplt(const Instruction *instruction);
+void RiscVZfhFcmplt(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -137,13 +137,13 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFcmple(const Instruction *instruction);
+void RiscVZfhFcmple(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
 // Destination Operands:
 //   rd: Integer Register
-void RiscVZfhFclass(const Instruction *instruction);
+void RiscVZfhFclass(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -151,7 +151,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtLh(const Instruction *instruction);
+void RiscVZfhCvtLh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -159,7 +159,7 @@
 // Destination Operands:
 //   rd: Integer Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtLuh(const Instruction *instruction);
+void RiscVZfhCvtLuh(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
@@ -167,7 +167,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHl(const Instruction *instruction);
+void RiscVZfhCvtHl(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
@@ -175,14 +175,14 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHlu(const Instruction *instruction);
+void RiscVZfhCvtHlu(const Instruction* instruction);
 
 }  // namespace RV64
 
 // Source Operands: *none*
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFlhChild(const Instruction *instruction);
+void RiscVZfhFlhChild(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -190,7 +190,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtSh(const Instruction *instruction);
+void RiscVZfhCvtSh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -198,7 +198,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHs(const Instruction *instruction);
+void RiscVZfhCvtHs(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -206,7 +206,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtDh(const Instruction *instruction);
+void RiscVZfhCvtDh(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -214,11 +214,11 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHd(const Instruction *instruction);
+void RiscVZfhCvtHd(const Instruction* instruction);
 
 // TODO(b/409778536): Factor out generic unimplemented instruction semantic
 //                    function.
-void RV32VUnimplementedInstruction(const Instruction *instruction);
+void RV32VUnimplementedInstruction(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -227,7 +227,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFadd(const Instruction *instruction);
+void RiscVZfhFadd(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -236,7 +236,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFsub(const Instruction *instruction);
+void RiscVZfhFsub(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -245,7 +245,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFmul(const Instruction *instruction);
+void RiscVZfhFmul(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -254,7 +254,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFdiv(const Instruction *instruction);
+void RiscVZfhFdiv(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -263,7 +263,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFmin(const Instruction *instruction);
+void RiscVZfhFmin(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -272,28 +272,28 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFmax(const Instruction *instruction);
+void RiscVZfhFmax(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
 //   frs2: Float Register
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFsgnj(const Instruction *instruction);
+void RiscVZfhFsgnj(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
 //   frs2: Float Register
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFsgnjn(const Instruction *instruction);
+void RiscVZfhFsgnjn(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
 //   frs2: Float Register
 // Destination Operands:
 //   frd: Float Register
-void RiscVZfhFsgnjx(const Instruction *instruction);
+void RiscVZfhFsgnjx(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -301,7 +301,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFsqrt(const Instruction *instruction);
+void RiscVZfhFsqrt(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -311,7 +311,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFmadd(const Instruction *instruction);
+void RiscVZfhFmadd(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -321,7 +321,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFmsub(const Instruction *instruction);
+void RiscVZfhFmsub(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -331,7 +331,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFnmadd(const Instruction *instruction);
+void RiscVZfhFnmadd(const Instruction* instruction);
 
 // Source Operands:
 //   frs1: Float Register
@@ -341,7 +341,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhFnmsub(const Instruction *instruction);
+void RiscVZfhFnmsub(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
@@ -349,7 +349,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHw(const Instruction *instruction);
+void RiscVZfhCvtHw(const Instruction* instruction);
 
 // Source Operands:
 //   rs1: Integer Register
@@ -357,7 +357,7 @@
 // Destination Operands:
 //   frd: Float Register
 //   fflags: Accrued Exception Flags field in FCSR
-void RiscVZfhCvtHwu(const Instruction *instruction);
+void RiscVZfhCvtHwu(const Instruction* instruction);
 
 }  // namespace riscv
 }  // namespace sim
diff --git a/riscv/riscv_zhintpause_instructions.cc b/riscv/riscv_zhintpause_instructions.cc
index 0421184..1725634 100644
--- a/riscv/riscv_zhintpause_instructions.cc
+++ b/riscv/riscv_zhintpause_instructions.cc
@@ -6,6 +6,6 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVPause(const Instruction *inst) { /* empty */ }
+void RiscVPause(const Instruction* inst) { /* empty */ }
 
 }  // namespace mpact::sim::riscv
diff --git a/riscv/riscv_zhintpause_instructions.h b/riscv/riscv_zhintpause_instructions.h
index e682d10..35f9e19 100644
--- a/riscv/riscv_zhintpause_instructions.h
+++ b/riscv/riscv_zhintpause_instructions.h
@@ -25,7 +25,7 @@
 using ::mpact::sim::generic::Instruction;
 
 // This instruction semantic function takes no source or destination operands.
-void RiscVPause(const Instruction *inst);
+void RiscVPause(const Instruction* inst);
 
 }  // namespace mpact::sim::riscv
 
diff --git a/riscv/riscv_zicbop_instructions.cc b/riscv/riscv_zicbop_instructions.cc
index e8a68e3..66269e4 100644
--- a/riscv/riscv_zicbop_instructions.cc
+++ b/riscv/riscv_zicbop_instructions.cc
@@ -27,18 +27,18 @@
 namespace RV32 {
 
 // These instructions are not implemented for now.
-void RiscVPrefetchI(const Instruction *inst) { /* empty */ }
-void RiscVPrefetchR(const Instruction *inst) { /* empty */ }
-void RiscVPrefetchW(const Instruction *inst) { /* empty */ }
+void RiscVPrefetchI(const Instruction* inst) { /* empty */ }
+void RiscVPrefetchR(const Instruction* inst) { /* empty */ }
+void RiscVPrefetchW(const Instruction* inst) { /* empty */ }
 
 }  // namespace RV32
 
 namespace RV64 {
 
 // These instructions are not implemented for now.
-void RiscVPrefetchI(const Instruction *inst) { /* empty */ }
-void RiscVPrefetchR(const Instruction *inst) { /* empty */ }
-void RiscVPrefetchW(const Instruction *inst) { /* empty */ }
+void RiscVPrefetchI(const Instruction* inst) { /* empty */ }
+void RiscVPrefetchR(const Instruction* inst) { /* empty */ }
+void RiscVPrefetchW(const Instruction* inst) { /* empty */ }
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_zicbop_instructions.h b/riscv/riscv_zicbop_instructions.h
index f603a37..6b5ba37 100644
--- a/riscv/riscv_zicbop_instructions.h
+++ b/riscv/riscv_zicbop_instructions.h
@@ -28,9 +28,9 @@
 
 // Each of these instructions take two source operands, rs1 and a 12 bit
 // immediate offset.
-void RiscVPrefetchI(const Instruction *inst);
-void RiscVPrefetchR(const Instruction *inst);
-void RiscVPrefetchW(const Instruction *inst);
+void RiscVPrefetchI(const Instruction* inst);
+void RiscVPrefetchR(const Instruction* inst);
+void RiscVPrefetchW(const Instruction* inst);
 
 }  // namespace RV32
 
@@ -38,9 +38,9 @@
 
 // Each of these instructions take two source operands, rs1 and a 12 bit
 // immediate offset.
-void RiscVPrefetchI(const Instruction *inst);
-void RiscVPrefetchR(const Instruction *inst);
-void RiscVPrefetchW(const Instruction *inst);
+void RiscVPrefetchI(const Instruction* inst);
+void RiscVPrefetchR(const Instruction* inst);
+void RiscVPrefetchW(const Instruction* inst);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_zicond_instructions.cc b/riscv/riscv_zicond_instructions.cc
index a81bccd..9db5ad0 100644
--- a/riscv/riscv_zicond_instructions.cc
+++ b/riscv/riscv_zicond_instructions.cc
@@ -27,14 +27,14 @@
 
 // If rs2 is zero, set the destination register to 0, otherwise copy rs1 to
 // the destination register.
-void RiscVCzeroEqz(const generic::Instruction *inst) {
+void RiscVCzeroEqz(const generic::Instruction* inst) {
   RiscVBinaryOp<RegType, RegValue, RegValue>(
       inst, [](RegValue rs1, RegValue rs2) { return rs2 == 0 ? 0 : rs1; });
 }
 
 // If rs2 is non-zero, set the destination register to 0, otherwise copy rs1 to
 // the destination register.
-void RiscVCzeroNez(const generic::Instruction *inst) {
+void RiscVCzeroNez(const generic::Instruction* inst) {
   RiscVBinaryOp<RegType, RegValue, RegValue>(
       inst, [](RegValue rs1, RegValue rs2) { return rs2 != 0 ? 0 : rs1; });
 }
@@ -48,14 +48,14 @@
 
 // If rs2 is zero, set the destination register to 0, otherwise copy rs1 to
 // the destination register.
-void RiscVCzeroEqz(const generic::Instruction *inst) {
+void RiscVCzeroEqz(const generic::Instruction* inst) {
   RiscVBinaryOp<RegType, RegValue, RegValue>(
       inst, [](RegValue rs1, RegValue rs2) { return rs2 == 0 ? 0 : rs1; });
 }
 
 // If rs2 is non-zero, set the destination register to 0, otherwise copy rs1 to
 // the destination register.
-void RiscVCzeroNez(const generic::Instruction *inst) {
+void RiscVCzeroNez(const generic::Instruction* inst) {
   RiscVBinaryOp<RegType, RegValue, RegValue>(
       inst, [](RegValue rs1, RegValue rs2) { return rs2 != 0 ? 0 : rs1; });
 }
diff --git a/riscv/riscv_zicond_instructions.h b/riscv/riscv_zicond_instructions.h
index f70b85b..5078b5c 100644
--- a/riscv/riscv_zicond_instructions.h
+++ b/riscv/riscv_zicond_instructions.h
@@ -28,15 +28,15 @@
 
 namespace RV32 {
 
-void RiscVCzeroEqz(const Instruction *inst);
-void RiscVCzeroNez(const Instruction *inst);
+void RiscVCzeroEqz(const Instruction* inst);
+void RiscVCzeroNez(const Instruction* inst);
 
 }  // namespace RV32
 
 namespace RV64 {
 
-void RiscVCzeroEqz(const Instruction *inst);
-void RiscVCzeroNez(const Instruction *inst);
+void RiscVCzeroEqz(const Instruction* inst);
+void RiscVCzeroNez(const Instruction* inst);
 
 }  // namespace RV64
 
diff --git a/riscv/riscv_zicsr_instructions.cc b/riscv/riscv_zicsr_instructions.cc
index b349f05..323b1f7 100644
--- a/riscv/riscv_zicsr_instructions.cc
+++ b/riscv/riscv_zicsr_instructions.cc
@@ -32,22 +32,22 @@
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
 template <typename T>
-inline T ReadCsr(RiscVCsrInterface *) {}
+inline T ReadCsr(RiscVCsrInterface*) {}
 
 template <>
-inline uint32_t ReadCsr<uint32_t>(RiscVCsrInterface *csr) {
+inline uint32_t ReadCsr<uint32_t>(RiscVCsrInterface* csr) {
   return csr->AsUint32();
 }
 template <>
-inline uint64_t ReadCsr<uint64_t>(RiscVCsrInterface *csr) {
+inline uint64_t ReadCsr<uint64_t>(RiscVCsrInterface* csr) {
   return csr->AsUint64();
 }
 
 // Helper function to check that the CSR permission is valid. If not, throw
 // an illegal instruction exception.
-bool CheckCsrPermission(int csr_index, Instruction *instruction) {
+bool CheckCsrPermission(int csr_index, Instruction* instruction) {
   auto required_mode = (csr_index >> 8) & 0x3;
-  auto *state = static_cast<RiscVState *>(instruction->state());
+  auto* state = static_cast<RiscVState*>(instruction->state());
   auto current_mode = state->privilege_mode();
   // If the privilege mode is too low, throw an exception.
   if (*current_mode < required_mode) {
@@ -70,9 +70,9 @@
 
 // Read the CSR, write a new value back.
 template <typename T>
-static inline void RVZiCsrrw(Instruction *instruction) {
+static inline void RVZiCsrrw(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<RiscVState *>(instruction->state());
+  auto state = static_cast<RiscVState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction)) return;
@@ -88,9 +88,9 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Update the register.
-  auto *reg = static_cast<generic::RegisterDestinationOperand<T> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<T>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<T>(0, ReadCsr<T>(csr));
@@ -100,9 +100,9 @@
 
 // Read the CSR, set the bits specified by the new value and write back.
 template <typename T>
-static inline void RVZiCsrrs(Instruction *instruction) {
+static inline void RVZiCsrrs(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<RiscVState *>(instruction->state());
+  auto state = static_cast<RiscVState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction)) return;
@@ -118,9 +118,9 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Update the register.
-  auto *reg = static_cast<generic::RegisterDestinationOperand<T> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<T>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<T>(0, ReadCsr<T>(csr));
@@ -130,9 +130,9 @@
 
 // Read the CSR, clear the bits specified by the new value and write back.
 template <typename T>
-static inline void RVZiCsrrc(Instruction *instruction) {
+static inline void RVZiCsrrc(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<RiscVState *>(instruction->state());
+  auto state = static_cast<RiscVState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction)) return;
@@ -148,9 +148,9 @@
   }
   // Get the new value.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Write the current value of the CSR to the destination register.
-  auto *reg = static_cast<generic::RegisterDestinationOperand<T> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<T>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   auto csr_val = ReadCsr<T>(csr);
@@ -161,9 +161,9 @@
 
 // Do not read the CSR, just write the new value back.
 template <typename T>
-static inline void RVZiCsrrwNr(Instruction *instruction) {
+static inline void RVZiCsrrwNr(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<RiscVState *>(instruction->state());
+  auto state = static_cast<RiscVState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(1)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction)) return;
@@ -176,7 +176,7 @@
                                ": ", result.status().message());
     return;
   }
-  auto *csr = result.value();
+  auto* csr = result.value();
   // Write the new value to the csr.
   T new_value = generic::GetInstructionSource<T>(instruction, 0);
   csr->Write(new_value);
@@ -184,9 +184,9 @@
 
 // Do not write a value back to the CSR, just read it.
 template <typename T>
-static inline void RVZiCsrrNw(Instruction *instruction) {
+static inline void RVZiCsrrNw(Instruction* instruction) {
   // Get a handle to the state instance.
-  auto state = static_cast<RiscVState *>(instruction->state());
+  auto state = static_cast<RiscVState*>(instruction->state());
   // Get the csr index.
   int csr_index = instruction->Source(0)->AsInt32(0);
   if (!CheckCsrPermission(csr_index, instruction)) return;
@@ -200,8 +200,8 @@
     return;
   }
   // Get the CSR object.
-  auto *csr = result.value();
-  auto *reg = static_cast<generic::RegisterDestinationOperand<T> *>(
+  auto* csr = result.value();
+  auto* reg = static_cast<generic::RegisterDestinationOperand<T>*>(
                   instruction->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<T>(0, ReadCsr<T>(csr));
@@ -213,21 +213,21 @@
 using UintReg = RegisterType::ValueType;
 
 // Read the CSR, write a new value back.
-void RiscVZiCsrrw(Instruction *instruction) { RVZiCsrrw<UintReg>(instruction); }
+void RiscVZiCsrrw(Instruction* instruction) { RVZiCsrrw<UintReg>(instruction); }
 
 // Read the CSR, set the bits specified by the new value and write back.
-void RiscVZiCsrrs(Instruction *instruction) { RVZiCsrrs<UintReg>(instruction); }
+void RiscVZiCsrrs(Instruction* instruction) { RVZiCsrrs<UintReg>(instruction); }
 
 // Read the CSR, clear the bits specified by the new value and write back.
-void RiscVZiCsrrc(Instruction *instruction) { RVZiCsrrc<UintReg>(instruction); }
+void RiscVZiCsrrc(Instruction* instruction) { RVZiCsrrc<UintReg>(instruction); }
 
 // Do not read the CSR, just write the new value back.
-void RiscVZiCsrrwNr(Instruction *instruction) {
+void RiscVZiCsrrwNr(Instruction* instruction) {
   RVZiCsrrwNr<UintReg>(instruction);
 }
 
 // Do not write a value back to the CSR, just read it.
-void RiscVZiCsrrNw(Instruction *instruction) {
+void RiscVZiCsrrNw(Instruction* instruction) {
   RVZiCsrrNw<UintReg>(instruction);
 }
 
@@ -239,21 +239,21 @@
 using UintReg = RegisterType::ValueType;
 
 // Read the CSR, write a new value back.
-void RiscVZiCsrrw(Instruction *instruction) { RVZiCsrrw<UintReg>(instruction); }
+void RiscVZiCsrrw(Instruction* instruction) { RVZiCsrrw<UintReg>(instruction); }
 
 // Read the CSR, set the bits specified by the new value and write back.
-void RiscVZiCsrrs(Instruction *instruction) { RVZiCsrrs<UintReg>(instruction); }
+void RiscVZiCsrrs(Instruction* instruction) { RVZiCsrrs<UintReg>(instruction); }
 
 // Read the CSR, clear the bits specified by the new value and write back.
-void RiscVZiCsrrc(Instruction *instruction) { RVZiCsrrc<UintReg>(instruction); }
+void RiscVZiCsrrc(Instruction* instruction) { RVZiCsrrc<UintReg>(instruction); }
 
 // Do not read the CSR, just write the new value back.
-void RiscVZiCsrrwNr(Instruction *instruction) {
+void RiscVZiCsrrwNr(Instruction* instruction) {
   RVZiCsrrwNr<UintReg>(instruction);
 }
 
 // Do not write a value back to the CSR, just read it.
-void RiscVZiCsrrNw(Instruction *instruction) {
+void RiscVZiCsrrNw(Instruction* instruction) {
   RVZiCsrrNw<UintReg>(instruction);
 }
 
diff --git a/riscv/riscv_zicsr_instructions.h b/riscv/riscv_zicsr_instructions.h
index 729186c..3d7b9f8 100644
--- a/riscv/riscv_zicsr_instructions.h
+++ b/riscv/riscv_zicsr_instructions.h
@@ -24,19 +24,19 @@
 using ::mpact::sim::generic::Instruction;
 
 namespace RV32 {
-void RiscVZiCsrrw(Instruction *instruction);
-void RiscVZiCsrrs(Instruction *instruction);
-void RiscVZiCsrrc(Instruction *instruction);
-void RiscVZiCsrrwNr(Instruction *instruction);
-void RiscVZiCsrrNw(Instruction *instruction);
+void RiscVZiCsrrw(Instruction* instruction);
+void RiscVZiCsrrs(Instruction* instruction);
+void RiscVZiCsrrc(Instruction* instruction);
+void RiscVZiCsrrwNr(Instruction* instruction);
+void RiscVZiCsrrNw(Instruction* instruction);
 }  // namespace RV32
 
 namespace RV64 {
-void RiscVZiCsrrw(Instruction *instruction);
-void RiscVZiCsrrs(Instruction *instruction);
-void RiscVZiCsrrc(Instruction *instruction);
-void RiscVZiCsrrwNr(Instruction *instruction);
-void RiscVZiCsrrNw(Instruction *instruction);
+void RiscVZiCsrrw(Instruction* instruction);
+void RiscVZiCsrrs(Instruction* instruction);
+void RiscVZiCsrrc(Instruction* instruction);
+void RiscVZiCsrrwNr(Instruction* instruction);
+void RiscVZiCsrrNw(Instruction* instruction);
 }  // namespace RV64
 
 }  // namespace riscv
diff --git a/riscv/riscv_zihintntl_instructions.cc b/riscv/riscv_zihintntl_instructions.cc
index 802139f..5049fc1 100644
--- a/riscv/riscv_zihintntl_instructions.cc
+++ b/riscv/riscv_zihintntl_instructions.cc
@@ -6,9 +6,9 @@
 
 using ::mpact::sim::generic::Instruction;
 
-void RiscVNtlP1(const Instruction *) { /* empty */ }
-void RiscVNtlPall(const Instruction *) { /* empty */ }
-void RiscVNtlS1(const Instruction *) { /* empty */ }
-void RiscVNtlAll(const Instruction *) { /* empty */ }
+void RiscVNtlP1(const Instruction*) { /* empty */ }
+void RiscVNtlPall(const Instruction*) { /* empty */ }
+void RiscVNtlS1(const Instruction*) { /* empty */ }
+void RiscVNtlAll(const Instruction*) { /* empty */ }
 
 }  // namespace mpact::sim::riscv
diff --git a/riscv/riscv_zihintntl_instructions.h b/riscv/riscv_zihintntl_instructions.h
index e08bd1f..b6589be 100644
--- a/riscv/riscv_zihintntl_instructions.h
+++ b/riscv/riscv_zihintntl_instructions.h
@@ -25,10 +25,10 @@
 using ::mpact::sim::generic::Instruction;
 
 // These instructions take no source or destination operands.
-void RiscVNtlP1(const Instruction *);
-void RiscVNtlPall(const Instruction *);
-void RiscVNtlS1(const Instruction *);
-void RiscVNtlAll(const Instruction *);
+void RiscVNtlP1(const Instruction*);
+void RiscVNtlPall(const Instruction*);
+void RiscVNtlS1(const Instruction*);
+void RiscVNtlAll(const Instruction*);
 
 }  // namespace mpact::sim::riscv
 
diff --git a/riscv/riscv_zimop_instructions.cc b/riscv/riscv_zimop_instructions.cc
index 27b3810..133b77b 100644
--- a/riscv/riscv_zimop_instructions.cc
+++ b/riscv/riscv_zimop_instructions.cc
@@ -27,9 +27,9 @@
 using RegType = RV32Register;
 using RegValue = typename RegType::ValueType;
 
-void RiscVMop(const Instruction *inst) {
+void RiscVMop(const Instruction* inst) {
   // Get the destination register and set it to zero.
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   inst->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<RegValue>(0, 0);
@@ -42,9 +42,9 @@
 using RegType = RV64Register;
 using RegValue = typename RegType::ValueType;
 
-void RiscVMop(const Instruction *inst) {
+void RiscVMop(const Instruction* inst) {
   // Get the destination register and set it to zero.
-  auto *reg = static_cast<generic::RegisterDestinationOperand<RegValue> *>(
+  auto* reg = static_cast<generic::RegisterDestinationOperand<RegValue>*>(
                   inst->Destination(0))
                   ->GetRegister();
   reg->data_buffer()->template Set<RegValue>(0, 0);
diff --git a/riscv/riscv_zimop_instructions.h b/riscv/riscv_zimop_instructions.h
index ee0e3c2..d7a21ac 100644
--- a/riscv/riscv_zimop_instructions.h
+++ b/riscv/riscv_zimop_instructions.h
@@ -27,7 +27,7 @@
 
 // This semantic function ignores the source operand(s) and takes one
 // destination operand.
-void RiscVMop(const Instruction *inst);
+void RiscVMop(const Instruction* inst);
 
 }  // namespace RV32
 
@@ -35,7 +35,7 @@
 
 // This semantic function ignores the source operand(s) and takes one
 // destination operand.
-void RiscVMop(const Instruction *inst);
+void RiscVMop(const Instruction* inst);
 
 }  // namespace RV64
 
diff --git a/riscv/rv32g_sim.cc b/riscv/rv32g_sim.cc
index 36e945e..e246cc7 100644
--- a/riscv/rv32g_sim.cc
+++ b/riscv/rv32g_sim.cc
@@ -160,7 +160,7 @@
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
 // Static pointer to the top instance. Used by the control-C handler.
-static mpact::sim::riscv::RiscVTop *top = nullptr;
+static mpact::sim::riscv::RiscVTop* top = nullptr;
 
 // Control-c handler to interrupt any running simulation.
 static void sim_sigint_handler(int arg) {
@@ -175,8 +175,8 @@
 using ::mpact::sim::riscv::RiscVTop;
 
 // Helper function to get the magic semihosting addresses from the loader.
-static bool GetMagicAddresses(mpact::sim::util::ElfProgramLoader *loader,
-                              RiscV32HtifSemiHost::SemiHostAddresses *magic) {
+static bool GetMagicAddresses(mpact::sim::util::ElfProgramLoader* loader,
+                              RiscV32HtifSemiHost::SemiHostAddresses* magic) {
   auto result = loader->GetSymbol("tohost_ready");
   if (!result.ok()) return false;
   magic->tohost_ready = result.value().first;
@@ -200,8 +200,8 @@
 // debug command shell.
 static bool PrintRegisters(
     absl::string_view input,
-    const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    const mpact::sim::riscv::DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   static const LazyRE2 reg_info_re{R"(\s*xyzreg\s+info\s*)"};
   if (!RE2::FullMatch(input, *reg_info_re)) {
     return false;
@@ -222,7 +222,7 @@
   return true;
 }
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   int return_code = 0;
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
@@ -244,9 +244,9 @@
       full_file_name.substr(full_file_name.find_last_of('/') + 1);
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
-  auto *memory = new mpact::sim::util::FlatDemandMemory();
-  mpact::sim::util::MemoryWatcher *memory_watcher = nullptr;
-  mpact::sim::util::AtomicMemory *atomic_memory = nullptr;
+  auto* memory = new mpact::sim::util::FlatDemandMemory();
+  mpact::sim::util::MemoryWatcher* memory_watcher = nullptr;
+  mpact::sim::util::AtomicMemory* atomic_memory = nullptr;
   if (absl::GetFlag(FLAGS_exit_on_tohost)) {
     memory_watcher = new mpact::sim::util::MemoryWatcher(memory);
     atomic_memory = new mpact::sim::util::AtomicMemory(memory_watcher);
@@ -262,7 +262,7 @@
     return -1;
   }
 
-  mpact::sim::util::MemoryInterface *memory_interface = memory;
+  mpact::sim::util::MemoryInterface* memory_interface = memory;
   if (memory_watcher != nullptr) {
     memory_interface = memory_watcher;
   }
@@ -273,7 +273,7 @@
   RiscVFPState rv_fp_state(rv_state.csr_set(), &rv_state);
   rv_state.set_rv_fp(&rv_fp_state);
   // Create the instruction decoder.
-  mpact::sim::generic::DecoderInterface *rv_decoder = nullptr;
+  mpact::sim::generic::DecoderInterface* rv_decoder = nullptr;
   if (absl::GetFlag(FLAGS_bitmanip)) {
     rv_decoder = new RiscV32GBitmanipDecoder(&rv_state, memory);
   } else {
@@ -301,7 +301,7 @@
     ComponentValueEntry icache_value;
     icache_value.set_name("icache");
     icache_value.set_string_value(absl::GetFlag(FLAGS_icache));
-    auto *cfg = riscv_top.GetConfig("icache");
+    auto* cfg = riscv_top.GetConfig("icache");
     auto status = cfg->Import(&icache_value);
     if (!status.ok()) return -1;
   }
@@ -310,17 +310,17 @@
     ComponentValueEntry dcache_value;
     dcache_value.set_name("dcache");
     dcache_value.set_string_value(absl::GetFlag(FLAGS_dcache));
-    auto *cfg = riscv_top.GetConfig("dcache");
+    auto* cfg = riscv_top.GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return -1;
     // Hook the cache into the memory port.
-    auto *dcache = riscv_top.dcache();
+    auto* dcache = riscv_top.dcache();
     dcache->set_memory(riscv_top.state()->memory());
     riscv_top.state()->set_memory(dcache);
   }
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
-    rv_state.set_on_ecall([&riscv_top](const Instruction *inst) -> bool {
+    rv_state.set_on_ecall([&riscv_top](const Instruction* inst) -> bool {
       riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, inst);
       return true;
     });
@@ -334,7 +334,7 @@
           [&riscv_top, tohost_addr, memory, &rv_state, &return_code, quiet](
               uint64_t, int) -> void {
             riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, nullptr);
-            auto *db = rv_state.db_factory()->Allocate<uint32_t>(1);
+            auto* db = rv_state.db_factory()->Allocate<uint32_t>(1);
             memory->Load(tohost_addr, db, nullptr, nullptr);
             auto word = db->Get<uint32_t>(0);
             db->DecRef();
@@ -413,7 +413,7 @@
     }
   }
 
-  RiscV32HtifSemiHost *htif_semihost = nullptr;
+  RiscV32HtifSemiHost* htif_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_htif)) {
     // Add htif semihosting.
     RiscV32HtifSemiHost::SemiHostAddresses magic_addresses;
@@ -435,14 +435,14 @@
     }
   }
 
-  RiscVArmSemihost *arm_semihost = nullptr;
+  RiscVArmSemihost* arm_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_arm)) {
     // Add ARM semihosting.
     arm_semihost = new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord32,
                                         memory, memory);
     arm_semihost->SetCmdLine(arg_vec);
     riscv_top.state()->AddEbreakHandler(
-        [arm_semihost](const Instruction *inst) -> bool {
+        [arm_semihost](const Instruction* inst) -> bool {
           if (arm_semihost->IsSemihostingCall(inst)) {
             arm_semihost->OnEBreak(inst);
             return true;
diff --git a/riscv/rv32g_test_sim.cc b/riscv/rv32g_test_sim.cc
index 00dac5e..15d6d6d 100644
--- a/riscv/rv32g_test_sim.cc
+++ b/riscv/rv32g_test_sim.cc
@@ -60,7 +60,7 @@
 ABSL_FLAG(std::optional<std::string>, dump_signature, std::nullopt,
           "Dump signature file name (riscv torture test)");
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
   if (arg_vec.size() > 2) {
@@ -73,8 +73,8 @@
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
   mpact::sim::util::FlatDemandMemory memory;
-  auto *watcher = new mpact::sim::util::MemoryWatcher(&memory);
-  auto *atomic_memory = new mpact::sim::util::AtomicMemory(watcher);
+  auto* watcher = new mpact::sim::util::MemoryWatcher(&memory);
+  auto* atomic_memory = new mpact::sim::util::AtomicMemory(watcher);
   // Load the elf segments into memory.
   mpact::sim::util::ElfProgramLoader elf_loader(&memory);
   auto load_result = elf_loader.LoadProgram(full_file_name);
@@ -190,7 +190,7 @@
       uint64_t begin_sig = begin_res.value().first;
       uint64_t end_sig = end_res.value().first;
       uint64_t length = end_sig - begin_sig;
-      uint64_t *buffer = new uint64_t[length >> 3];
+      uint64_t* buffer = new uint64_t[length >> 3];
       auto status = riscv_top.ReadMemory(begin_sig, buffer, length);
       for (int i = 0; i < length >> 3; ++i) {
         sig_file << std::hex << buffer[i] << std::endl;
diff --git a/riscv/rv32gv_sim.cc b/riscv/rv32gv_sim.cc
index c5b1cd3..cac54a3 100644
--- a/riscv/rv32gv_sim.cc
+++ b/riscv/rv32gv_sim.cc
@@ -161,7 +161,7 @@
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
 // Static pointer to the top instance. Used by the control-C handler.
-static mpact::sim::riscv::RiscVTop *top = nullptr;
+static mpact::sim::riscv::RiscVTop* top = nullptr;
 
 // Control-c handler to interrupt any running simulation.
 static void sim_sigint_handler(int arg) {
@@ -176,8 +176,8 @@
 using ::mpact::sim::riscv::RiscVTop;
 
 // Helper function to get the magic semihosting addresses from the loader.
-static bool GetMagicAddresses(mpact::sim::util::ElfProgramLoader *loader,
-                              RiscV32HtifSemiHost::SemiHostAddresses *magic) {
+static bool GetMagicAddresses(mpact::sim::util::ElfProgramLoader* loader,
+                              RiscV32HtifSemiHost::SemiHostAddresses* magic) {
   auto result = loader->GetSymbol("tohost_ready");
   if (!result.ok()) return false;
   magic->tohost_ready = result.value().first;
@@ -201,8 +201,8 @@
 // debug command shell.
 static bool PrintRegisters(
     absl::string_view input,
-    const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    const mpact::sim::riscv::DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   static const LazyRE2 reg_info_re{R"(\s*xyzreg\s+info\s*)"};
   if (!RE2::FullMatch(input, *reg_info_re)) {
     return false;
@@ -223,7 +223,7 @@
   return true;
 }
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   int return_code = 0;
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
@@ -245,9 +245,9 @@
       full_file_name.substr(full_file_name.find_last_of('/') + 1);
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
-  auto *memory = new mpact::sim::util::FlatDemandMemory();
-  mpact::sim::util::MemoryWatcher *memory_watcher = nullptr;
-  mpact::sim::util::AtomicMemory *atomic_memory = nullptr;
+  auto* memory = new mpact::sim::util::FlatDemandMemory();
+  mpact::sim::util::MemoryWatcher* memory_watcher = nullptr;
+  mpact::sim::util::AtomicMemory* atomic_memory = nullptr;
   if (absl::GetFlag(FLAGS_exit_on_tohost)) {
     memory_watcher = new mpact::sim::util::MemoryWatcher(memory);
     atomic_memory = new mpact::sim::util::AtomicMemory(memory_watcher);
@@ -263,7 +263,7 @@
     return -1;
   }
 
-  mpact::sim::util::MemoryInterface *memory_interface = memory;
+  mpact::sim::util::MemoryInterface* memory_interface = memory;
   if (memory_watcher != nullptr) {
     memory_interface = memory_watcher;
   }
@@ -274,7 +274,7 @@
   RiscVVectorState rvv_state(&rv_state, 16 /*vector byte length*/);
   rv_state.set_rv_fp(&rv_fp_state);
   // Create the instruction decoder.
-  mpact::sim::generic::DecoderInterface *rv_decoder = nullptr;
+  mpact::sim::generic::DecoderInterface* rv_decoder = nullptr;
   if (absl::GetFlag(FLAGS_bitmanip)) {
     rv_decoder = new RiscV32GZBVecDecoder(&rv_state, memory);
   } else {
@@ -299,7 +299,7 @@
   RiscVTop riscv_top("RiscV32GVSim", &rv_state, rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
-    rv_state.set_on_ecall([&riscv_top](const Instruction *inst) -> bool {
+    rv_state.set_on_ecall([&riscv_top](const Instruction* inst) -> bool {
       riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, inst);
       return true;
     });
@@ -314,7 +314,7 @@
           [&riscv_top, tohost_addr, memory, &rv_state, &return_code, quiet](
               uint64_t, int) -> void {
             riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, nullptr);
-            auto *db = rv_state.db_factory()->Allocate<uint32_t>(1);
+            auto* db = rv_state.db_factory()->Allocate<uint32_t>(1);
             memory->Load(tohost_addr, db, nullptr, nullptr);
             auto word = db->Get<uint32_t>(0);
             db->DecRef();
@@ -394,7 +394,7 @@
     }
   }
 
-  RiscV32HtifSemiHost *htif_semihost = nullptr;
+  RiscV32HtifSemiHost* htif_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_htif)) {
     // Add htif semihosting.
     RiscV32HtifSemiHost::SemiHostAddresses magic_addresses;
@@ -416,14 +416,14 @@
     }
   }
 
-  RiscVArmSemihost *arm_semihost = nullptr;
+  RiscVArmSemihost* arm_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_arm)) {
     // Add ARM semihosting.
     arm_semihost = new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord32,
                                         memory, memory);
     arm_semihost->SetCmdLine(arg_vec);
     riscv_top.state()->AddEbreakHandler(
-        [arm_semihost](const Instruction *inst) -> bool {
+        [arm_semihost](const Instruction* inst) -> bool {
           if (arm_semihost->IsSemihostingCall(inst)) {
             arm_semihost->OnEBreak(inst);
             return true;
diff --git a/riscv/rv64g_sim.cc b/riscv/rv64g_sim.cc
index 5f56635..d2ac4c5 100644
--- a/riscv/rv64g_sim.cc
+++ b/riscv/rv64g_sim.cc
@@ -150,7 +150,7 @@
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
 // Static pointer to the top instance. Used by the control-C handler.
-static mpact::sim::riscv::RiscVTop *top = nullptr;
+static mpact::sim::riscv::RiscVTop* top = nullptr;
 
 // Control-c handler to interrupt any running simulation.
 static void sim_sigint_handler(int arg) {
@@ -168,8 +168,8 @@
 // debug command shell.
 static bool PrintRegisters(
     absl::string_view input,
-    const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    const mpact::sim::riscv::DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   static const LazyRE2 reg_info_re{R"(\s*reg\s+info\s*)"};
   if (!RE2::FullMatch(input, *reg_info_re)) {
     return false;
@@ -190,7 +190,7 @@
   return true;
 }
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   int return_code = 0;
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
@@ -211,9 +211,9 @@
       full_file_name.substr(full_file_name.find_last_of('/') + 1);
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
-  auto *memory = new mpact::sim::util::FlatDemandMemory();
-  mpact::sim::util::MemoryWatcher *memory_watcher = nullptr;
-  mpact::sim::util::AtomicMemory *atomic_memory = nullptr;
+  auto* memory = new mpact::sim::util::FlatDemandMemory();
+  mpact::sim::util::MemoryWatcher* memory_watcher = nullptr;
+  mpact::sim::util::AtomicMemory* atomic_memory = nullptr;
   if (absl::GetFlag(FLAGS_exit_on_tohost)) {
     memory_watcher = new mpact::sim::util::MemoryWatcher(memory);
     atomic_memory = new mpact::sim::util::AtomicMemory(memory_watcher);
@@ -230,7 +230,7 @@
     return -1;
   }
 
-  mpact::sim::util::MemoryInterface *memory_interface = memory;
+  mpact::sim::util::MemoryInterface* memory_interface = memory;
   if (memory_watcher != nullptr) {
     memory_interface = memory_watcher;
   }
@@ -262,7 +262,7 @@
   RiscVTop riscv_top("RiscV32Sim", &rv_state, &rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
-    rv_state.set_on_ecall([&riscv_top](const Instruction *inst) -> bool {
+    rv_state.set_on_ecall([&riscv_top](const Instruction* inst) -> bool {
       riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, inst);
       return true;
     });
@@ -277,7 +277,7 @@
           [&riscv_top, tohost_addr, memory, &rv_state, &return_code, quiet](
               uint64_t, int) -> void {
             riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, nullptr);
-            auto *db = rv_state.db_factory()->Allocate<uint32_t>(1);
+            auto* db = rv_state.db_factory()->Allocate<uint32_t>(1);
             memory->Load(tohost_addr, db, nullptr, nullptr);
             auto word = db->Get<uint32_t>(0);
             db->DecRef();
@@ -358,14 +358,14 @@
   }
 
   // Set up arm semihosting if specified. Htif not supported for RiscV64.
-  RiscVArmSemihost *arm_semihost = nullptr;
+  RiscVArmSemihost* arm_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_arm)) {
     // Add ARM semihosting.
     arm_semihost = new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord64,
                                         memory, memory);
     arm_semihost->SetCmdLine(arg_vec);
     riscv_top.state()->AddEbreakHandler(
-        [arm_semihost](const Instruction *inst) {
+        [arm_semihost](const Instruction* inst) {
           if (arm_semihost->IsSemihostingCall(inst)) {
             arm_semihost->OnEBreak(inst);
             return true;
diff --git a/riscv/rv64g_test_sim.cc b/riscv/rv64g_test_sim.cc
index fdb67ad..c956c8d 100644
--- a/riscv/rv64g_test_sim.cc
+++ b/riscv/rv64g_test_sim.cc
@@ -65,7 +65,7 @@
 ABSL_FLAG(bool, log_commits, false, "Log commits similar to spike");
 ABSL_FLAG(int64_t, max_cycles, -1, "Max cycles to simulate");
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
   if (arg_vec.size() > 2) {
@@ -78,9 +78,9 @@
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
   mpact::sim::util::FlatDemandMemory memory;
-  auto *watcher = new mpact::sim::util::MemoryWatcher(&memory);
-  auto *test_watcher = new mpact::sim::riscv::RiscVTestMemWatcher(watcher);
-  auto *atomic_memory = new mpact::sim::util::AtomicMemory(test_watcher);
+  auto* watcher = new mpact::sim::util::MemoryWatcher(&memory);
+  auto* test_watcher = new mpact::sim::riscv::RiscVTestMemWatcher(watcher);
+  auto* atomic_memory = new mpact::sim::util::AtomicMemory(test_watcher);
   // Load the elf segments into memory.
   mpact::sim::util::ElfProgramLoader elf_loader(&memory);
   auto load_result = elf_loader.LoadProgram(full_file_name);
@@ -129,8 +129,8 @@
   bool ok = true;
   uint64_t pc = entry_point;
   bool commit_trace = absl::GetFlag(FLAGS_log_commits);
-  auto *register_map = riscv_top.state()->registers();
-  mpact::sim::generic::DataBuffer *inst_db =
+  auto* register_map = riscv_top.state()->registers();
+  mpact::sim::generic::DataBuffer* inst_db =
       riscv_top.state()->db_factory()->Allocate<uint32_t>(1);
   int64_t count = 0;
   int64_t max_count = absl::GetFlag(FLAGS_max_cycles);
@@ -148,7 +148,7 @@
     ok = true;
     if (commit_trace) {
       // This IncRef's the inst instance. Need to DecRef it when we are done.
-      auto *inst = riscv_top.GetInstruction(pc).value();
+      auto* inst = riscv_top.GetInstruction(pc).value();
       std::string trace_str;
       absl::StrAppend(
           &trace_str, "core   0: ", *(riscv_top.state()->privilege_mode()),
@@ -158,7 +158,7 @@
           &trace_str, " (0x",
           absl::Hex(inst_db->Get<uint32_t>(0), absl::PadSpec::kZeroPad8), ")");
       for (int i = 0; i < inst->DestinationsSize(); ++i) {
-        auto *dest = inst->Destination(i);
+        auto* dest = inst->Destination(i);
         if (dest == nullptr) continue;
         auto name = dest->AsString();
         if (name == "pc") continue;
@@ -167,7 +167,7 @@
         if (iter == register_map->end()) {
           continue;
         } else {
-          auto *db = iter->second->data_buffer();
+          auto* db = iter->second->data_buffer();
           auto size = db->size<uint8_t>();
           if (size != sizeof(uint64_t)) {
             continue;
@@ -177,10 +177,10 @@
               absl::Hex(db->Get<uint64_t>(0), absl::PadSpec::kZeroPad16));
         }
       }
-      auto *child = inst->child();
+      auto* child = inst->child();
       while (child != nullptr) {
         for (int i = 0; i < child->DestinationsSize(); ++i) {
-          auto *dest = child->Destination(i);
+          auto* dest = child->Destination(i);
           if (dest == nullptr) continue;
           auto name = dest->AsString();
           if (name == "pc") continue;
@@ -189,7 +189,7 @@
           if (iter == register_map->end()) {
             continue;
           } else {
-            auto *db = iter->second->data_buffer();
+            auto* db = iter->second->data_buffer();
             auto size = db->size<uint8_t>();
             if (size != sizeof(uint64_t)) {
               absl::StrAppend(&trace_str, " size issue:  ", name);
@@ -249,7 +249,7 @@
       uint64_t begin_sig = begin_res.value().first;
       uint64_t end_sig = end_res.value().first;
       uint64_t length = end_sig - begin_sig;
-      uint8_t *buffer = new uint8_t[length];
+      uint8_t* buffer = new uint8_t[length];
       auto status = riscv_top.ReadMemory(begin_sig, buffer, length);
       sig_file << std::setfill('0') << std::hex;
       for (int i = 0; i < length; i += 16) {
diff --git a/riscv/rv64gv_sim.cc b/riscv/rv64gv_sim.cc
index 4029017..5a2cc15 100644
--- a/riscv/rv64gv_sim.cc
+++ b/riscv/rv64gv_sim.cc
@@ -155,7 +155,7 @@
 constexpr char kStackSizeSymbolName[] = "__stack_size";
 
 // Static pointer to the top instance. Used by the control-C handler.
-static mpact::sim::riscv::RiscVTop *top = nullptr;
+static mpact::sim::riscv::RiscVTop* top = nullptr;
 
 // Control-c handler to interrupt any running simulation.
 static void sim_sigint_handler(int arg) {
@@ -173,8 +173,8 @@
 // debug command shell.
 static bool PrintRegisters(
     absl::string_view input,
-    const mpact::sim::riscv::DebugCommandShell::CoreAccess &core_access,
-    std::string &output) {
+    const mpact::sim::riscv::DebugCommandShell::CoreAccess& core_access,
+    std::string& output) {
   static const LazyRE2 reg_info_re{R"(\s*reg\s+info\s*)"};
   if (!RE2::FullMatch(input, *reg_info_re)) {
     return false;
@@ -195,7 +195,7 @@
   return true;
 }
 
-int main(int argc, char **argv) {
+int main(int argc, char** argv) {
   int return_code = 0;
   auto arg_vec = absl::ParseCommandLine(argc, argv);
 
@@ -216,9 +216,9 @@
       full_file_name.substr(full_file_name.find_last_of('/') + 1);
   std::string file_basename = file_name.substr(0, file_name.find_first_of('.'));
 
-  auto *memory = new mpact::sim::util::FlatDemandMemory();
-  mpact::sim::util::MemoryWatcher *memory_watcher = nullptr;
-  mpact::sim::util::AtomicMemory *atomic_memory = nullptr;
+  auto* memory = new mpact::sim::util::FlatDemandMemory();
+  mpact::sim::util::MemoryWatcher* memory_watcher = nullptr;
+  mpact::sim::util::AtomicMemory* atomic_memory = nullptr;
   if (absl::GetFlag(FLAGS_exit_on_tohost)) {
     memory_watcher = new mpact::sim::util::MemoryWatcher(memory);
     atomic_memory = new mpact::sim::util::AtomicMemory(memory_watcher);
@@ -235,7 +235,7 @@
     return -1;
   }
 
-  mpact::sim::util::MemoryInterface *memory_interface = memory;
+  mpact::sim::util::MemoryInterface* memory_interface = memory;
   if (memory_watcher != nullptr) {
     memory_interface = memory_watcher;
   }
@@ -249,7 +249,7 @@
   RiscVVectorState rv_vector_state(&rv_state, 64);
   rv_state.set_rv_vector(&rv_vector_state);
   // Create the instruction decoder.
-  mpact::sim::generic::DecoderInterface *rv_decoder = nullptr;
+  mpact::sim::generic::DecoderInterface* rv_decoder = nullptr;
   if (absl::GetFlag(FLAGS_bitmanip)) {
     rv_decoder = new RiscV64GZBVecDecoder(&rv_state, memory);
   } else {
@@ -274,7 +274,7 @@
   RiscVTop riscv_top("RiscV32Sim", &rv_state, rv_decoder);
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
-    rv_state.set_on_ecall([&riscv_top](const Instruction *inst) -> bool {
+    rv_state.set_on_ecall([&riscv_top](const Instruction* inst) -> bool {
       riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, inst);
       return true;
     });
@@ -289,7 +289,7 @@
           [&riscv_top, tohost_addr, memory, &rv_state, &return_code, quiet](
               uint64_t, int) -> void {
             riscv_top.RequestHalt(RiscVTop::HaltReason::kProgramDone, nullptr);
-            auto *db = rv_state.db_factory()->Allocate<uint32_t>(1);
+            auto* db = rv_state.db_factory()->Allocate<uint32_t>(1);
             memory->Load(tohost_addr, db, nullptr, nullptr);
             auto word = db->Get<uint32_t>(0);
             db->DecRef();
@@ -370,14 +370,14 @@
   }
 
   // Set up arm semihosting if specified. Htif not supported for RiscV64.
-  RiscVArmSemihost *arm_semihost = nullptr;
+  RiscVArmSemihost* arm_semihost = nullptr;
   if (absl::GetFlag(FLAGS_semihost_arm)) {
     // Add ARM semihosting.
     arm_semihost = new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord64,
                                         memory, memory);
     arm_semihost->SetCmdLine(arg_vec);
     riscv_top.state()->AddEbreakHandler(
-        [arm_semihost](const Instruction *inst) {
+        [arm_semihost](const Instruction* inst) {
           if (arm_semihost->IsSemihostingCall(inst)) {
             arm_semihost->OnEBreak(inst);
             return true;
diff --git a/riscv/stoull_wrapper.cc b/riscv/stoull_wrapper.cc
index 2d3dfb6..adfba21 100644
--- a/riscv/stoull_wrapper.cc
+++ b/riscv/stoull_wrapper.cc
@@ -14,9 +14,14 @@
 
 #include "riscv/stoull_wrapper.h"
 
+#include <cstddef>
+#include <cstdint>
 #include <stdexcept>
 #include <string>
 
+#include "absl/status/status.h"
+#include "absl/status/statusor.h"
+
 // Google3 does not allow for exceptions, however, std:stoull can throw
 // exceptions when no number can be parsed. This wraps these exceptions,
 // translating them to absl::StatusOr<> and prevents exceptions from bleeding
@@ -27,13 +32,14 @@
 namespace riscv {
 namespace internal {
 
-absl::StatusOr<uint64_t> stoull(const std::string str, size_t *indx, int base) {
+absl::StatusOr<uint64_t> stoull(const std::string& str, size_t* indx,
+                                int base) {
   uint64_t value;
   try {
     value = std::stoull(str, indx, base);
-  } catch (const std::invalid_argument &e) {
+  } catch (const std::invalid_argument& e) {
     return absl::InvalidArgumentError("Conversion failed");
-  } catch (const std::out_of_range &e) {
+  } catch (const std::out_of_range& e) {
     return absl::OutOfRangeError("Conversion failed");
   } catch (...) {
     return absl::InternalError("Oops");
diff --git a/riscv/stoull_wrapper.h b/riscv/stoull_wrapper.h
index 1932c24..dd3cbf2 100644
--- a/riscv/stoull_wrapper.h
+++ b/riscv/stoull_wrapper.h
@@ -15,6 +15,8 @@
 #ifndef MPACT_RISCV_RISCV_STOULL_WRAPPER_H_
 #define MPACT_RISCV_RISCV_STOULL_WRAPPER_H_
 
+#include <cstddef>
+#include <cstdint>
 #include <string>
 
 #include "absl/status/statusor.h"
@@ -27,7 +29,7 @@
 namespace riscv {
 namespace internal {
 
-absl::StatusOr<uint64_t> stoull(const std::string str, size_t *indx = nullptr,
+absl::StatusOr<uint64_t> stoull(const std::string& str, size_t* indx = nullptr,
                                 int base = 10);
 
 }  // namespace internal
diff --git a/riscv/test/BUILD b/riscv/test/BUILD
index 1ffbd97..a41ea0c 100644
--- a/riscv/test/BUILD
+++ b/riscv/test/BUILD
@@ -157,6 +157,7 @@
         "//riscv:riscv_g",
         "//riscv:riscv_state",
         "@com_google_absl//absl/log:check",
+        "@com_google_absl//absl/strings",
         "@com_google_googletest//:gtest_main",
         "@com_google_mpact-sim//mpact/sim/generic:core",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
@@ -438,6 +439,7 @@
         "//riscv:riscv_arm_semihost",
         "//riscv:riscv_state",
         "@com_google_absl//absl/log:check",
+        "@com_google_absl//absl/strings",
         "@com_google_googletest//:gtest_main",
         "@com_google_mpact-sim//mpact/sim/generic:core",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
@@ -591,6 +593,7 @@
         "//riscv:riscv_v",
         "@com_google_absl//absl/random",
         "@com_google_absl//absl/strings",
+        "@com_google_absl//absl/types:span",
         "@com_google_googletest//:gtest_main",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
         "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
diff --git a/riscv/test/librenode_mpact_riscv32_so_test.cc b/riscv/test/librenode_mpact_riscv32_so_test.cc
index 38694c4..b46a452 100644
--- a/riscv/test/librenode_mpact_riscv32_so_test.cc
+++ b/riscv/test/librenode_mpact_riscv32_so_test.cc
@@ -29,7 +29,7 @@
 
   ~LibRenodeMpactRiscV32SoTest() { dlclose(lib_); }
 
-  void *lib_ = nullptr;
+  void* lib_ = nullptr;
 };
 
 TEST_F(LibRenodeMpactRiscV32SoTest, Construct) {
@@ -96,13 +96,13 @@
   EXPECT_NE(dlsym(lib_, "set_irq_value"), nullptr);
 }
 
-using ConstructType = int32_t (*)(char *, int32_t);
-using StepType = uint64_t (*)(int32_t, uint64_t, int32_t *);
-using SetConfigType = int32_t (*)(int32_t, const char *[], const char *[],
+using ConstructType = int32_t (*)(char*, int32_t);
+using StepType = uint64_t (*)(int32_t, uint64_t, int32_t*);
+using SetConfigType = int32_t (*)(int32_t, const char*[], const char*[],
                                   int32_t);
-using LoadElfType = uint64_t (*)(int32_t, const char *, bool, int32_t *);
+using LoadElfType = uint64_t (*)(int32_t, const char*, bool, int32_t*);
 using GetRegInfoSize = int32_t (*)(int32_t);
-using GetRegInfo = int32_t (*)(int32_t, int32_t, char *name, void *info);
+using GetRegInfo = int32_t (*)(int32_t, int32_t, char* name, void* info);
 using WriteRegisterType = void (*)(int32_t, int32_t, uint64_t);
 using DestructType = void (*)(int32_t);
 
@@ -144,15 +144,15 @@
   int num_regs = get_reg_info_size(id);
   CHECK_GT(num_regs, 0);
   // Set configuration items.
-  const char *kInstProfile = "instProfile";
-  const char *kMemProfile = "memProfile";
-  const char *kStackEnd = "stackEnd";
-  const char *kMemoryBase = "memoryBase";
-  const char *kMemorySize = "memorySize";
+  const char* kInstProfile = "instProfile";
+  const char* kMemProfile = "memProfile";
+  const char* kStackEnd = "stackEnd";
+  const char* kMemoryBase = "memoryBase";
+  const char* kMemorySize = "memorySize";
 
-  const char *kConfigItems[] = {kInstProfile, kMemProfile, kStackEnd,
+  const char* kConfigItems[] = {kInstProfile, kMemProfile, kStackEnd,
                                 kMemoryBase, kMemorySize};
-  const char *kConfigValues[] = {"1", "1", "0x00030000", "0x00000000",
+  const char* kConfigValues[] = {"1", "1", "0x00030000", "0x00000000",
                                  "0x10000000"};
   status = set_config(id, kConfigItems, kConfigValues, 5);
   CHECK_EQ(status, 0);
diff --git a/riscv/test/librenode_mpact_riscv64_so_test.cc b/riscv/test/librenode_mpact_riscv64_so_test.cc
index 9055f70..3fd2355 100644
--- a/riscv/test/librenode_mpact_riscv64_so_test.cc
+++ b/riscv/test/librenode_mpact_riscv64_so_test.cc
@@ -29,7 +29,7 @@
 
   ~LibRenodeMpactRiscV64SoTest() { dlclose(lib_); }
 
-  void *lib_ = nullptr;
+  void* lib_ = nullptr;
 };
 
 TEST_F(LibRenodeMpactRiscV64SoTest, Construct) {
@@ -96,14 +96,14 @@
   EXPECT_NE(dlsym(lib_, "set_irq_value"), nullptr);
 }
 
-using ConstructType = int32_t (*)(char *, int32_t);
+using ConstructType = int32_t (*)(char*, int32_t);
 using DestructType = void (*)(int32_t);
-using StepType = uint64_t (*)(int32_t, uint64_t, int32_t *);
-using SetConfigType = int32_t (*)(int32_t, const char *[], const char *[],
+using StepType = uint64_t (*)(int32_t, uint64_t, int32_t*);
+using SetConfigType = int32_t (*)(int32_t, const char*[], const char*[],
                                   int32_t);
-using LoadElfType = uint64_t (*)(int32_t, const char *, bool, int32_t *);
+using LoadElfType = uint64_t (*)(int32_t, const char*, bool, int32_t*);
 using GetRegInfoSize = int32_t (*)(int32_t);
-using GetRegInfo = int32_t (*)(int32_t, int32_t, char *name, void *info);
+using GetRegInfo = int32_t (*)(int32_t, int32_t, char* name, void* info);
 using WriteRegisterType = void (*)(int32_t, int32_t, uint64_t);
 
 TEST_F(LibRenodeMpactRiscV64SoTest, RunProgram) {
@@ -144,15 +144,15 @@
   int num_regs = get_reg_info_size(id);
   CHECK_GT(num_regs, 0);
   // Set configuration items.
-  const char *kInstProfile = "instProfile";
-  const char *kMemProfile = "memProfile";
-  const char *kStackEnd = "stackEnd";
-  const char *kMemoryBase = "memoryBase";
-  const char *kMemorySize = "memorySize";
+  const char* kInstProfile = "instProfile";
+  const char* kMemProfile = "memProfile";
+  const char* kStackEnd = "stackEnd";
+  const char* kMemoryBase = "memoryBase";
+  const char* kMemorySize = "memorySize";
 
-  const char *kConfigItems[] = {kInstProfile, kMemProfile, kStackEnd,
+  const char* kConfigItems[] = {kInstProfile, kMemProfile, kStackEnd,
                                 kMemoryBase, kMemorySize};
-  const char *kConfigValues[] = {"1", "1", "0x00030000", "0x00000000",
+  const char* kConfigValues[] = {"1", "1", "0x00030000", "0x00000000",
                                  "0x10000000"};
   status = set_config(id, kConfigItems, kConfigValues, 5);
   CHECK_EQ(status, 0);
diff --git a/riscv/test/riscv32_bitmanip_instructions_test.cc b/riscv/test/riscv32_bitmanip_instructions_test.cc
index 25ccf14..998094e 100644
--- a/riscv/test/riscv32_bitmanip_instructions_test.cc
+++ b/riscv/test/riscv32_bitmanip_instructions_test.cc
@@ -93,29 +93,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -124,9 +124,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -141,12 +141,12 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
-  RiscVState *state_;
-  Instruction *instruction_;
+  RiscVState* state_;
+  Instruction* instruction_;
   absl::BitGen bitgen_;
 };
 
diff --git a/riscv/test/riscv32_decoder_test.cc b/riscv/test/riscv32_decoder_test.cc
index 5a87736..a0d2d91 100644
--- a/riscv/test/riscv32_decoder_test.cc
+++ b/riscv/test/riscv32_decoder_test.cc
@@ -52,7 +52,7 @@
     auto result = loader_.LoadProgram(input_file);
     CHECK_OK(result.status());
     elf_reader_.load(input_file);
-    auto *symtab = elf_reader_.sections[".symtab"];
+    auto* symtab = elf_reader_.sections[".symtab"];
     CHECK_NE(symtab, nullptr);
     symbol_accessor_ = new SymbolAccessor(elf_reader_, symtab);
   }
@@ -64,7 +64,7 @@
   mpact::sim::riscv::RiscVState state_;
   mpact::sim::util::ElfProgramLoader loader_;
   mpact::sim::riscv::RiscV32Decoder decoder_;
-  SymbolAccessor *symbol_accessor_;
+  SymbolAccessor* symbol_accessor_;
 };
 
 // This test is really pretty simple. It decodes the instructions in "main".
@@ -84,15 +84,15 @@
   uint64_t address = value;
   while (address < value + size) {
     EXPECT_FALSE(state_.program_error_controller()->HasError());
-    auto *inst = decoder_.DecodeInstruction(address);
+    auto* inst = decoder_.DecodeInstruction(address);
     ASSERT_NE(inst, nullptr);
     inst->Execute(nullptr);
     if (state_.program_error_controller()->HasError()) {
       auto errvec = state_.program_error_controller()->GetUnmaskedErrorNames();
-      for (auto &err : errvec) {
+      for (auto& err : errvec) {
         LOG(INFO) << "Error: " << err;
         auto msgvec = state_.program_error_controller()->GetErrorMessages(err);
-        for (auto &msg : msgvec) {
+        for (auto& msg : msgvec) {
           LOG(INFO) << "    " << msg;
         }
       }
@@ -107,7 +107,7 @@
 
 // Even with a bad address, a valid instruction object should be returned.
 TEST_F(RiscV32DecoderTest, BadAddress) {
-  auto *inst = decoder_.DecodeInstruction(0x4321);
+  auto* inst = decoder_.DecodeInstruction(0x4321);
   ASSERT_NE(inst, nullptr);
   inst->Execute(nullptr);
   inst->DecRef();
diff --git a/riscv/test/riscv32_htif_semihost_test.cc b/riscv/test/riscv32_htif_semihost_test.cc
index 0cdd474..6d98dda 100644
--- a/riscv/test/riscv32_htif_semihost_test.cc
+++ b/riscv/test/riscv32_htif_semihost_test.cc
@@ -44,8 +44,8 @@
   }
 
   DataBufferFactory db_factory_;
-  mpact::sim::util::MemoryWatcher *watcher_;
-  mpact::sim::util::FlatDemandMemory *memory_;
+  mpact::sim::util::MemoryWatcher* watcher_;
+  mpact::sim::util::FlatDemandMemory* memory_;
   SemiHostAddresses semi_host_addresses_ = {0x1000, 0x1008, 0x2000, 0x2008};
 };
 
@@ -53,10 +53,10 @@
 TEST_F(RiscV32HtifSemiHostTest, Constructors) {
   bool halted = false;
   std::string error;
-  auto *one = new RiscV32HtifSemiHost(watcher_, memory_, semi_host_addresses_);
+  auto* one = new RiscV32HtifSemiHost(watcher_, memory_, semi_host_addresses_);
   one->SetHaltCallback([&halted]() { halted = true; });
   one->SetErrorCallback([&error](std::string err) { error = err; });
-  auto *two = new RiscV32HtifSemiHost(
+  auto* two = new RiscV32HtifSemiHost(
       watcher_, memory_, semi_host_addresses_, [&halted]() { halted = true; },
       [&error](std::string err) { error = err; });
   delete one;
@@ -68,15 +68,15 @@
   bool halted = false;
   bool error_call = false;
   std::string error;
-  auto *semi_host =
+  auto* semi_host =
       new RiscV32HtifSemiHost(watcher_, memory_, semi_host_addresses_);
   semi_host->SetHaltCallback([&halted]() { halted = true; });
   semi_host->SetErrorCallback([&error, &error_call](std::string msg) {
     error_call = true;
     error = msg;
   });
-  auto *db1 = db_factory_.Allocate<uint8_t>(1);
-  auto *db8 = db_factory_.Allocate<uint64_t>(1);
+  auto* db1 = db_factory_.Allocate<uint8_t>(1);
+  auto* db8 = db_factory_.Allocate<uint64_t>(1);
   db1->Set<uint8_t>(0, 1);
   db8->Set<uint64_t>(0, 1);
   watcher_->Store(semi_host_addresses_.tohost, db8);
@@ -96,20 +96,20 @@
   bool halted = false;
   bool error_call = false;
   std::string error;
-  auto *semi_host =
+  auto* semi_host =
       new RiscV32HtifSemiHost(watcher_, memory_, semi_host_addresses_);
   semi_host->SetHaltCallback([&halted]() { halted = true; });
   semi_host->SetErrorCallback([&error, &error_call](std::string msg) {
     error_call = true;
     error = msg;
   });
-  auto *db1 = db_factory_.Allocate<uint8_t>(1);
-  auto *db8 = db_factory_.Allocate<uint64_t>(1);
-  auto *db64 = db_factory_.Allocate<uint64_t>(8);
+  auto* db1 = db_factory_.Allocate<uint8_t>(1);
+  auto* db8 = db_factory_.Allocate<uint64_t>(1);
+  auto* db64 = db_factory_.Allocate<uint64_t>(8);
 
   db1->Set<uint8_t>(0, 1);
   db8->Set<uint64_t>(0, 0x4000);
-  for (auto &el : db64->Get<uint64_t>()) el = 0;
+  for (auto& el : db64->Get<uint64_t>()) el = 0;
   db64->Set<uint64_t>(0, 123);
   watcher_->Store(0x4000, db64);
   watcher_->Store(semi_host_addresses_.tohost, db8);
@@ -132,22 +132,22 @@
   bool halted = false;
   bool error_call = false;
   std::string error;
-  auto *semi_host =
+  auto* semi_host =
       new RiscV32HtifSemiHost(watcher_, memory_, semi_host_addresses_);
   semi_host->SetHaltCallback([&halted]() { halted = true; });
   semi_host->SetErrorCallback([&error, &error_call](std::string msg) {
     error_call = true;
     error = msg;
   });
-  auto *db1 = db_factory_.Allocate<uint8_t>(1);
-  auto *db8 = db_factory_.Allocate<uint64_t>(1);
-  auto *db16 = db_factory_.Allocate<uint8_t>(16);
-  auto *db64 = db_factory_.Allocate<uint64_t>(8);
+  auto* db1 = db_factory_.Allocate<uint8_t>(1);
+  auto* db8 = db_factory_.Allocate<uint64_t>(1);
+  auto* db16 = db_factory_.Allocate<uint8_t>(16);
+  auto* db64 = db_factory_.Allocate<uint64_t>(8);
 
   db1->Set<uint8_t>(0, 1);
   db8->Set<uint64_t>(0, 0x4000);
   std::memcpy(db16->raw_ptr(), kHelloWorld, strlen(kHelloWorld));
-  for (auto &el : db64->Get<uint64_t>()) el = 0;
+  for (auto& el : db64->Get<uint64_t>()) el = 0;
   db64->Set<uint64_t>(0, 64);
   db64->Set<uint64_t>(1, 2);
   db64->Set<uint64_t>(2, 0x4100);
diff --git a/riscv/test/riscv32g_encoding_test.cc b/riscv/test/riscv32g_encoding_test.cc
index e77f4be..bb680d4 100644
--- a/riscv/test/riscv32g_encoding_test.cc
+++ b/riscv/test/riscv32g_encoding_test.cc
@@ -225,8 +225,8 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV32GEncoding *enc_;
+  RiscVState* state_;
+  RiscV32GEncoding* enc_;
 };
 
 constexpr int kRdValue = 1;
@@ -258,7 +258,7 @@
 }
 
 TEST_F(RiscV32GEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -266,7 +266,7 @@
 }
 
 TEST_F(RiscV32GEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -274,7 +274,7 @@
 }
 
 TEST_F(RiscV32GEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -283,7 +283,7 @@
 }
 
 TEST_F(RiscV32GEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv32g_vec_encoding_test.cc b/riscv/test/riscv32g_vec_encoding_test.cc
index f3af998..753678a 100644
--- a/riscv/test/riscv32g_vec_encoding_test.cc
+++ b/riscv/test/riscv32g_vec_encoding_test.cc
@@ -54,12 +54,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV32GVecEncoding *enc_;
+  RiscVState* state_;
+  RiscV32GVecEncoding* enc_;
 };
 
 TEST_F(RiscV32GVecEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -67,7 +67,7 @@
 }
 
 TEST_F(RiscV32GVecEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -75,7 +75,7 @@
 }
 
 TEST_F(RiscV32GVecEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -84,7 +84,7 @@
 }
 
 TEST_F(RiscV32GVecEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv32gzb_encoding_test.cc b/riscv/test/riscv32gzb_encoding_test.cc
index 8131160..d0e4b79 100644
--- a/riscv/test/riscv32gzb_encoding_test.cc
+++ b/riscv/test/riscv32gzb_encoding_test.cc
@@ -98,12 +98,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV32GZBEncoding *enc_;
+  RiscVState* state_;
+  RiscV32GZBEncoding* enc_;
 };
 
 TEST_F(RiscV32GZBEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -111,7 +111,7 @@
 }
 
 TEST_F(RiscV32GZBEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -119,7 +119,7 @@
 }
 
 TEST_F(RiscV32GZBEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -128,7 +128,7 @@
 }
 
 TEST_F(RiscV32GZBEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv32gzb_vec_encoding_test.cc b/riscv/test/riscv32gzb_vec_encoding_test.cc
index f14f8df..f34a2c8 100644
--- a/riscv/test/riscv32gzb_vec_encoding_test.cc
+++ b/riscv/test/riscv32gzb_vec_encoding_test.cc
@@ -54,12 +54,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV32GZBVecEncoding *enc_;
+  RiscVState* state_;
+  RiscV32GZBVecEncoding* enc_;
 };
 
 TEST_F(RiscV32GZBVecEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -67,7 +67,7 @@
 }
 
 TEST_F(RiscV32GZBVecEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -75,7 +75,7 @@
 }
 
 TEST_F(RiscV32GZBVecEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -84,7 +84,7 @@
 }
 
 TEST_F(RiscV32GZBVecEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv64_bitmanip_instructions_test.cc b/riscv/test/riscv64_bitmanip_instructions_test.cc
index ecb82e9..661bc83 100644
--- a/riscv/test/riscv64_bitmanip_instructions_test.cc
+++ b/riscv/test/riscv64_bitmanip_instructions_test.cc
@@ -92,29 +92,29 @@
   // Appends the source and destination operands for the register names
   // given in the two vectors.
   void AppendRegisterOperands(
-      Instruction *inst, const std::vector<std::string_view> &sources,
-      const std::vector<std::string_view> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+      Instruction* inst, const std::vector<std::string_view>& sources,
+      const std::vector<std::string_view>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   void AppendRegisterOperands(
-      const std::vector<std::string_view> &sources,
-      const std::vector<std::string_view> &destinations) {
+      const std::vector<std::string_view>& sources,
+      const std::vector<std::string_view>& destinations) {
     AppendRegisterOperands(instruction_.get(), sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -124,9 +124,9 @@
   template <typename T>
   void SetRegisterValues(
       const std::vector<std::tuple<std::string_view, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV64Register::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV64Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -141,7 +141,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -163,7 +163,7 @@
   EXPECT_EQ(GetRegisterValue<int64_t>(kX3), (kUVal1 & 0xffff'ffffLL) + kUVal2);
 }
 
-void VshNaddTestHelper(RV64BitmanipInstructionTest &test, int shift) {
+void VshNaddTestHelper(RV64BitmanipInstructionTest& test, int shift) {
   test.AppendRegisterOperands({kX1, kX2, kX4}, {kX3});
 
   test.SetRegisterValues<uint64_t>(
@@ -187,7 +187,7 @@
   VshNaddTestHelper(*this, 3);
 }
 
-void VshNadduwTestHelper(RV64BitmanipInstructionTest &test, int shift) {
+void VshNadduwTestHelper(RV64BitmanipInstructionTest& test, int shift) {
   test.AppendRegisterOperands({kX1, kX2, kX4}, {kX3});
 
   test.SetRegisterValues<uint64_t>(
diff --git a/riscv/test/riscv64_decoder_test.cc b/riscv/test/riscv64_decoder_test.cc
index 0354f11..e4461a5 100644
--- a/riscv/test/riscv64_decoder_test.cc
+++ b/riscv/test/riscv64_decoder_test.cc
@@ -57,7 +57,7 @@
     auto result = loader_.LoadProgram(input_file);
     CHECK_OK(result.status());
     elf_reader_.load(input_file);
-    auto *symtab = elf_reader_.sections[".symtab"];
+    auto* symtab = elf_reader_.sections[".symtab"];
     CHECK_NE(symtab, nullptr);
     symbol_accessor_ = new SymbolAccessor(elf_reader_, symtab);
   }
@@ -69,11 +69,11 @@
   mpact::sim::util::FlatDemandMemory memory_;
   mpact::sim::util::ElfProgramLoader loader_;
   RiscV64Decoder decoder_;
-  SymbolAccessor *symbol_accessor_;
+  SymbolAccessor* symbol_accessor_;
 };
 
 TEST_F(RiscV64DecoderTest, Getters) {
-  RiscV64Decoder *decoder = nullptr;
+  RiscV64Decoder* decoder = nullptr;
   LogSink log_sink;
   absl::AddLogSink(&log_sink);
   decoder = new RiscV64Decoder(&state_, &memory_);
@@ -99,15 +99,15 @@
   uint64_t address = value;
   while (address < value + size) {
     EXPECT_FALSE(state_.program_error_controller()->HasError());
-    auto *inst = decoder_.DecodeInstruction(address);
+    auto* inst = decoder_.DecodeInstruction(address);
     ASSERT_NE(inst, nullptr);
     inst->Execute(nullptr);
     if (state_.program_error_controller()->HasError()) {
       auto errvec = state_.program_error_controller()->GetUnmaskedErrorNames();
-      for (auto &err : errvec) {
+      for (auto& err : errvec) {
         LOG(INFO) << "Error: " << err;
         auto msgvec = state_.program_error_controller()->GetErrorMessages(err);
-        for (auto &msg : msgvec) {
+        for (auto& msg : msgvec) {
           LOG(INFO) << "    " << msg;
         }
       }
@@ -122,7 +122,7 @@
 
 // Even with a bad address, a valid instruction object should be returned.
 TEST_F(RiscV64DecoderTest, BadAddress) {
-  auto *inst = decoder_.DecodeInstruction(0x4321);
+  auto* inst = decoder_.DecodeInstruction(0x4321);
   ASSERT_NE(inst, nullptr);
   inst->Execute(nullptr);
   inst->DecRef();
diff --git a/riscv/test/riscv64g_encoding_test.cc b/riscv/test/riscv64g_encoding_test.cc
index 5380649..c277327 100644
--- a/riscv/test/riscv64g_encoding_test.cc
+++ b/riscv/test/riscv64g_encoding_test.cc
@@ -239,8 +239,8 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV64GEncoding *enc_;
+  RiscVState* state_;
+  RiscV64GEncoding* enc_;
 };
 
 constexpr int kRdValue = 1;
@@ -272,7 +272,7 @@
 }
 
 TEST_F(RiscV64GEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -280,7 +280,7 @@
 }
 
 TEST_F(RiscV64GEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -288,7 +288,7 @@
 }
 
 TEST_F(RiscV64GEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -297,7 +297,7 @@
 }
 
 TEST_F(RiscV64GEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv64g_vec_encoding_test.cc b/riscv/test/riscv64g_vec_encoding_test.cc
index 1af43a0..273f139 100644
--- a/riscv/test/riscv64g_vec_encoding_test.cc
+++ b/riscv/test/riscv64g_vec_encoding_test.cc
@@ -54,12 +54,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV64GVecEncoding *enc_;
+  RiscVState* state_;
+  RiscV64GVecEncoding* enc_;
 };
 
 TEST_F(RiscV64GVecEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -67,7 +67,7 @@
 }
 
 TEST_F(RiscV64GVecEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -75,7 +75,7 @@
 }
 
 TEST_F(RiscV64GVecEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -84,7 +84,7 @@
 }
 
 TEST_F(RiscV64GVecEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv64gzb_encoding_test.cc b/riscv/test/riscv64gzb_encoding_test.cc
index fd29d6e..a1474ce 100644
--- a/riscv/test/riscv64gzb_encoding_test.cc
+++ b/riscv/test/riscv64gzb_encoding_test.cc
@@ -54,12 +54,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV64GZBEncoding *enc_;
+  RiscVState* state_;
+  RiscV64GZBEncoding* enc_;
 };
 
 TEST_F(RiscV64GZBEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -67,7 +67,7 @@
 }
 
 TEST_F(RiscV64GZBEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -75,7 +75,7 @@
 }
 
 TEST_F(RiscV64GZBEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -84,7 +84,7 @@
 }
 
 TEST_F(RiscV64GZBEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv64gzb_vec_encoding_test.cc b/riscv/test/riscv64gzb_vec_encoding_test.cc
index fa801c1..6d0e00d 100644
--- a/riscv/test/riscv64gzb_vec_encoding_test.cc
+++ b/riscv/test/riscv64gzb_vec_encoding_test.cc
@@ -54,12 +54,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscV64GZBVecEncoding *enc_;
+  RiscVState* state_;
+  RiscV64GZBVecEncoding* enc_;
 };
 
 TEST_F(RiscV64GZBVecEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -67,7 +67,7 @@
 }
 
 TEST_F(RiscV64GZBVecEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -75,7 +75,7 @@
 }
 
 TEST_F(RiscV64GZBVecEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -84,7 +84,7 @@
 }
 
 TEST_F(RiscV64GZBVecEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/test/riscv_a_instructions_test.cc b/riscv/test/riscv_a_instructions_test.cc
index 99cae8e..b7397f6 100644
--- a/riscv/test/riscv_a_instructions_test.cc
+++ b/riscv/test/riscv_a_instructions_test.cc
@@ -14,12 +14,16 @@
 
 #include "riscv/riscv_a_instructions.h"
 
+#include <algorithm>
 #include <cstdint>
 #include <ios>
 #include <string>
+#include <tuple>
+#include <type_traits>
 #include <vector>
 
 #include "absl/log/check.h"
+#include "absl/strings/string_view.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/instruction.h"
@@ -120,21 +124,21 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
@@ -142,9 +146,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV64Register::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV64Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -163,7 +167,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
     if (std::is_signed<T>::value) {
       return static_cast<T>(reg->data_buffer()->Get<int64_t>(0));
     } else {
@@ -171,13 +175,13 @@
     }
   }
 
-  DataBuffer *db_w_;
-  DataBuffer *db_d_;
-  FlatDemandMemory *memory_;
-  AtomicMemory *atomic_memory_;
-  RiscVState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
+  DataBuffer* db_w_;
+  DataBuffer* db_d_;
+  FlatDemandMemory* memory_;
+  AtomicMemory* atomic_memory_;
+  RiscVState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
 };
 
 TEST_F(RiscVAInstructionsTest, ALrw) {
diff --git a/riscv/test/riscv_arm_semihost_test.cc b/riscv/test/riscv_arm_semihost_test.cc
index 999c325..0c5352b 100644
--- a/riscv/test/riscv_arm_semihost_test.cc
+++ b/riscv/test/riscv_arm_semihost_test.cc
@@ -17,10 +17,14 @@
 #include <time.h>
 #include <unistd.h>
 
+#include <cstdint>
+#include <cstdio>
 #include <cstring>
 #include <string>
+#include <type_traits>
 
 #include "absl/log/check.h"
+#include "absl/strings/str_cat.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/instruction.h"
@@ -61,7 +65,7 @@
 
 constexpr int kBufferSize = 128;
 
-// Opcode sequence that idenfifies the semihosting call. This consists
+// Opcode sequence that identifies the semihosting call. This consists
 // of a shift immediate on the x0 (constant 0 register), followed by
 // an ebreak instruction, followed by a different shift immediate on x0.
 constexpr uint32_t kSemihostCallSequence[] = {0x01f01013, 0x00100073,
@@ -103,19 +107,19 @@
 // Test fixture for RiscV Arm Semihosting.
 class RiscVArmSemihostTest : public testing::Test {
  public:
-  void SetTrue(bool *value) { *value = true; }
-  RiscVArmSemihost *semi32() const { return semi32_; }
-  RiscVArmSemihost *semi64() const { return semi64_; }
-  RV32Register *a0_32() const { return a0_32_; }
-  RV32Register *a1_32() const { return a1_32_; }
-  RV64Register *a0_64() const { return a0_64_; }
-  RV64Register *a1_64() const { return a1_64_; }
-  Instruction *semihost_inst_32() const { return semihost_inst_32_; }
-  Instruction *semihost_inst_64() const { return semihost_inst_64_; }
-  Instruction *non_semihost_inst_32() const { return non_semihost_inst_32_; }
-  Instruction *non_semihost_inst_64() const { return non_semihost_inst_64_; }
-  DataBufferFactory *db_factory() { return &db_factory_; }
-  mpact::sim::util::MemoryInterface *memory() const { return memory_; }
+  void SetTrue(bool* value) { *value = true; }
+  RiscVArmSemihost* semi32() const { return semi32_; }
+  RiscVArmSemihost* semi64() const { return semi64_; }
+  RV32Register* a0_32() const { return a0_32_; }
+  RV32Register* a1_32() const { return a1_32_; }
+  RV64Register* a0_64() const { return a0_64_; }
+  RV64Register* a1_64() const { return a1_64_; }
+  Instruction* semihost_inst_32() const { return semihost_inst_32_; }
+  Instruction* semihost_inst_64() const { return semihost_inst_64_; }
+  Instruction* non_semihost_inst_32() const { return non_semihost_inst_32_; }
+  Instruction* non_semihost_inst_64() const { return non_semihost_inst_64_; }
+  DataBufferFactory* db_factory() { return &db_factory_; }
+  mpact::sim::util::MemoryInterface* memory() const { return memory_; }
 
  protected:
   RiscVArmSemihostTest() {
@@ -171,15 +175,15 @@
   }
 
   DataBufferFactory db_factory_;
-  mpact::sim::util::FlatDemandMemory *memory_;
-  RiscVState *state32_;
-  RiscVState *state64_;
-  Instruction *semihost_inst_32_;
-  Instruction *semihost_inst_64_;
-  Instruction *non_semihost_inst_32_;
-  Instruction *non_semihost_inst_64_;
-  RiscVArmSemihost *semi32_;
-  RiscVArmSemihost *semi64_;
+  mpact::sim::util::FlatDemandMemory* memory_;
+  RiscVState* state32_;
+  RiscVState* state64_;
+  Instruction* semihost_inst_32_;
+  Instruction* semihost_inst_64_;
+  Instruction* non_semihost_inst_32_;
+  Instruction* non_semihost_inst_64_;
+  RiscVArmSemihost* semi32_;
+  RiscVArmSemihost* semi64_;
   RV32Register *a0_32_, *a1_32_;
   RV64Register *a0_64_, *a1_64_;
 };
@@ -188,24 +192,24 @@
 
 // Semihosting instance.
 template <typename T>
-RiscVArmSemihost *SemiHost(RiscVArmSemihostTest *test) {}
+RiscVArmSemihost* SemiHost(RiscVArmSemihostTest* test) {}
 
 template <>
-RiscVArmSemihost *SemiHost<uint32_t>(RiscVArmSemihostTest *test) {
+RiscVArmSemihost* SemiHost<uint32_t>(RiscVArmSemihostTest* test) {
   return test->semi32();
 }
 
 template <>
-RiscVArmSemihost *SemiHost<uint64_t>(RiscVArmSemihostTest *test) {
+RiscVArmSemihost* SemiHost<uint64_t>(RiscVArmSemihostTest* test) {
   return test->semi64();
 }
 
 // Register.
 template <typename T>
-typename RegisterType<T>::type *AReg(RiscVArmSemihostTest *test, T num) {}
+typename RegisterType<T>::type* AReg(RiscVArmSemihostTest* test, T num) {}
 
 template <>
-typename RegisterType<uint32_t>::type *AReg(RiscVArmSemihostTest *test,
+typename RegisterType<uint32_t>::type* AReg(RiscVArmSemihostTest* test,
                                             uint32_t num) {
   if (num == 0) return test->a0_32();
   if (num == 1) return test->a1_32();
@@ -213,7 +217,7 @@
 }
 
 template <>
-typename RegisterType<uint64_t>::type *AReg(RiscVArmSemihostTest *test,
+typename RegisterType<uint64_t>::type* AReg(RiscVArmSemihostTest* test,
                                             uint64_t num) {
   if (num == 0) return test->a0_64();
   if (num == 1) return test->a1_64();
@@ -222,28 +226,28 @@
 
 // Semihosting instruction instance.
 template <typename T>
-Instruction *SemihostInst(RiscVArmSemihostTest *test, T num = 0) {}
+Instruction* SemihostInst(RiscVArmSemihostTest* test, T num = 0) {}
 
 template <>
-Instruction *SemihostInst<uint32_t>(RiscVArmSemihostTest *test, uint32_t) {
+Instruction* SemihostInst<uint32_t>(RiscVArmSemihostTest* test, uint32_t) {
   return test->semihost_inst_32();
 }
 
 template <>
-Instruction *SemihostInst<uint64_t>(RiscVArmSemihostTest *test, uint64_t) {
+Instruction* SemihostInst<uint64_t>(RiscVArmSemihostTest* test, uint64_t) {
   return test->semihost_inst_64();
 }
 
 // Non-semihosting instruction instance.
 template <typename T>
-Instruction *NonSemihostInst(RiscVArmSemihostTest *test, T num = 0) {}
+Instruction* NonSemihostInst(RiscVArmSemihostTest* test, T num = 0) {}
 
 template <>
-Instruction *NonSemihostInst<uint32_t>(RiscVArmSemihostTest *test, uint32_t) {
+Instruction* NonSemihostInst<uint32_t>(RiscVArmSemihostTest* test, uint32_t) {
   return test->non_semihost_inst_32();
 }
 template <>
-Instruction *NonSemihostInst<uint64_t>(RiscVArmSemihostTest *test, uint64_t) {
+Instruction* NonSemihostInst<uint64_t>(RiscVArmSemihostTest* test, uint64_t) {
   return test->non_semihost_inst_64();
 }
 
@@ -251,7 +255,7 @@
 // call.
 
 template <typename T>
-void CallRecognitionTest(RiscVArmSemihostTest *test) {
+void CallRecognitionTest(RiscVArmSemihostTest* test) {
   AReg<T>(test, 0)->data_buffer()->template Set<T>(0, kSysTime);
   AReg<T>(test, 1)->data_buffer()->template Set<T>(0, 0);
   SemiHost<T>(test)->OnEBreak(SemihostInst<T>(test));
@@ -271,7 +275,7 @@
 // Verify that a sequence that doesn't match doesn't trigger semihosting call.
 
 template <typename T>
-void CallNonRecognitionTest(RiscVArmSemihostTest *test) {
+void CallNonRecognitionTest(RiscVArmSemihostTest* test) {
   AReg<T>(test, 0)->data_buffer()->template Set<T>(0, kSysTime);
   AReg<T>(test, 1)->data_buffer()->template Set<T>(0, 0);
   SemiHost<T>(test)->OnEBreak(NonSemihostInst<T>(test));
@@ -313,7 +317,7 @@
       [&detected]() { detected = true; });
 
   // Write exception code to memory.
-  auto *db = db_factory()->Allocate<uint64_t>(1);
+  auto* db = db_factory()->Allocate<uint64_t>(1);
   db->template Set<uint64_t>(0, kAdpStoppedApplicationExit);
   memory_->Store(kParameterAddress, db);
   db->DecRef();
@@ -331,17 +335,17 @@
 
 // Test the Write system call (printf to stderr).
 template <typename T>
-void SysWriteTest(RiscVArmSemihostTest *test) {
+void SysWriteTest(RiscVArmSemihostTest* test) {
   testing::internal::CaptureStderr();
 
   // Write string to memory.
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(strlen(kHelloWorld));
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(strlen(kHelloWorld));
   std::memcpy(str_db->raw_ptr(), kHelloWorld, strlen(kHelloWorld));
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, 2);
   db->template Set<T>(1, kStringAddress);
   db->template Set<T>(2, strlen(kHelloWorld));
@@ -367,7 +371,7 @@
 // Systick should just return -1 for now.
 
 template <typename T>
-void SysTickTest(RiscVArmSemihostTest *test) {
+void SysTickTest(RiscVArmSemihostTest* test) {
   AReg<T>(test, 0)->data_buffer()->template Set<T>(0, kSysTickFreq);
   AReg<T>(test, 1)->data_buffer()->template Set<T>(0, 0);
   SemiHost<T>(test)->OnEBreak(SemihostInst<T>(test));
@@ -384,15 +388,15 @@
 // Test SysOpen
 
 template <typename T>
-void SysOpenTest(RiscVArmSemihostTest *test) {
+void SysOpenTest(RiscVArmSemihostTest* test) {
   std::string input_file = absl::StrCat(kDepotPath, "testfiles/", kFileName);
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
   std::memcpy(str_db->raw_ptr(), input_file.c_str(), input_file.length() + 1);
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kStringAddress);
   db->template Set<T>(1, 0);
   db->template Set<T>(2, input_file.length());
@@ -446,15 +450,15 @@
 
 // Test sys open and close.
 template <typename T>
-void SysOpenCloseTest(RiscVArmSemihostTest *test) {
+void SysOpenCloseTest(RiscVArmSemihostTest* test) {
   std::string input_file = absl::StrCat(kDepotPath, "testfiles/", kFileName);
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
   std::memcpy(str_db->raw_ptr(), input_file.c_str(), input_file.length() + 1);
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kStringAddress);
   db->template Set<T>(1, 0);
   db->template Set<T>(2, input_file.length());
@@ -512,16 +516,16 @@
 // Test open-read-close.
 
 template <typename T>
-void SysOpenReadClose(RiscVArmSemihostTest *test) {
+void SysOpenReadClose(RiscVArmSemihostTest* test) {
   // Open the file.
   std::string input_file = absl::StrCat(kDepotPath, "testfiles/", kFileName);
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
   std::memcpy(str_db->raw_ptr(), input_file.c_str(), input_file.length() + 1);
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kStringAddress);
   db->template Set<T>(1, 0);
   db->template Set<T>(2, input_file.length());
@@ -556,7 +560,7 @@
 
   db = test->db_factory()->Allocate<uint8_t>(6);
   test->memory()->Load(kBufferAddress, db, nullptr, nullptr);
-  std::string file_value(reinterpret_cast<char *>(db->raw_ptr()), 6);
+  std::string file_value(reinterpret_cast<char*>(db->raw_ptr()), 6);
   db->DecRef();
 
   // Verify the number of characters read and that the characters are correct.
@@ -590,15 +594,15 @@
 // Test flen (file length).
 
 template <typename T>
-void SysFlenTest(RiscVArmSemihostTest *test) {  // Open the file.
+void SysFlenTest(RiscVArmSemihostTest* test) {  // Open the file.
   std::string input_file = absl::StrCat(kDepotPath, "testfiles/", kFileName);
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
   std::memcpy(str_db->raw_ptr(), input_file.c_str(), input_file.length() + 1);
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kStringAddress);
   db->template Set<T>(1, 0);
   db->template Set<T>(2, input_file.length());
@@ -641,9 +645,9 @@
 // Test tmpnam call.
 
 template <typename T>
-void SysTmpnamTest(RiscVArmSemihostTest *test) {
+void SysTmpnamTest(RiscVArmSemihostTest* test) {
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kBufferAddress);
   db->template Set<T>(1, 1);
   db->template Set<T>(2, kTmpNamLength);
@@ -663,7 +667,7 @@
   auto tmpnam_db = test->db_factory()->Allocate<char>(kTmpNamLength);
   test->memory()->Load(kBufferAddress, tmpnam_db, nullptr, nullptr);
 
-  char *tmp_name = static_cast<char *>(tmpnam_db->raw_ptr());
+  char* tmp_name = static_cast<char*>(tmpnam_db->raw_ptr());
   auto length = strlen(tmp_name);
   EXPECT_LE(length, kTmpNamLength);
   EXPECT_GT(length, 0);
@@ -678,7 +682,7 @@
 // Test that HeapInfo returns a struct with all zeros.
 
 template <typename T>
-void SysHeapInfoTest(RiscVArmSemihostTest *test) {
+void SysHeapInfoTest(RiscVArmSemihostTest* test) {
   // Set up register values.
   AReg<T>(test, 0)->data_buffer()->template Set<T>(0, kSysHeapInfo);
   AReg<T>(test, 1)->data_buffer()->template Set<T>(0, kBufferAddress);
@@ -686,7 +690,7 @@
   SemiHost<T>(test)->OnEBreak(SemihostInst<T>(test));
 
   // Fetch the returned values.
-  auto *db = test->db_factory()->Allocate<T>(4);
+  auto* db = test->db_factory()->Allocate<T>(4);
   test->memory()->Load(kBufferAddress, db, nullptr, nullptr);
   EXPECT_EQ(db->template Get<T>(0), 0);
   EXPECT_EQ(db->template Get<T>(1), 0);
@@ -702,15 +706,15 @@
 // Test that seek works by opening a file, seeking, then reading from the file.
 
 template <typename T>
-void SysSeekTest(RiscVArmSemihostTest *test) {
+void SysSeekTest(RiscVArmSemihostTest* test) {
   std::string input_file = absl::StrCat(kDepotPath, "testfiles/", kFileName);
-  auto *str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
+  auto* str_db = test->db_factory()->Allocate<uint8_t>(input_file.length() + 1);
   std::memcpy(str_db->raw_ptr(), input_file.c_str(), input_file.length() + 1);
   test->memory()->Store(kStringAddress, str_db);
   str_db->DecRef();
 
   // Set up parameter block.
-  auto *db = test->db_factory()->Allocate<T>(3);
+  auto* db = test->db_factory()->Allocate<T>(3);
   db->template Set<T>(0, kStringAddress);
   db->template Set<T>(1, 0);
   db->template Set<T>(2, input_file.length());
@@ -771,7 +775,7 @@
 
   db = test->db_factory()->Allocate<uint8_t>(6);
   test->memory()->Load(kBufferAddress, db, nullptr, nullptr);
-  std::string file_value(reinterpret_cast<char *>(db->raw_ptr()), 4);
+  std::string file_value(reinterpret_cast<char*>(db->raw_ptr()), 4);
   db->DecRef();
 
   // Verify the number of characters read and that the characters are correct.
diff --git a/riscv/test/riscv_breakpoint_test.cc b/riscv/test/riscv_breakpoint_test.cc
index 944693a..f27f0b1 100644
--- a/riscv/test/riscv_breakpoint_test.cc
+++ b/riscv/test/riscv_breakpoint_test.cc
@@ -79,13 +79,13 @@
 
   uint64_t latch_address_ = 0;
   int latch_size_ = -1;
-  RiscVActionPointMemoryInterface *rv_ap_memory_interface_;
-  ActionPointManagerBase *ap_manager_;
-  BreakpointManager *bp_manager_;
+  RiscVActionPointMemoryInterface* rv_ap_memory_interface_;
+  ActionPointManagerBase* ap_manager_;
+  BreakpointManager* bp_manager_;
   DataBufferFactory db_factory_;
-  FlatDemandMemory *memory_;
-  DataBuffer *db2_;
-  DataBuffer *db4_;
+  FlatDemandMemory* memory_;
+  DataBuffer* db2_;
+  DataBuffer* db4_;
 };
 
 TEST_F(RiscVBreakpointTest, Breakpoint16) {
diff --git a/riscv/test/riscv_clint_test.cc b/riscv/test/riscv_clint_test.cc
index d15023f..d5f9b46 100644
--- a/riscv/test/riscv_clint_test.cc
+++ b/riscv/test/riscv_clint_test.cc
@@ -32,7 +32,7 @@
     state_ = new RiscVState("test", RiscVXlen::RV32, &memory_);
     state_->set_on_trap([this](bool is_interrupt, uint64_t trap_value,
                                uint64_t exception_code, uint64_t epc,
-                               const Instruction *inst) {
+                               const Instruction* inst) {
       return TrapHandler(is_interrupt, trap_value, exception_code, epc, inst);
     });
     cycle_counter_.Initialize("cycle_counter", 0);
@@ -43,26 +43,26 @@
   // Gets called on a trap.
   bool TrapHandler(bool is_interrupt, uint64_t trap_value,
                    uint64_t exception_code, uint64_t epc,
-                   const Instruction *inst);
+                   const Instruction* inst);
 
   FlatDemandMemory memory_;
   // Counter.
   SimpleCounter<uint64_t> cycle_counter_;
   // CherIoT state.
-  RiscVState *state_;
+  RiscVState* state_;
   // Latched trap info.
   bool trap_taken_ = false;
   bool trap_is_interrupt_ = false;
   uint64_t trap_value_ = 0;
   uint64_t trap_exception_code_ = 0;
   uint64_t trap_epc_ = 0;
-  const Instruction *trap_inst_ = nullptr;
+  const Instruction* trap_inst_ = nullptr;
 };
 
 // Called when there is a trap in the CherIoT state.
 bool RiscVClintTest::TrapHandler(bool is_interrupt, uint64_t trap_value,
                                  uint64_t exception_code, uint64_t epc,
-                                 const Instruction *inst) {
+                                 const Instruction* inst) {
   trap_taken_ = true;
   trap_is_interrupt_ = is_interrupt;
   trap_value_ = trap_value;
@@ -74,9 +74,9 @@
 
 // Test loads and stores for msip memory mapped register.
 TEST_F(RiscVClintTest, MSip) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, 0xdeadbeef);
-  auto *clint = new RiscVClint(/*period=*/1, state_->mip());
+  auto* clint = new RiscVClint(/*period=*/1, state_->mip());
   cycle_counter_.AddListener(clint);
   // Initial value should be zero.
   clint->Load(kMSip, db, nullptr, nullptr);
@@ -110,8 +110,8 @@
 
 // Test reads/writes to mtimecmp.
 TEST_F(RiscVClintTest, MTimeCmp) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
-  auto *clint = new RiscVClint(/*period=*/100, state_->mip());
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* clint = new RiscVClint(/*period=*/100, state_->mip());
   cycle_counter_.AddListener(clint);
 
   // Verify value of mtimecmp.
@@ -180,7 +180,7 @@
 
 // Test the reads/writes to mtime.
 TEST_F(RiscVClintTest, MTime) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   auto clint = new RiscVClint(/*period=*/100, state_->mip());
   cycle_counter_.AddListener(clint);
   // Initial value should be zero.
diff --git a/riscv/test/riscv_csr_test.cc b/riscv/test/riscv_csr_test.cc
index 10801d3..0ab2a2e 100644
--- a/riscv/test/riscv_csr_test.cc
+++ b/riscv/test/riscv_csr_test.cc
@@ -52,12 +52,12 @@
   ~RiscV32CsrTest() override { delete state_; }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
+  RiscVState* state_;
 };
 
 // Test that the simple csr constructs properly and with the expected values.
 TEST_F(RiscV32CsrTest, SimpleCsrConstruction) {
-  auto *csr0 = new RiscV32SimpleCsr(kCsrName0, RiscVCsrEnum::kUScratch,
+  auto* csr0 = new RiscV32SimpleCsr(kCsrName0, RiscVCsrEnum::kUScratch,
                                     kDeadBeef, state_);
   EXPECT_EQ(csr0->name(), kCsrName0);
   EXPECT_EQ(csr0->index(), static_cast<int>(RiscVCsrEnum::kUScratch));
@@ -68,7 +68,7 @@
   EXPECT_EQ(csr0->read_mask(), kReadMask);
   EXPECT_EQ(csr0->write_mask(), kWriteMask);
 
-  auto *csr1 = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
+  auto* csr1 = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
                                     kReadMask, kWriteMask, state_);
   EXPECT_EQ(csr1->name(), kCsrName1);
   EXPECT_EQ(csr1->index(), static_cast<int>(RiscVCsrEnum::kMScratch));
@@ -81,7 +81,7 @@
 
 // Read and write values from/to the csr.
 TEST_F(RiscV32CsrTest, SimpleCsrReadWrite) {
-  auto *csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
+  auto* csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
                                    kReadMask, kWriteMask, state_);
   EXPECT_EQ(csr->AsUint32(), kA5 & kReadMask);
   csr->Write(kAllOnes);
@@ -93,7 +93,7 @@
 
 // Raw read/writes.
 TEST_F(RiscV32CsrTest, SimpleCsrSetGet) {
-  auto *csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
+  auto* csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kMScratch, kA5,
                                    kReadMask, kWriteMask, state_);
   EXPECT_EQ(csr->GetUint32(), kA5);
   csr->Set(kAllOnes);
@@ -105,7 +105,7 @@
 // Test the csr-set class.
 TEST_F(RiscV32CsrTest, CsrSet) {
   // Allocate new csr.
-  auto *csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kUScratch, kA5,
+  auto* csr = new RiscV32SimpleCsr(kCsrName1, RiscVCsrEnum::kUScratch, kA5,
                                    kReadMask, kWriteMask, state_);
   // Add it to the set, then try to add it again. The second attempt should
   // fail.
@@ -116,7 +116,7 @@
   auto result =
       state_->csr_set()->GetCsr(static_cast<int>(RiscVCsrEnum::kUScratch));
   EXPECT_OK(result.status());
-  auto *stored_csr = result.value();
+  auto* stored_csr = result.value();
   EXPECT_EQ(stored_csr, csr);
   EXPECT_EQ(stored_csr->AsUint32(), (kA5 & kReadMask));
   // Getting a different csr should fail.
@@ -127,12 +127,12 @@
 
 // Test that the shadow csr constructs properly and with the expected values.
 TEST_F(RiscV32CsrTest, ShadowCsrConstruction) {
-  auto *csr0 = new RiscV32SimpleCsr(kCsrName0, RiscVCsrEnum::kMScratch,
+  auto* csr0 = new RiscV32SimpleCsr(kCsrName0, RiscVCsrEnum::kMScratch,
                                     kDeadBeef, state_);
   EXPECT_EQ(csr0->name(), kCsrName0);
   EXPECT_EQ(csr0->index(), static_cast<int>(RiscVCsrEnum::kMScratch));
 
-  auto *csr1 = new RiscVShadowCsr<uint32_t>(
+  auto* csr1 = new RiscVShadowCsr<uint32_t>(
       kCsrName1, RiscVCsrEnum::kUScratch, kReadMask, kWriteMask, state_, csr0);
   EXPECT_EQ(csr1->name(), kCsrName1);
   EXPECT_EQ(csr1->index(), static_cast<int>(RiscVCsrEnum::kUScratch));
diff --git a/riscv/test/riscv_d_instructions_test.cc b/riscv/test/riscv_d_instructions_test.cc
index c6658ba..096cbce 100644
--- a/riscv/test/riscv_d_instructions_test.cc
+++ b/riscv/test/riscv_d_instructions_test.cc
@@ -62,7 +62,7 @@
 
 static bool is_snan(double a) {
   if (!std::isnan(a)) return false;
-  auto ua = *reinterpret_cast<uint64_t *>(&a);
+  auto ua = *reinterpret_cast<uint64_t*>(&a);
   if ((ua & (1ULL << (FPTypeInfo<double>::kSigSize - 1))) == 0) return true;
   return false;
 }
@@ -107,13 +107,13 @@
         double res;
         if (lhs > 0) {
           res = sqrt(lhs);
-          uint64_t dhls = *reinterpret_cast<uint64_t *>(&lhs);
+          uint64_t dhls = *reinterpret_cast<uint64_t*>(&lhs);
           // Get exponent of source value.
           int exp = (dhls & FPTypeInfo<double>::kExpMask) >>
                     FPTypeInfo<double>::kSigSize;
           exp -= FPTypeInfo<double>::kExpBias;
           // Get significand of result.
-          uint64_t dres = *reinterpret_cast<uint64_t *>(&res);
+          uint64_t dres = *reinterpret_cast<uint64_t*>(&res);
           uint64_t sig = dres & FPTypeInfo<double>::kSigMask;
           bool is_square;
           // Slightly different test based on whether the exponent of the source
@@ -132,7 +132,7 @@
           flags = *FPExceptions::kInvalidOp;
         }
         uint64_t val = FPTypeInfo<double>::kCanonicalNaN;
-        res = *reinterpret_cast<const double *>(&val);
+        res = *reinterpret_cast<const double*>(&val);
         return std::tie(res, flags);
       });
 }
@@ -149,7 +149,7 @@
         }
         if (std::isnan(lhs) && std::isnan(rhs)) {
           uint64_t val = FPTypeInfo<double>::kCanonicalNaN;
-          return std::tie(*reinterpret_cast<const double *>(&val), flag);
+          return std::tie(*reinterpret_cast<const double*>(&val), flag);
         }
         if (std::isnan(lhs)) return std::tie(rhs, flag);
         if (std::isnan(rhs)) return std::tie(lhs, flag);
@@ -171,7 +171,7 @@
         }
         if (std::isnan(lhs) && std::isnan(rhs)) {
           uint64_t val = FPTypeInfo<double>::kCanonicalNaN;
-          return std::tie(*reinterpret_cast<const double *>(&val), flag);
+          return std::tie(*reinterpret_cast<const double*>(&val), flag);
         }
         if (std::isnan(lhs)) return std::tie(rhs, flag);
         if (std::isnan(rhs)) return std::tie(lhs, flag);
@@ -299,10 +299,10 @@
   BinaryOpFPTestHelper<double, double, double>(
       "dsgnjn", instruction_, {"d", "d", "d"}, 64,
       [](double lhs, double rhs) -> double {
-        auto lhs_u = *reinterpret_cast<uint64_t *>(&lhs);
-        auto rhs_u = *reinterpret_cast<uint64_t *>(&rhs);
+        auto lhs_u = *reinterpret_cast<uint64_t*>(&lhs);
+        auto rhs_u = *reinterpret_cast<uint64_t*>(&rhs);
         auto res_u = (lhs_u ^ rhs_u) & 0x8000'0000'0000'0000;
-        auto res = *reinterpret_cast<double *>(&res_u);
+        auto res = *reinterpret_cast<double*>(&res_u);
         return copysign(abs(lhs), res);
       });
 }
@@ -358,7 +358,7 @@
             return std::signbit(lhs) ? 1 : 1 << 7;
           case FP_NAN: {
             auto uint_val =
-                *reinterpret_cast<typename FPTypeInfo<double>::IntType *>(&lhs);
+                *reinterpret_cast<typename FPTypeInfo<double>::IntType*>(&lhs);
             bool quiet_nan =
                 (uint_val >> (FPTypeInfo<double>::kSigSize - 1)) & 1;
             return quiet_nan ? 1 << 9 : 1 << 8;
diff --git a/riscv/test/riscv_f_instructions_test.cc b/riscv/test/riscv_f_instructions_test.cc
index ccfc110..91177b2 100644
--- a/riscv/test/riscv_f_instructions_test.cc
+++ b/riscv/test/riscv_f_instructions_test.cc
@@ -59,7 +59,7 @@
 
 static bool is_snan(float a) {
   if (!std::isnan(a)) return false;
-  uint32_t ua = *reinterpret_cast<uint32_t *>(&a);
+  uint32_t ua = *reinterpret_cast<uint32_t*>(&a);
   if ((ua & (1 << (FPTypeInfo<float>::kSigSize - 1))) == 0) return true;
   return false;
 }
@@ -114,7 +114,7 @@
           flags = *FPExceptions::kInvalidOp;
         }
         uint32_t val = FPTypeInfo<float>::kCanonicalNaN;
-        res = *reinterpret_cast<const float *>(&val);
+        res = *reinterpret_cast<const float*>(&val);
         return std::tie(res, flags);
       });
 }
@@ -131,7 +131,7 @@
         }
         if (std::isnan(lhs) && std::isnan(rhs)) {
           uint32_t val = FPTypeInfo<float>::kCanonicalNaN;
-          return std::tie(*reinterpret_cast<const float *>(&val), flag);
+          return std::tie(*reinterpret_cast<const float*>(&val), flag);
         }
         if (std::isnan(lhs)) return std::tie(rhs, flag);
         if (std::isnan(rhs)) return std::tie(lhs, flag);
@@ -153,7 +153,7 @@
         }
         if (std::isnan(lhs) && std::isnan(rhs)) {
           uint32_t val = FPTypeInfo<float>::kCanonicalNaN;
-          return std::tie(*reinterpret_cast<const float *>(&val), flag);
+          return std::tie(*reinterpret_cast<const float*>(&val), flag);
         }
         if (std::isnan(lhs)) return std::tie(rhs, flag);
         if (std::isnan(rhs)) return std::tie(lhs, flag);
@@ -259,10 +259,10 @@
   BinaryOpFPTestHelper<float, float, float>(
       "fsgnjn", instruction_, {"f", "f", "f"}, 32,
       [](float lhs, float rhs) -> float {
-        auto lhs_u = *reinterpret_cast<uint32_t *>(&lhs);
-        auto rhs_u = *reinterpret_cast<uint32_t *>(&rhs);
+        auto lhs_u = *reinterpret_cast<uint32_t*>(&lhs);
+        auto rhs_u = *reinterpret_cast<uint32_t*>(&rhs);
         auto res_u = (lhs_u ^ rhs_u) & 0x8000'0000;
-        auto res = *reinterpret_cast<float *>(&res_u);
+        auto res = *reinterpret_cast<float*>(&res_u);
         return copysign(abs(lhs), res);
       });
 }
@@ -318,7 +318,7 @@
             return std::signbit(lhs) ? 1 : 1 << 7;
           case FP_NAN: {
             auto uint_val =
-                *reinterpret_cast<typename FPTypeInfo<float>::IntType *>(&lhs);
+                *reinterpret_cast<typename FPTypeInfo<float>::IntType*>(&lhs);
             bool quiet_nan =
                 (uint_val >> (FPTypeInfo<float>::kSigSize - 1)) & 1;
             return quiet_nan ? 1 << 9 : 1 << 8;
diff --git a/riscv/test/riscv_fp_host_test.cc b/riscv/test/riscv_fp_host_test.cc
index e8b589e..65ec654 100644
--- a/riscv/test/riscv_fp_host_test.cc
+++ b/riscv/test/riscv_fp_host_test.cc
@@ -26,13 +26,13 @@
     delete instruction_;
   }
 
-  HostFloatingPointInterface *host_fp_interface_;
-  Instruction *instruction_;
+  HostFloatingPointInterface* host_fp_interface_;
+  Instruction* instruction_;
 };
 
 static float sum = 0.0;
 
-static void simple_add(const Instruction *inst) { sum += 1.0; }
+static void simple_add(const Instruction* inst) { sum += 1.0; }
 
 TEST_F(RiscVFPHostTest, SetGetCsr) {
   // Run through all the different values of the csr status bits.
diff --git a/riscv/test/riscv_fp_test_base.h b/riscv/test/riscv_fp_test_base.h
index d54889b..ed5c528 100644
--- a/riscv/test/riscv_fp_test_base.h
+++ b/riscv/test/riscv_fp_test_base.h
@@ -297,7 +297,7 @@
 template <typename S, typename D>
 struct GreaterSize {
   static const bool value =
-      sizeof(S) > sizeof(D) && IsMpactFp<S>::value &&std::is_integral<D>::value;
+      sizeof(S) > sizeof(D) && IsMpactFp<S>::value&& std::is_integral<D>::value;
 };
 
 template <typename S, typename D>
@@ -353,7 +353,7 @@
     child_instruction_ = new Instruction(kInstAddress, state_);
     child_instruction_->set_size(4);
     // Initialize a portion of memory with a known pattern.
-    auto *db = state_->db_factory()->Allocate(8192);
+    auto* db = state_->db_factory()->Allocate(8192);
     auto span = db->Get<uint8_t>();
     for (int i = 0; i < 8192; i++) {
       span[i] = i & 0xff;
@@ -389,15 +389,15 @@
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
   template <typename T>
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
@@ -405,18 +405,18 @@
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
   template <typename T>
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands<T>(instruction_, sources, destinations);
   }
 
   // named register and sets it to the corresponding value.
   template <typename T, typename RegisterType = XRegister>
   void SetRegisterValues(
-      const std::vector<std::tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RegisterType>(reg_name).first;
-      auto *db =
+      const std::vector<std::tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RegisterType>(reg_name).first;
+      auto* db =
           state_->db_factory()->Allocate<typename RegisterType::ValueType>(1);
       db->template Set<T>(0, value);
       reg->SetDataBuffer(db);
@@ -426,12 +426,12 @@
 
   template <typename T, typename RegisterType = XRegister>
   void SetNaNBoxedRegisterValues(
-      const std::vector<std::tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
+      const std::vector<std::tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
       typename RegisterType::ValueType reg_value =
           NaNBox<T, typename RegisterType::ValueType>(value);
-      auto *reg = state_->GetRegister<RegisterType>(reg_name).first;
-      auto *db =
+      auto* reg = state_->GetRegister<RegisterType>(reg_name).first;
+      auto* db =
           state_->db_factory()->Allocate<typename RegisterType::ValueType>(1);
       db->template Set<typename RegisterType::ValueType>(0, reg_value);
       reg->SetDataBuffer(db);
@@ -440,7 +440,7 @@
   }
 
   // Initializes the semantic function of the instruction object.
-  void SetSemanticFunction(Instruction *inst,
+  void SetSemanticFunction(Instruction* inst,
                            Instruction::SemanticFunction fcn) {
     inst->set_semantic_function(fcn);
   }
@@ -477,13 +477,13 @@
   // This method uses random values for each field in the fp number.
   template <typename T>
   void FillArrayWithRandomFPValues(absl::Span<T> span) {
-    for (auto &val : span) {
+    for (auto& val : span) {
       val = RandomFPValue<T>();
     }
   }
 
   template <typename R, typename LHS>
-  void UnaryOpFPTestHelper(absl::string_view name, Instruction *inst,
+  void UnaryOpFPTestHelper(absl::string_view name, Instruction* inst,
                            absl::Span<const absl::string_view> reg_prefixes,
                            int delta_position,
                            std::function<R(LHS)> operation) {
@@ -508,14 +508,14 @@
     AppendRegisterOperands<XRegister>({kRmName}, {});
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       if constexpr (std::is_integral<LHS>::value) {
         SetRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
@@ -550,7 +550,7 @@
   // Tester for unary instructions that produce an exception flag value.
   template <typename R, typename LHS>
   void UnaryOpWithFflagsFPTestHelper(
-      absl::string_view name, Instruction *inst,
+      absl::string_view name, Instruction* inst,
       absl::Span<const absl::string_view> reg_prefixes, int delta_position,
       std::function<std::tuple<R, uint32_t>(LHS, uint32_t)> operation) {
     using LhsRegisterType = RVFpRegister;
@@ -574,17 +574,17 @@
       AppendRegisterOperands<RVFpRegister>({}, {kRdName});
     }
     AppendRegisterOperands<XRegister>({kRmName}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       if constexpr (std::is_integral<LHS>::value) {
         SetRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
@@ -630,7 +630,7 @@
 
   // Test helper for binary fp instructions.
   template <typename R, typename LHS, typename RHS>
-  void BinaryOpFPTestHelper(absl::string_view name, Instruction *inst,
+  void BinaryOpFPTestHelper(absl::string_view name, Instruction* inst,
                             absl::Span<const absl::string_view> reg_prefixes,
                             int delta_position,
                             std::function<R(LHS, RHS)> operation) {
@@ -662,19 +662,19 @@
       AppendRegisterOperands<RVFpRegister>({}, {kRdName});
     }
     AppendRegisterOperands<XRegister>({kRmName}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     FillArrayWithRandomFPValues<RHS>(rhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       SetNaNBoxedRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
       SetNaNBoxedRegisterValues<RHS, RhsRegisterType>({{kR2Name, rhs_span[i]}});
@@ -709,7 +709,7 @@
   // value.
   template <typename R, typename LHS, typename RHS>
   void BinaryOpWithFflagsFPTestHelper(
-      absl::string_view name, Instruction *inst,
+      absl::string_view name, Instruction* inst,
       absl::Span<const absl::string_view> reg_prefixes, int delta_position,
       std::function<std::tuple<R, uint32_t>(LHS, RHS)> operation) {
     using LhsRegisterType = RVFpRegister;
@@ -742,19 +742,19 @@
       AppendRegisterOperands<RVFpRegister>({}, {kRdName});
     }
     AppendRegisterOperands<XRegister>({kRmName}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     FillArrayWithRandomFPValues<RHS>(rhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       SetNaNBoxedRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
       SetNaNBoxedRegisterValues<RHS, RhsRegisterType>({{kR2Name, rhs_span[i]}});
@@ -795,7 +795,7 @@
   }
 
   template <typename R, typename LHS, typename MHS, typename RHS>
-  void TernaryOpFPTestHelper(absl::string_view name, Instruction *inst,
+  void TernaryOpFPTestHelper(absl::string_view name, Instruction* inst,
                              absl::Span<const absl::string_view> reg_prefixes,
                              int delta_position,
                              std::function<R(LHS, MHS, RHS)> operation) {
@@ -840,14 +840,14 @@
     FillArrayWithRandomFPValues<MHS>(mhs_span);
     FillArrayWithRandomFPValues<RHS>(rhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       SetNaNBoxedRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
       SetNaNBoxedRegisterValues<MHS, MhsRegisterType>({{kR2Name, mhs_span[i]}});
@@ -879,7 +879,7 @@
 
   template <typename R, typename LHS, typename MHS, typename RHS>
   void TernaryOpWithFflagsFPTestHelper(
-      absl::string_view name, Instruction *inst,
+      absl::string_view name, Instruction* inst,
       absl::Span<const absl::string_view> reg_prefixes, int delta_position,
       std::function<R(LHS, MHS, RHS)> operation) {
     using LhsRegisterType = RVFpRegister;
@@ -919,20 +919,20 @@
       AppendRegisterOperands<RVFpRegister>({}, {kRdName});
     }
     AppendRegisterOperands<XRegister>({kRmName}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     FillArrayWithRandomFPValues<MHS>(mhs_span);
     FillArrayWithRandomFPValues<RHS>(rhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
     for (int i = 0; i < kTestValueLength; i++) {
       SetNaNBoxedRegisterValues<LHS, LhsRegisterType>({{kR1Name, lhs_span[i]}});
       SetNaNBoxedRegisterValues<MHS, MhsRegisterType>({{kR2Name, mhs_span[i]}});
@@ -972,20 +972,16 @@
     }
   }
 
-  absl::Span<XRegister *> xreg() { return absl::Span<XRegister *>(xreg_); }
+  absl::Span<XRegister*> xreg() { return absl::Span<XRegister*>(xreg_); }
 
-  absl::Span<RVFpRegister *> freg() {
-    return absl::Span<RVFpRegister *>(freg_);
-  }
+  absl::Span<RVFpRegister*> freg() { return absl::Span<RVFpRegister*>(freg_); }
 
-  absl::Span<RV64Register *> dreg() {
-    return absl::Span<RV64Register *>(dreg_);
-  }
-  absl::BitGen &bitgen() { return bitgen_; }
-  Instruction *instruction() { return instruction_; }
+  absl::Span<RV64Register*> dreg() { return absl::Span<RV64Register*>(dreg_); }
+  absl::BitGen& bitgen() { return bitgen_; }
+  Instruction* instruction() { return instruction_; }
 
   template <typename From, typename To>
-  To RoundToInteger(From val, uint32_t rm, uint32_t &flags) {
+  To RoundToInteger(From val, uint32_t rm, uint32_t& flags) {
     constexpr To kMax = std::numeric_limits<To>::max();
     constexpr To kMin = std::numeric_limits<To>::min();
     To value = 0;
@@ -1150,14 +1146,14 @@
   }
 
  protected:
-  XRegister *xreg_[32];
-  RV64Register *dreg_[32];
-  RVFpRegister *freg_[32];
-  RiscVState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
-  FlatDemandMemory *memory_;
-  RiscVFPState *rv_fp_;
+  XRegister* xreg_[32];
+  RV64Register* dreg_[32];
+  RVFpRegister* freg_[32];
+  RiscVState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
+  FlatDemandMemory* memory_;
+  RiscVFPState* rv_fp_;
   absl::BitGen bitgen_;
 };
 
@@ -1376,7 +1372,7 @@
   U Convert(FPRoundingMode rm = FPRoundingMode::kRoundToNearest);
 
   template <typename U>
-  U ConvertWithFlags(uint32_t &fflags,
+  U ConvertWithFlags(uint32_t& fflags,
                      FPRoundingMode rm = FPRoundingMode::kRoundToNearest) {
     fflags_ = 0;
     U ret = Convert<U>(rm);
@@ -1396,8 +1392,8 @@
 
   template <typename IntReturnType, typename FpReturnType>
   void NarrowingConversionMakeExponentAndSignificand(FPRoundingMode,
-                                                     IntReturnType &,
-                                                     IntReturnType &);
+                                                     IntReturnType&,
+                                                     IntReturnType&);
 
   template <typename IntReturnType, typename FpReturnType>
   IntReturnType NarrowingConversionHandleInfinity(FPRoundingMode);
@@ -1423,18 +1419,18 @@
     return value;
   }
 
-  const int *GetRoundingTable(FPRoundingMode rm) {
+  const int* GetRoundingTable(FPRoundingMode rm) {
     switch (rm) {
       case FPRoundingMode::kRoundToNearest:
-        return static_cast<const int *>(internal::kRoundToNearestTable);
+        return static_cast<const int*>(internal::kRoundToNearestTable);
       case FPRoundingMode::kRoundTowardsZero:
-        return static_cast<const int *>(internal::kRoundTowardsZeroTable);
+        return static_cast<const int*>(internal::kRoundTowardsZeroTable);
       case FPRoundingMode::kRoundDown:
-        return static_cast<const int *>(internal::kRoundDownTable);
+        return static_cast<const int*>(internal::kRoundDownTable);
       case FPRoundingMode::kRoundUp:
-        return static_cast<const int *>(internal::kRoundUpTable);
+        return static_cast<const int*>(internal::kRoundUpTable);
       default:
-        return static_cast<const int *>(internal::kRoundToNearestTable);
+        return static_cast<const int*>(internal::kRoundToNearestTable);
     }
   }
 };  // class FpConversionsTestHelper
@@ -1510,8 +1506,8 @@
 template <typename T>
 template <typename IntReturnType, typename FpReturnType>
 void FpConversionsTestHelper<T>::NarrowingConversionMakeExponentAndSignificand(
-    FPRoundingMode rm, IntReturnType &out_exponent,
-    IntReturnType &out_significand) {
+    FPRoundingMode rm, IntReturnType& out_exponent,
+    IntReturnType& out_significand) {
   int32_t e_max = FPTypeInfo<FpReturnType>::kExpBias;
   int32_t e_min = 1 - e_max;
   IntType in_exponent = (unsigned_value_ & FPTypeInfo<FpType>::kExpMask) >>
diff --git a/riscv/test/riscv_getters_zfh.h b/riscv/test/riscv_getters_zfh.h
index 0722c3e..4ec622f 100644
--- a/riscv/test/riscv_getters_zfh.h
+++ b/riscv/test/riscv_getters_zfh.h
@@ -35,10 +35,10 @@
 using ::mpact::sim::generic::operator*;  // NOLINT: is used below (clang error).
 
 template <typename Enum, typename Extractors, typename IntegerRegister>
-void AddRiscVZfhSourceScalarGetters(SourceOpGetterMap &getter_map,
-                                    RiscVEncodingCommon *common) {
+void AddRiscVZfhSourceScalarGetters(SourceOpGetterMap& getter_map,
+                                    RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::Inst32Format::ExtractRs1(common->inst_word());
     if (num == 0) return new generic::IntLiteralOperand<0>({1});
     return GetRegisterSourceOp<IntegerRegister>(
@@ -46,16 +46,16 @@
         kXRegisterAliases[num]);
   });
   // I in IImm12 stands for IType instructions.
-  Insert(getter_map, *Enum::kIImm12, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kIImm12, [common]() -> SourceOperandInterface* {
     const auto num = Extractors::IType::ExtractImm12(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
   // S in SImm12 stands for SType instructions.
-  Insert(getter_map, *Enum::kSImm12, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kSImm12, [common]() -> SourceOperandInterface* {
     const auto num = Extractors::SType::ExtractSImm(common->inst_word());
     return new generic::ImmediateOperand<int32_t>(num);
   });
-  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kRm, [common]() -> SourceOperandInterface* {
     const auto num =
         Extractors::Inst32Format::ExtractFunc3(common->inst_word());
     return new generic::ImmediateOperand<uint8_t>(num);
@@ -63,22 +63,22 @@
 }
 
 template <typename Enum, typename Extractors, typename FloatRegister>
-void AddRiscVZfhSourceFloatGetters(SourceOpGetterMap &getter_map,
-                                   RiscVEncodingCommon *common) {
+void AddRiscVZfhSourceFloatGetters(SourceOpGetterMap& getter_map,
+                                   RiscVEncodingCommon* common) {
   // Source operand getters.
-  Insert(getter_map, *Enum::kFrs1, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs1, [common]() -> SourceOperandInterface* {
     int num = Extractors::Inst32Format::ExtractRs1(common->inst_word());
     return GetRegisterSourceOp<FloatRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kFrs2, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs2, [common]() -> SourceOperandInterface* {
     int num = Extractors::Inst32Format::ExtractRs2(common->inst_word());
     return GetRegisterSourceOp<FloatRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
         kFRegisterAliases[num]);
   });
-  Insert(getter_map, *Enum::kFrs3, [common]() -> SourceOperandInterface * {
+  Insert(getter_map, *Enum::kFrs3, [common]() -> SourceOperandInterface* {
     int num = Extractors::Inst32Format::ExtractRs3(common->inst_word());
     return GetRegisterSourceOp<FloatRegister>(
         common->state(), absl::StrCat(RiscVState::kFregPrefix, num),
@@ -87,29 +87,29 @@
 }
 
 template <typename Enum, typename Extractors, typename IntegerRegister>
-void AddRiscVZfhDestScalarGetters(DestOpGetterMap &getter_map,
-                                  RiscVEncodingCommon *common) {
+void AddRiscVZfhDestScalarGetters(DestOpGetterMap& getter_map,
+                                  RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kRd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            auto num = Extractors::Inst32Format::ExtractRd(common->inst_word());
            std::string name = absl::StrCat(RiscVState::kXregPrefix, num);
            return mpact::sim::riscv::GetRegisterDestinationOp<IntegerRegister>(
                common->state(), name, latency);
          });
   Insert(getter_map, *Enum::kFflags,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            return GetCSRSetBitsDestinationOp<uint32_t>(common->state(),
                                                        "fflags", latency, "");
          });
 }
 
 template <typename Enum, typename Extractors, typename FloatRegister>
-void AddRiscVZfhDestFloatGetters(DestOpGetterMap &getter_map,
-                                 RiscVEncodingCommon *common) {
+void AddRiscVZfhDestFloatGetters(DestOpGetterMap& getter_map,
+                                 RiscVEncodingCommon* common) {
   // Destination operand getters.
   Insert(getter_map, *Enum::kFrd,
-         [common](int latency) -> DestinationOperandInterface * {
+         [common](int latency) -> DestinationOperandInterface* {
            auto num = Extractors::Inst32Format::ExtractRd(common->inst_word());
            std::string name = absl::StrCat(RiscVState::kFregPrefix, num);
            return mpact::sim::riscv::GetRegisterDestinationOp<FloatRegister>(
@@ -123,8 +123,8 @@
 // extraction functions, and the IntRegister and FpRegister types that are used
 // to construct the register operand.
 template <typename Enum, typename Extractors>
-void AddRiscVZfhSimpleResourceGetters(SimpleResourceGetterMap &getter_map,
-                                      RiscVEncodingCommon *common) {
+void AddRiscVZfhSimpleResourceGetters(SimpleResourceGetterMap& getter_map,
+                                      RiscVEncodingCommon* common) {
   // TODO(julianmb): Add resource getters when appropriate.
 }
 
diff --git a/riscv/test/riscv_i_instructions_test.cc b/riscv/test/riscv_i_instructions_test.cc
index 1584c52..be6f98e 100644
--- a/riscv/test/riscv_i_instructions_test.cc
+++ b/riscv/test/riscv_i_instructions_test.cc
@@ -71,29 +71,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -102,9 +102,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -119,13 +119,13 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
-  FlatDemandMemory *memory_;
-  RiscVState *state_;
-  Instruction *instruction_;
+  FlatDemandMemory* memory_;
+  RiscVState* state_;
+  Instruction* instruction_;
 };
 
 // Almost all the tests below follow the same pattern. There are two phases.
@@ -407,7 +407,7 @@
 
 TEST_F(RV32IInstructionTest, RV32ILw) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -416,7 +416,7 @@
   AppendRegisterOperands({kX1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::riscv::RV32::RiscVILw);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::riscv::RV32::RiscVILwChild);
   AppendRegisterOperands(child, {}, {kX3});
   instruction_->AppendChild(child);
@@ -429,7 +429,7 @@
 
 TEST_F(RV32IInstructionTest, RV32ILh) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -438,7 +438,7 @@
   AppendRegisterOperands({kX1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::riscv::RV32::RiscVILh);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::riscv::RV32::RiscVILhChild);
   AppendRegisterOperands(child, {}, {kX3});
   instruction_->AppendChild(child);
@@ -451,7 +451,7 @@
 
 TEST_F(RV32IInstructionTest, RV32ILhu) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -460,7 +460,7 @@
   AppendRegisterOperands({kX1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::riscv::RV32::RiscVILhu);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::riscv::RV32::RiscVILhuChild);
   AppendRegisterOperands(child, {}, {kX3});
   instruction_->AppendChild(child);
@@ -473,7 +473,7 @@
 
 TEST_F(RV32IInstructionTest, RV32ILb) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -482,7 +482,7 @@
   AppendRegisterOperands({kX1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::riscv::RV32::RiscVILb);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::riscv::RV32::RiscVILbChild);
   AppendRegisterOperands(child, {}, {kX3});
   instruction_->AppendChild(child);
@@ -495,7 +495,7 @@
 
 TEST_F(RV32IInstructionTest, RV32ILbu) {
   // Initialize memory.
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   db->Set<uint32_t>(0, kMemValue);
   state_->StoreMemory(instruction_, kMemAddress + kOffset, db);
   db->DecRef();
@@ -504,7 +504,7 @@
   AppendRegisterOperands({kX1}, {});
   AppendImmediateOperands<uint32_t>({kOffset});
   SetSemanticFunction(&::mpact::sim::riscv::RV32::RiscVILbu);
-  auto *child = new Instruction(state_);
+  auto* child = new Instruction(state_);
   child->set_semantic_function(&::mpact::sim::riscv::RV32::RiscVILbuChild);
   AppendRegisterOperands(child, {}, {kX3});
   instruction_->AppendChild(child);
@@ -526,7 +526,7 @@
 
   SetRegisterValues<uint32_t>({{kX1, kMemAddress}, {kX3, kMemValue}});
   instruction_->Execute(nullptr);
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), kMemValue);
   db->DecRef();
@@ -540,7 +540,7 @@
   SetRegisterValues<uint32_t>({{kX1, kMemAddress}, {kX3, kMemValue}});
   instruction_->Execute(nullptr);
 
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), static_cast<uint16_t>(kMemValue));
   db->DecRef();
@@ -554,7 +554,7 @@
   SetRegisterValues<uint32_t>({{kX1, kMemAddress}, {kX3, kMemValue}});
   instruction_->Execute(nullptr);
 
-  auto *db = state_->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(1);
   state_->LoadMemory(instruction_, kMemAddress + kOffset, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), static_cast<uint8_t>(kMemValue));
   db->DecRef();
diff --git a/riscv/test/riscv_plic_test.cc b/riscv/test/riscv_plic_test.cc
index 62c150c..0473f53 100644
--- a/riscv/test/riscv_plic_test.cc
+++ b/riscv/test/riscv_plic_test.cc
@@ -150,15 +150,15 @@
   }
 
   // Accessors.
-  RiscVPlic *plic() { return plic_; }
-  DataBufferFactory &db_factory() { return db_factory_; }
-  MockRiscVInterruptTarget *target(int i) { return target_[i]; }
+  RiscVPlic* plic() { return plic_; }
+  DataBufferFactory& db_factory() { return db_factory_; }
+  MockRiscVInterruptTarget* target(int i) { return target_[i]; }
 
  private:
-  DataBuffer *db_;
+  DataBuffer* db_;
   DataBufferFactory db_factory_;
-  RiscVPlic *plic_ = nullptr;
-  MockRiscVInterruptTarget *target_[kNumContexts];
+  RiscVPlic* plic_ = nullptr;
+  MockRiscVInterruptTarget* target_[kNumContexts];
 };
 
 // Test that the initial state of the PLIC is as expected. Nothing enabled,
diff --git a/riscv/test/riscv_state_test.cc b/riscv/test/riscv_state_test.cc
index eb29b70..26fca24 100644
--- a/riscv/test/riscv_state_test.cc
+++ b/riscv/test/riscv_state_test.cc
@@ -40,23 +40,23 @@
 
 TEST(RiscVStateTest, Basic) {
   FlatDemandMemory memory;
-  auto *state = new RiscVState("test", RiscVXlen::RV32, &memory);
+  auto* state = new RiscVState("test", RiscVXlen::RV32, &memory);
   // Make sure pc has been created.
   auto iter = state->registers()->find("pc");
-  auto *ptr = (iter != state->registers()->end()) ? iter->second : nullptr;
+  auto* ptr = (iter != state->registers()->end()) ? iter->second : nullptr;
   CHECK_NE(ptr, nullptr);
   // Set pc to 0x1000, then read value back through pc operand.
-  auto *pc = static_cast<RV32Register *>(ptr);
+  auto* pc = static_cast<RV32Register*>(ptr);
   pc->data_buffer()->Set<uint32_t>(0, kPcValue);
-  auto *pc_op = state->pc_operand();
+  auto* pc_op = state->pc_operand();
   EXPECT_EQ(pc_op->AsUint32(0), kPcValue);
   delete state;
 }
 
 TEST(RiscVStateTest, Memory) {
   FlatDemandMemory memory;
-  auto *state = new RiscVState("test", RiscVXlen::RV32, &memory);
-  auto *db = state->db_factory()->Allocate<uint32_t>(1);
+  auto* state = new RiscVState("test", RiscVXlen::RV32, &memory);
+  auto* db = state->db_factory()->Allocate<uint32_t>(1);
   state->LoadMemory(nullptr, kMemAddr, db, nullptr, nullptr);
   EXPECT_EQ(db->Get<uint32_t>(0), 0);
   db->Set<uint32_t>(0, kMemValue);
@@ -70,11 +70,11 @@
 
 TEST(RiscVStateTest, OutOfBoundLoad) {
   FlatDemandMemory memory;
-  auto *state = new RiscVState("test", RiscVXlen::RV32, &memory);
+  auto* state = new RiscVState("test", RiscVXlen::RV32, &memory);
   state->set_max_physical_address(kMemAddr - 4);
   state->set_on_trap([](bool is_interrupt, uint64_t trap_value,
                         uint64_t exception_code, uint64_t epc,
-                        const mpact::sim::riscv::Instruction *inst) -> bool {
+                        const mpact::sim::riscv::Instruction* inst) -> bool {
     if (exception_code ==
         static_cast<uint64_t>(
             mpact::sim::riscv::ExceptionCode::kLoadAccessFault)) {
@@ -83,9 +83,9 @@
     }
     return false;
   });
-  auto *db = state->db_factory()->Allocate<uint32_t>(1);
+  auto* db = state->db_factory()->Allocate<uint32_t>(1);
   // Create a dummy instruction so trap can dereference the address.
-  auto *dummy_inst = new mpact::sim::riscv::Instruction(0x0, nullptr);
+  auto* dummy_inst = new mpact::sim::riscv::Instruction(0x0, nullptr);
   dummy_inst->set_size(4);
   testing::internal::CaptureStderr();
   state->LoadMemory(dummy_inst, kMemAddr, db, nullptr, nullptr);
diff --git a/riscv/test/riscv_top_test.cc b/riscv/test/riscv_top_test.cc
index 0176c02..7e0657f 100644
--- a/riscv/test/riscv_top_test.cc
+++ b/riscv/test/riscv_top_test.cc
@@ -69,8 +69,8 @@
 
 // Helper function to get symbol addresses from the loader.
 static bool GetMagicAddresses(
-    mpact::sim::util::ElfProgramLoader *loader,
-    mpact::sim::riscv::RiscV32HtifSemiHost::SemiHostAddresses *magic) {
+    mpact::sim::util::ElfProgramLoader* loader,
+    mpact::sim::riscv::RiscV32HtifSemiHost::SemiHostAddresses* magic) {
   auto result = loader->GetSymbol("tohost_ready");
   if (!result.ok()) return false;
   magic->tohost_ready = result.value().first;
@@ -93,8 +93,8 @@
 // Helper RAII style class for setting up HTIF semihosting.
 class HtifSemihostSetup {
  public:
-  HtifSemihostSetup(RiscVTop *top, mpact::sim::util::ElfProgramLoader *loader,
-                    mpact::sim::util::MemoryInterface *memory)
+  HtifSemihostSetup(RiscVTop* top, mpact::sim::util::ElfProgramLoader* loader,
+                    mpact::sim::util::MemoryInterface* memory)
       : memory_(memory), state_(top->state()) {
     mpact::sim::riscv::RiscV32HtifSemiHost::SemiHostAddresses magic;
     if (GetMagicAddresses(loader, &magic)) {
@@ -120,17 +120,17 @@
   }
 
  private:
-  mpact::sim::util::MemoryInterface *memory_ = nullptr;
-  mpact::sim::riscv::RiscVState *state_ = nullptr;
-  mpact::sim::util::MemoryWatcher *watcher_ = nullptr;
-  mpact::sim::riscv::RiscV32HtifSemiHost *semihost_ = nullptr;
+  mpact::sim::util::MemoryInterface* memory_ = nullptr;
+  mpact::sim::riscv::RiscVState* state_ = nullptr;
+  mpact::sim::util::MemoryWatcher* watcher_ = nullptr;
+  mpact::sim::riscv::RiscV32HtifSemiHost* semihost_ = nullptr;
 };
 
 // Helper RAII style class for setting up ARM semihosting.
 class ArmSemihostSetup {
  public:
-  explicit ArmSemihostSetup(RiscVTop *top,
-                            mpact::sim::util::MemoryInterface *memory) {
+  explicit ArmSemihostSetup(RiscVTop* top,
+                            mpact::sim::util::MemoryInterface* memory) {
     auto xlen = top->state()->xlen();
     if (xlen == RiscVXlen::RV64) {
       semihost_ = new RiscVArmSemihost(RiscVArmSemihost::BitWidth::kWord64,
@@ -141,7 +141,7 @@
     }
     auto semihost = semihost_;
     top->state()->AddEbreakHandler([semihost,
-                                    top](const Instruction *inst) -> bool {
+                                    top](const Instruction* inst) -> bool {
       if (semihost->IsSemihostingCall(inst)) {
         semihost->OnEBreak(inst);
       } else {
@@ -157,7 +157,7 @@
   ~ArmSemihostSetup() { delete semihost_; }
 
  private:
-  mpact::sim::riscv::RiscVArmSemihost *semihost_ = nullptr;
+  mpact::sim::riscv::RiscVArmSemihost* semihost_ = nullptr;
 };
 
 class RiscVTopTest : public testing::Test {
@@ -207,12 +207,12 @@
   }
 
   uint64_t entry_point_;
-  RiscVTop *riscv_top_ = nullptr;
-  mpact::sim::util::ElfProgramLoader *loader_ = nullptr;
-  FlatDemandMemory *memory_ = nullptr;
-  RiscVState *state_ = nullptr;
-  RiscVFPState *fp_state_ = nullptr;
-  DecoderInterface *decoder_ = nullptr;
+  RiscVTop* riscv_top_ = nullptr;
+  mpact::sim::util::ElfProgramLoader* loader_ = nullptr;
+  FlatDemandMemory* memory_ = nullptr;
+  RiscVState* state_ = nullptr;
+  RiscVFPState* fp_state_ = nullptr;
+  DecoderInterface* decoder_ = nullptr;
 };
 
 // Runs the program from beginning to end using HTIF semihosting.
@@ -460,7 +460,7 @@
   EXPECT_EQ(riscv_top_->WriteRegister("x32", word_value).code(),
             absl::StatusCode::kNotFound);
   // Aliases.
-  for (auto &[name, alias] : {std::tuple<std::string, std::string>{"x1", "ra"},
+  for (auto& [name, alias] : {std::tuple<std::string, std::string>{"x1", "ra"},
                               {"x4", "tp"},
                               {"x8", "s0"}}) {
     uint32_t write_value = 0xba5eba11;
diff --git a/riscv/test/riscv_vector_basic_bit_manipulation_test.cc b/riscv/test/riscv_vector_basic_bit_manipulation_test.cc
index 96f4843..e680097 100644
--- a/riscv/test/riscv_vector_basic_bit_manipulation_test.cc
+++ b/riscv/test/riscv_vector_basic_bit_manipulation_test.cc
@@ -51,7 +51,7 @@
 // Helper function for testing the vandn_vv instruction. Generate the expected
 // result using the bitwise operator.
 template <typename T>
-inline void VandnVVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VandnVVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vandn);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vandn", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -61,7 +61,7 @@
 // Helper function for testing the vandn_vx instruction. Generate the expected
 // result using the bitwise operator.
 template <typename T>
-inline void VandnVXHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VandnVXHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vandn);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vandn", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -71,7 +71,7 @@
 // Helper function for testing the vbrev_v instruction. Generate the expected
 // result by reversing the input bits.
 template <typename T>
-inline void VbrevVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VbrevVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vbrev);
   tester->UnaryOpTestHelperV<T, T>(absl::StrCat("Vbrev", sizeof(T) * 8, "v"),
                                    /*sew*/ sizeof(T) * 8, tester->instruction(),
@@ -88,7 +88,7 @@
 // Helper function for testing the vbrev8_v instruction. Generate the expected
 // result by reversing the bits in each of the input bytes.
 template <typename T>
-inline void Vbrev8VHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void Vbrev8VHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vbrev8);
   tester->UnaryOpTestHelperV<T, T>(
       absl::StrCat("Vbrev8", sizeof(T) * 8, "v"), /*sew*/ sizeof(T) * 8,
@@ -110,7 +110,7 @@
 // Helper function for testing the vbrev_v instruction. Generate the expected
 // result by reversing the bytes of the input.
 template <typename T>
-inline void Vrev8VHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void Vrev8VHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vrev8);
   tester->UnaryOpTestHelperV<T, T>(
       absl::StrCat("Vrev8", sizeof(T) * 8, "v"), /*sew*/ sizeof(T) * 8,
@@ -127,7 +127,7 @@
 // Helper function for testing the vrol_vv instruction. Generate the expected
 // result by rotating the input bits left.
 template <typename T>
-inline void VrolVVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VrolVVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vrol);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vrol", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -143,7 +143,7 @@
 // Helper function for testing the vrol_vx instruction. Generate the expected
 // result by rotating the input bits left.
 template <typename T>
-inline void VrolVXHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VrolVXHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vrol);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vrol", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -159,7 +159,7 @@
 // Helper function for testing the vror_vv instruction. Generate the expected
 // result by rotating the input bits right.
 template <typename T>
-inline void VrorVVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VrorVVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vror);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vror", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -175,7 +175,7 @@
 // Helper function for testing the vror_vx instruction. Generate the expected
 // result by rotating the input bits right.
 template <typename T>
-inline void VrorVXHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VrorVXHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vror);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vror", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -191,7 +191,7 @@
 // Helper function for testing the vror_vi instruction. Generate the expected
 // result by rotating the input bits right.
 template <typename T>
-inline void VrorVIHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VrorVIHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vror);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vror", sizeof(T) * 8, "vi"), /*sew*/ sizeof(T) * 8,
@@ -207,7 +207,7 @@
 // Helper function for testing the vclz_v instruction. Generate the expected
 // result by counting the number of leading zeros in the input.
 template <typename T>
-inline void VclzVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VclzVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vclz);
   tester->UnaryOpTestHelperV<T, T>(
       absl::StrCat("vclz", sizeof(T) * 8, "v"), /*sew*/ sizeof(T) * 8,
@@ -226,7 +226,7 @@
 // Helper function for testing the vctz_v instruction. Generate the expected
 // result by counting the number of trailing zeros in the input.
 template <typename T>
-inline void VctzVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VctzVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&Vctz);
   tester->UnaryOpTestHelperV<T, T>(absl::StrCat("vctz", sizeof(T) * 8, "v"),
                                    /*sew*/ sizeof(T) * 8, tester->instruction(),
@@ -245,7 +245,7 @@
 // Helper function for testing the vcpop_v instruction. Generate the expected
 // result by counting the number of bits set in the input.
 template <typename T>
-inline void VcpopVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VcpopVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   tester->SetSemanticFunction(&VectorVcpop);
   tester->UnaryOpTestHelperV<T, T>(absl::StrCat("vcpop", sizeof(T) * 8, "v"),
                                    /*sew*/ sizeof(T) * 8, tester->instruction(),
@@ -262,7 +262,7 @@
 // Helper function for testing the vwsll_vv instruction. Generate the expected
 // result by shifting the widened input left.
 template <typename T>
-inline void VwsllVVHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VwsllVVHelper(RiscVVectorBasicBitManipulationTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsll);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -277,7 +277,7 @@
 // Helper function for testing the vwsll_vx instruction. Generate the expected
 // result by shifting the widened input left.
 template <typename T>
-inline void VwsllVXHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VwsllVXHelper(RiscVVectorBasicBitManipulationTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsll);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -292,7 +292,7 @@
 // Helper function for testing the vwsll_vi instruction. Generate the expected
 // result by shifting the widened input left.
 template <typename T>
-inline void VwsllVIHelper(RiscVVectorBasicBitManipulationTest *tester) {
+inline void VwsllVIHelper(RiscVVectorBasicBitManipulationTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsll);
   tester->BinaryOpTestHelperVV<WT, T, T>(
diff --git a/riscv/test/riscv_vector_fp_compare_instructions_test.cc b/riscv/test/riscv_vector_fp_compare_instructions_test.cc
index 58de677..7681c59 100644
--- a/riscv/test/riscv_vector_fp_compare_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_compare_instructions_test.cc
@@ -71,7 +71,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskFPOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Vs1)) {
@@ -95,14 +95,14 @@
     // Overwrite the first few values of the input data with infinities,
     // zeros, denormals and NaNs.
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
     // Make every third value the same (at least if the types are same sized).
     for (int i = 0; i < std::min(vs1_size, vs2_size); i += 3) {
       vs1_span[i] = static_cast<Vs1>(vs2_span[i]);
@@ -172,10 +172,10 @@
               uint8_t expected_value =
                   operation(vs2_value[i], vs1_value[i], mask_value);
               auto int_vs2_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                       &vs2_value[i]);
               auto int_vs1_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                       &vs1_value[i]);
               EXPECT_EQ(expected_value, inst_value)
                   << absl::StrCat(name, "[", i, "] op(", vs2_value[i], "[0x",
@@ -197,7 +197,7 @@
   // not use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskFPOpTestHelperVV(absl::string_view name, int sew,
-                                  Instruction *inst,
+                                  Instruction* inst,
                                   std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskFPOpWithMaskTestHelperVV<Vs2, Vs1>(
         name, sew, inst,
@@ -213,7 +213,7 @@
   // use the mask bit.
   template <typename Vs2, typename Fs1>
   void BinaryMaskFPOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Fs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Fs1)) {
@@ -297,10 +297,10 @@
               uint8_t expected_value =
                   operation(vs2_value[i], fs1_value, mask_value);
               auto int_vs2_val =
-                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                       &vs2_value[i]);
               auto int_fs1_val =
-                  *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType *>(
+                  *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType*>(
                       &fs1_value);
               EXPECT_EQ(expected_value, inst_value)
                   << absl::StrCat(name, "[", i, "] op(", vs2_value[i], "[0x",
@@ -321,7 +321,7 @@
   // use the mask bit.
   template <typename Vs2, typename Fs1>
   void BinaryMaskFPOpTestHelperVX(absl::string_view name, int sew,
-                                  Instruction *inst,
+                                  Instruction* inst,
                                   std::function<uint8_t(Vs2, Fs1)> operation) {
     BinaryMaskFPOpWithMaskTestHelperVX<Vs2, Fs1>(
         name, sew, inst,
diff --git a/riscv/test/riscv_vector_fp_instructions_test.cc b/riscv/test/riscv_vector_fp_instructions_test.cc
index cf123c6..98d1673 100644
--- a/riscv/test/riscv_vector_fp_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_instructions_test.cc
@@ -102,7 +102,7 @@
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void TernaryOpFPTestHelperVV(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs2, Vs1, Vd)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -137,49 +137,49 @@
       using VdInt = typename FPTypeInfo<Vd>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
-      *reinterpret_cast<VdInt *>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
-      *reinterpret_cast<VdInt *>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
-      *reinterpret_cast<VdInt *>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
-      *reinterpret_cast<VdInt *>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
+      *reinterpret_cast<VdInt*>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
+      *reinterpret_cast<VdInt*>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
+      *reinterpret_cast<VdInt*>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
+      *reinterpret_cast<VdInt*>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
       if (lmul_index == 4) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
       } else if (lmul_index == 5) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
       } else if (lmul_index == 6) {
-        *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
-        *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
+        *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
       }
       // Modify the first mask bits to use each of the special floating point
       // values.
@@ -260,23 +260,23 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 auto int_vd_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &vd_value[count]);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val = operation(vs2_value[count], vs1_value[count],
                                           vd_value[count]);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                           &vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -312,7 +312,7 @@
   // scalar instructions.
   template <typename Vd, typename Vs2, typename Fs1>
   void TernaryOpFPTestHelperVX(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs2, Fs1, Vd)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -343,22 +343,22 @@
       using VdInt = typename FPTypeInfo<Vd>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
-      *reinterpret_cast<VdInt *>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
-      *reinterpret_cast<VdInt *>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
-      *reinterpret_cast<VdInt *>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
-      *reinterpret_cast<VdInt *>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
-      *reinterpret_cast<VdInt *>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
-      *reinterpret_cast<VdInt *>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[0]) = FPTypeInfo<Vd>::kQNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[1]) = FPTypeInfo<Vd>::kSNaN;
+      *reinterpret_cast<VdInt*>(&vd_span[2]) = FPTypeInfo<Vd>::kPosInf;
+      *reinterpret_cast<VdInt*>(&vd_span[3]) = FPTypeInfo<Vd>::kNegInf;
+      *reinterpret_cast<VdInt*>(&vd_span[4]) = FPTypeInfo<Vd>::kPosZero;
+      *reinterpret_cast<VdInt*>(&vd_span[5]) = FPTypeInfo<Vd>::kNegZero;
+      *reinterpret_cast<VdInt*>(&vd_span[6]) = FPTypeInfo<Vd>::kPosDenorm;
+      *reinterpret_cast<VdInt*>(&vd_span[7]) = FPTypeInfo<Vd>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -383,7 +383,7 @@
         // Try different vector lengths (updated at the bottom of the loop).
         for (int vlen_count = 0; vlen_count < 4; vlen_count++) {
           // Clear vd_span.
-          for (auto &vd_val : vd_span) vd_val = 0;
+          for (auto& vd_val : vd_span) vd_val = 0;
           ASSERT_TRUE(vlen > vstart);
           int num_values = std::min(num_reg_values, vlen);
           ConfigureVectorUnit(vtype, vlen);
@@ -448,10 +448,10 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 auto int_vd_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &vd_value[count]);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   // Set rounding mode and perform the computation.
@@ -461,13 +461,13 @@
                       operation(vs2_value[count], fs1_value, vd_value[count]);
                   // Extract the integer view of the fp values.
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_fs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Fs1>::IntType*>(
                           &fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -1116,10 +1116,10 @@
         sign_op) {
   using Int = typename FPTypeInfo<T>::IntType;
   Int sign_mask = 1ULL << (FPTypeInfo<T>::kBitSize - 1);
-  Int vs2i = *reinterpret_cast<Int *>(&vs2);
-  Int vs1i = *reinterpret_cast<Int *>(&vs1);
+  Int vs2i = *reinterpret_cast<Int*>(&vs2);
+  Int vs1i = *reinterpret_cast<Int*>(&vs1);
   Int resi = sign_op(vs2i, vs1i, sign_mask);
-  return *reinterpret_cast<T *>(&resi);
+  return *reinterpret_cast<T*>(&resi);
 }
 
 // The sign is that of vs1.
@@ -1260,7 +1260,7 @@
 template <typename T>
 bool is_snan(T value) {
   using IntType = typename FPTypeInfo<T>::IntType;
-  IntType int_value = *reinterpret_cast<IntType *>(&value);
+  IntType int_value = *reinterpret_cast<IntType*>(&value);
   bool signal = (int_value & (1ULL << (FPTypeInfo<T>::kSigSize - 1))) == 0;
   return std::isnan(value) && signal;
 }
@@ -1275,7 +1275,7 @@
   if (std::isnan(vs2) && std::isnan(vs1)) {
     // Canonical NaN.
     auto canonical = FPTypeInfo<T>::kCanonicalNaN;
-    T canonical_fp = *reinterpret_cast<T *>(&canonical);
+    T canonical_fp = *reinterpret_cast<T*>(&canonical);
     return std::tie(canonical_fp, flag);
   }
   if (std::isnan(vs2)) return std::tie(vs1, flag);
diff --git a/riscv/test/riscv_vector_fp_reduction_instructions_test.cc b/riscv/test/riscv_vector_fp_reduction_instructions_test.cc
index d0fec04..bd7535e 100644
--- a/riscv/test/riscv_vector_fp_reduction_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_reduction_instructions_test.cc
@@ -15,21 +15,20 @@
 #include "riscv/riscv_vector_fp_reduction_instructions.h"
 
 #include <algorithm>
-#include <cstring>
-#include <ios>
-#include <limits>
-#include <string>
-#include <type_traits>
+#include <cstdint>
+#include <functional>
 #include <vector>
 
 #include "absl/random/random.h"
+#include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
 #include "absl/types/span.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/instruction.h"
+#include "riscv/riscv_fp_host.h"
+#include "riscv/riscv_fp_info.h"
 #include "riscv/riscv_fp_state.h"
 #include "riscv/riscv_register.h"
-#include "riscv/riscv_vector_state.h"
 #include "riscv/test/riscv_vector_fp_test_utilities.h"
 #include "riscv/test/riscv_vector_instructions_test_base.h"
 
@@ -69,7 +68,7 @@
   // Helper function for floating point reduction operations.
   template <typename Vd, typename Vs2, typename Vs1>
   void ReductionOpFPTestHelper(absl::string_view name, int sew,
-                               Instruction *inst, int delta_position,
+                               Instruction* inst, int delta_position,
                                std::function<Vd(Vs1, Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -195,8 +194,8 @@
 template <typename T>
 T MaxMinHelper(T vs2, T vs1, std::function<T(T, T)> operation) {
   using UInt = typename FPTypeInfo<T>::IntType;
-  UInt vs2_uint = *reinterpret_cast<UInt *>(&vs2);
-  UInt vs1_uint = *reinterpret_cast<UInt *>(&vs1);
+  UInt vs2_uint = *reinterpret_cast<UInt*>(&vs2);
+  UInt vs1_uint = *reinterpret_cast<UInt*>(&vs1);
   UInt mask = 1ULL << (FPTypeInfo<T>::kSigSize - 1);
   bool nan_vs2 = std::isnan(vs2);
   bool nan_vs1 = std::isnan(vs1);
@@ -205,7 +204,7 @@
     // Canonical NaN.
     UInt canonical = ((1ULL << (FPTypeInfo<T>::kExpSize + 1)) - 1)
                      << (FPTypeInfo<T>::kSigSize - 1);
-    T canonical_fp = *reinterpret_cast<T *>(&canonical);
+    T canonical_fp = *reinterpret_cast<T*>(&canonical);
     return canonical_fp;
   }
   if (nan_vs2) return vs1;
diff --git a/riscv/test/riscv_vector_fp_test_utilities.h b/riscv/test/riscv_vector_fp_test_utilities.h
index 9ed5ff4..b291c94 100644
--- a/riscv/test/riscv_vector_fp_test_utilities.h
+++ b/riscv/test/riscv_vector_fp_test_utilities.h
@@ -120,12 +120,12 @@
     if (exp > delta_position) {
       exp -= delta_position;
       UInt udelta = exp << FPTypeInfo<T>::kSigSize;
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     } else {
       // Becomes a denormal
       int diff = delta_position - exp;
       UInt udelta = 1ULL << (FPTypeInfo<T>::kSigSize - 1 - diff);
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     }
     EXPECT_THAT(reg, testing::NanSensitiveFloatNear(op, delta)) << str;
   } else {
@@ -145,12 +145,12 @@
     if (exp > delta_position) {
       exp -= delta_position;
       UInt udelta = exp << FPTypeInfo<T>::kSigSize;
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     } else {
       // Becomes a denormal
       int diff = delta_position - exp;
       UInt udelta = 1ULL << (FPTypeInfo<T>::kSigSize - 1 - diff);
-      delta = *reinterpret_cast<T *>(&udelta);
+      delta = *reinterpret_cast<T*>(&udelta);
     }
     EXPECT_THAT(reg, testing::NanSensitiveDoubleNear(op, delta)) << str;
   } else {
@@ -179,7 +179,7 @@
 struct GreaterSize {
   static const bool value =
       sizeof(S) > sizeof(D) &&
-      std::is_floating_point<S>::value &&std::is_integral<D>::value;
+      std::is_floating_point<S>::value&& std::is_integral<D>::value;
 };
 
 template <typename S, typename D>
@@ -204,16 +204,16 @@
 inline typename std::enable_if<internal::LessSize<S, D>::value, D>::type NaNBox(
     S value) {
   using SInt = typename FPTypeInfo<S>::IntType;
-  SInt sval = *reinterpret_cast<SInt *>(&value);
+  SInt sval = *reinterpret_cast<SInt*>(&value);
   D dval = (~static_cast<D>(0) << (sizeof(S) * 8)) | sval;
-  return *reinterpret_cast<D *>(&dval);
+  return *reinterpret_cast<D*>(&dval);
 }
 
 // This version does a straight copy - as the data types are the same size.
 template <typename S, typename D>
 inline typename std::enable_if<internal::EqualSize<S, D>::value, D>::type
 NaNBox(S value) {
-  return *reinterpret_cast<D *>(&value);
+  return *reinterpret_cast<D*>(&value);
 }
 
 // Signal error if the register is smaller than the floating point value.
@@ -248,14 +248,14 @@
                              1ULL << FPTypeInfo<T>::kSigSize);
     UInt value = (sign & 1) << (FPTypeInfo<T>::kBitSize - 1) |
                  (exp << FPTypeInfo<T>::kSigSize) | sig;
-    T val = *reinterpret_cast<T *>(&value);
+    T val = *reinterpret_cast<T*>(&value);
     return val;
   }
 
   // This method uses random values for each field in the fp number.
   template <typename T>
   void FillArrayWithRandomFPValues(absl::Span<T> span) {
-    for (auto &val : span) {
+    for (auto& val : span) {
       val = RandomFPValue<T>();
     }
   }
@@ -270,41 +270,41 @@
     using Vs1Int = typename FPTypeInfo<Vs1>::IntType;
     // Overwrite the first few values of the input data with infinities,
     // zeros, denormals and NaNs.
-    *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-    *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+    *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
     if (count == 4) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kNegDenorm;
     } else if (count == 5) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kNegDenorm;
     } else if (count == 6) {
-      *reinterpret_cast<Vs1Int *>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
-      *reinterpret_cast<Vs1Int *>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[0]) = FPTypeInfo<Vs1>::kQNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[1]) = FPTypeInfo<Vs1>::kSNaN;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[2]) = FPTypeInfo<Vs1>::kNegInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[3]) = FPTypeInfo<Vs1>::kPosInf;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[4]) = FPTypeInfo<Vs1>::kNegZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[5]) = FPTypeInfo<Vs1>::kPosZero;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[6]) = FPTypeInfo<Vs1>::kNegDenorm;
+      *reinterpret_cast<Vs1Int*>(&vs1_span[7]) = FPTypeInfo<Vs1>::kPosDenorm;
     }
     // Modify the first mask bits to use each of the special floating
     // point values.
@@ -315,7 +315,7 @@
   // NaN etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpFPTestHelperVV(absl::string_view name, int sew,
-                              Instruction *inst, int delta_position,
+                              Instruction* inst, int delta_position,
                               std::function<Vd(Vs2, Vs1)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -410,19 +410,19 @@
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
                 auto int_reg_val =
-                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                    *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                         &reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val = operation(vs2_value[count], vs1_value[count]);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs1>::IntType*>(
                           &vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -456,7 +456,7 @@
   // NaN etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpWithFflagsFPTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2, Vs1)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -478,7 +478,7 @@
     auto vs2_span = Span<Vs2>(vs2_value);
     auto vs1_span = Span<Vs1>(vs1_value);
     AppendVectorRegisterOperands({kVs2, kVs1, kVmask}, {kVd});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});
@@ -558,7 +558,7 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   Vd op_val;
                   uint32_t flag;
@@ -569,11 +569,11 @@
                     op_val = op_val_tmp;
                     flag = flag_tmp;
                   }
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
                   auto int_vs1_val =
-                      *reinterpret_cast<Vs1Int *>(&vs1_value[count]);
+                      *reinterpret_cast<Vs1Int*>(&vs1_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -609,7 +609,7 @@
   // NaN etc.) during testing, not just random values.
   template <typename Vd, typename Vs2, typename Fs1, typename ScalarReg>
   void BinaryOpWithFflagsFPTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2, Fs1)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -629,7 +629,7 @@
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {kVd});
     AppendRegisterOperands<ScalarReg>({kFs1Name}, {});
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     AppendVectorRegisterOperands({kVmask}, {});
     SetVectorRegisterValues<uint8_t>(
@@ -640,14 +640,14 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating
       // point values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -728,7 +728,7 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && mask_value && (count < num_values)) {
                   Vd op_val;
                   uint32_t flag;
@@ -739,10 +739,10 @@
                     op_val = op_val_tmp;
                     flag = flag_tmp;
                   }
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
-                  auto int_fs1_val = *reinterpret_cast<Fs1Int *>(&fs1_value);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
+                  auto int_fs1_val = *reinterpret_cast<Fs1Int*>(&fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -778,7 +778,7 @@
   // vector scalar instructions.
   template <typename Vd, typename Vs2, typename Fs1, typename ScalarReg>
   void BinaryOpFPWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<Vd(Vs2, Fs1, bool)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -807,14 +807,14 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
       // Modify the first mask bits to use each of the special floating
       // point values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -892,15 +892,15 @@
                       ((kA5Mask[mask_index] >> mask_offset) & 0b1) != 0;
                 }
                 auto reg_val = vreg_[reg]->data_buffer()->Get<Vd>(i);
-                auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
+                auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
                 if ((count >= vstart) && (count < num_values)) {
                   ScopedFPStatus set_fpstatus(rv_fp_->host_fp_interface());
                   auto op_val =
                       operation(vs2_value[count], fs1_value, mask_value);
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
-                  auto int_fs1_val = *reinterpret_cast<Fs1Int *>(&fs1_value);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
+                  auto int_fs1_val = *reinterpret_cast<Fs1Int*>(&fs1_value);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -932,7 +932,7 @@
   // not use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1, typename ScalarReg>
   void BinaryOpFPTestHelperVX(absl::string_view name, int sew,
-                              Instruction *inst, int delta_position,
+                              Instruction* inst, int delta_position,
                               std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpFPWithMaskTestHelperVX<Vd, Vs2, Vs1, ScalarReg>(
         name, sew, inst, delta_position,
@@ -945,7 +945,7 @@
   }
 
  protected:
-  mpact::sim::riscv::RiscVFPState *rv_fp_;
+  mpact::sim::riscv::RiscVFPState* rv_fp_;
 };
 
 }  // namespace test
diff --git a/riscv/test/riscv_vector_fp_unary_instructions_test.cc b/riscv/test/riscv_vector_fp_unary_instructions_test.cc
index e3ee470..1c5b142 100644
--- a/riscv/test/riscv_vector_fp_unary_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_unary_instructions_test.cc
@@ -116,7 +116,7 @@
   template <typename T>
   void FillArrayWithRandomFPValues(absl::Span<T> span) {
     using UInt = typename FPTypeInfo<T>::IntType;
-    for (auto &val : span) {
+    for (auto& val : span) {
       UInt sign = absl::Uniform(absl::IntervalClosed, bitgen_, 0ULL, 1ULL);
       UInt exp = absl::Uniform(absl::IntervalClosedOpen, bitgen_, 0ULL,
                                1ULL << FPTypeInfo<T>::kExpSize);
@@ -124,14 +124,14 @@
                                1ULL << FPTypeInfo<T>::kSigSize);
       UInt value = (sign & 1) << (FPTypeInfo<T>::kBitSize - 1) |
                    (exp << FPTypeInfo<T>::kSigSize) | sig;
-      val = *reinterpret_cast<T *>(&value);
+      val = *reinterpret_cast<T*>(&value);
     }
   }
 
   // Floating point test needs to ensure to use the fp special values (inf, NaN
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2>
-  void UnaryOpFPTestHelperV(absl::string_view name, int sew, Instruction *inst,
+  void UnaryOpFPTestHelperV(absl::string_view name, int sew, Instruction* inst,
                             int delta_position,
                             std::function<Vd(Vs2)> operation) {
     int byte_sew = sew / 8;
@@ -156,17 +156,17 @@
       using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[8]) = 0x0119515e;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[9]) = 0x0007fea3;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[10]) = 0x800bc58f;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[8]) = 0x0119515e;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[9]) = 0x0007fea3;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[10]) = 0x800bc58f;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -233,13 +233,13 @@
                   auto op_val = operation(vs2_value[count]);
                   // Do separate comparison if the result is a NaN.
                   auto int_reg_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &reg_val);
                   auto int_op_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vd>::IntType*>(
                           &op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType *>(
+                      *reinterpret_cast<typename FPTypeInfo<Vs2>::IntType*>(
                           &vs2_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
@@ -273,7 +273,7 @@
   // etc.) during testing, not just random values.
   template <typename Vd, typename Vs2>
   void UnaryOpWithFflagsFPTestHelperV(
-      absl::string_view name, int sew, Instruction *inst, int delta_position,
+      absl::string_view name, int sew, Instruction* inst, int delta_position,
       std::function<std::tuple<Vd, uint32_t>(Vs2)> operation) {
     using VdInt = typename FPTypeInfo<Vd>::IntType;
     using Vs2Int = typename FPTypeInfo<Vs2>::IntType;
@@ -290,7 +290,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2, kVmask}, {kVd});
-    auto *op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(op);
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});
@@ -300,17 +300,17 @@
       FillArrayWithRandomFPValues<Vs2>(vs2_span);
       // Overwrite the first few values of the input data with infinities,
       // zeros, denormals and NaNs.
-      *reinterpret_cast<Vs2Int *>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[8]) = 0x0119515e;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[9]) = 0x0007fea3;
-      *reinterpret_cast<Vs2Int *>(&vs2_span[10]) = 0x800bc58f;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[0]) = FPTypeInfo<Vs2>::kQNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[1]) = FPTypeInfo<Vs2>::kSNaN;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[2]) = FPTypeInfo<Vs2>::kPosInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[3]) = FPTypeInfo<Vs2>::kNegInf;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[4]) = FPTypeInfo<Vs2>::kPosZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[5]) = FPTypeInfo<Vs2>::kNegZero;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[6]) = FPTypeInfo<Vs2>::kPosDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[7]) = FPTypeInfo<Vs2>::kNegDenorm;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[8]) = 0x0119515e;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[9]) = 0x0007fea3;
+      *reinterpret_cast<Vs2Int*>(&vs2_span[10]) = 0x800bc58f;
       // Modify the first mask bits to use each of the special floating point
       // values.
       vreg_[kVmask]->data_buffer()->Set<uint8_t>(0, 0xff);
@@ -393,10 +393,10 @@
                   }
                   fflags_test |= (rv_fp_->fflags()->AsUint32() | flag);
                   // Do separate comparison if the result is a NaN.
-                  auto int_reg_val = *reinterpret_cast<VdInt *>(&reg_val);
-                  auto int_op_val = *reinterpret_cast<VdInt *>(&op_val);
+                  auto int_reg_val = *reinterpret_cast<VdInt*>(&reg_val);
+                  auto int_op_val = *reinterpret_cast<VdInt*>(&op_val);
                   auto int_vs2_val =
-                      *reinterpret_cast<Vs2Int *>(&vs2_value[count]);
+                      *reinterpret_cast<Vs2Int*>(&vs2_value[count]);
                   FPCompare<Vd>(
                       op_val, reg_val, delta_position,
                       absl::StrCat(name, "[", count, "] op(", vs2_value[count],
@@ -427,8 +427,8 @@
   }
 
  protected:
-  mpact::sim::riscv::RiscVFPState *rv_fp_ = nullptr;
-  RiscVCsrInterface *fflags_ = nullptr;
+  mpact::sim::riscv::RiscVFPState* rv_fp_ = nullptr;
+  RiscVCsrInterface* fflags_ = nullptr;
 };
 
 // Templated helper function for classifying fp numbers.
@@ -439,8 +439,7 @@
     case FP_INFINITE:
       return std::signbit(val) ? 1 : 1 << 7;
     case FP_NAN: {
-      auto uint_val =
-          *reinterpret_cast<typename FPTypeInfo<T>::IntType *>(&val);
+      auto uint_val = *reinterpret_cast<typename FPTypeInfo<T>::IntType*>(&val);
       bool quiet_nan = (uint_val >> (FPTypeInfo<T>::kSigSize - 1)) & 1;
       return quiet_nan ? 1 << 9 : 1 << 8;
     }
@@ -495,7 +494,7 @@
 
 // Helper function for fp to integer conversions.
 template <typename F, typename I>
-std::tuple<I, uint32_t> ConvertHelper(F value, RiscVFPState *fp_state) {
+std::tuple<I, uint32_t> ConvertHelper(F value, RiscVFPState* fp_state) {
   constexpr F kMin = static_cast<F>(std::numeric_limits<I>::min());
   constexpr F kMax = static_cast<F>(std::numeric_limits<I>::max());
   ScopedFPStatus status(fp_state->host_fp_interface());
@@ -715,15 +714,15 @@
         }
         using UIntD = typename FPTypeInfo<double>::IntType;
         using UIntF = typename FPTypeInfo<float>::IntType;
-        UIntD uval = *reinterpret_cast<UIntD *>(&vs2);
+        UIntD uval = *reinterpret_cast<UIntD*>(&vs2);
         int diff = FPTypeInfo<double>::kSigSize - FPTypeInfo<float>::kSigSize;
         UIntF bit = (uval & (FPTypeInfo<double>::kSigMask >> diff)) != 0;
         float res = static_cast<float>(vs2);
         // The narrowing conversion may have generated an infinity, so check
         // for infinity before doing rounding.
         if (std::isinf(res)) return res;
-        UIntF ures = *reinterpret_cast<UIntF *>(&res) | bit;
-        return *reinterpret_cast<float *>(&ures);
+        UIntF ures = *reinterpret_cast<UIntF*>(&res) | bit;
+        return *reinterpret_cast<float*>(&ures);
       });
 }
 
@@ -801,11 +800,11 @@
 
 // Helper function for testing approximate reciprocal instruction.
 template <typename T>
-inline T Vrecip7vTestHelper(T vs2, RiscVFPState *rv_fp) {
+inline T Vrecip7vTestHelper(T vs2, RiscVFPState* rv_fp) {
   using UInt = typename FPTypeInfo<T>::IntType;
   if (FPTypeInfo<T>::IsNaN(vs2)) {
     auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-    return *reinterpret_cast<T *>(&nan_value);
+    return *reinterpret_cast<T*>(&nan_value);
   }
   if (std::isinf(vs2)) {
     return std::signbit(vs2) ? -0.0 : 0.0;
@@ -813,9 +812,9 @@
   if (vs2 == 0.0) {
     UInt value =
         std::signbit(vs2) ? FPTypeInfo<T>::kNegInf : FPTypeInfo<T>::kPosInf;
-    return *reinterpret_cast<T *>(&value);
+    return *reinterpret_cast<T*>(&value);
   }
-  UInt uint_vs2 = *reinterpret_cast<UInt *>(&vs2);
+  UInt uint_vs2 = *reinterpret_cast<UInt*>(&vs2);
   auto exp = (uint_vs2 & FPTypeInfo<T>::kExpMask) >> FPTypeInfo<T>::kSigSize;
   auto sig2 =
       (uint_vs2 & FPTypeInfo<T>::kSigMask) >> (FPTypeInfo<T>::kSigSize - 2);
@@ -827,7 +826,7 @@
         return std::numeric_limits<T>::lowest();
       } else {
         UInt value = FPTypeInfo<T>::kNegInf;
-        return *reinterpret_cast<T *>(&value);
+        return *reinterpret_cast<T*>(&value);
       }
     } else {
       if ((rm == FPRoundingMode::kRoundTowardsZero) ||
@@ -835,17 +834,17 @@
         return std::numeric_limits<T>::max();
       } else {
         UInt value = FPTypeInfo<T>::kPosInf;
-        return *reinterpret_cast<T *>(&value);
+        return *reinterpret_cast<T*>(&value);
       }
     }
   }
   ScopedFPStatus status(rv_fp->host_fp_interface(),
                         FPRoundingMode::kRoundTowardsZero);
   T value = 1.0 / vs2;
-  UInt uint_val = *reinterpret_cast<UInt *>(&value);
+  UInt uint_val = *reinterpret_cast<UInt*>(&value);
   UInt mask = FPTypeInfo<T>::kSigMask >> 7;
   uint_val = uint_val & ~mask;
-  return *reinterpret_cast<T *>(&uint_val);
+  return *reinterpret_cast<T*>(&uint_val);
 }
 
 // Test approximate reciprocal instruction.
@@ -860,18 +859,18 @@
 
 // Helper function for testing approximate reciprocal square root instruction.
 template <typename T>
-inline std::tuple<T, uint32_t> Vfrsqrt7vTestHelper(T vs2, RiscVFPState *rv_fp) {
+inline std::tuple<T, uint32_t> Vfrsqrt7vTestHelper(T vs2, RiscVFPState* rv_fp) {
   using UInt = typename FPTypeInfo<T>::IntType;
   T return_value;
   uint32_t fflags = 0;
   if (FPTypeInfo<T>::IsNaN(vs2) || (vs2 < 0.0)) {
     auto nan_value = FPTypeInfo<T>::kCanonicalNaN;
-    return_value = *reinterpret_cast<T *>(&nan_value);
+    return_value = *reinterpret_cast<T*>(&nan_value);
     fflags = static_cast<uint32_t>(FPExceptions::kInvalidOp);
   } else if (vs2 == 0.0) {
     UInt value =
         std::signbit(vs2) ? FPTypeInfo<T>::kNegInf : FPTypeInfo<T>::kPosInf;
-    return_value = *reinterpret_cast<T *>(&value);
+    return_value = *reinterpret_cast<T*>(&value);
     fflags = static_cast<uint32_t>(FPExceptions::kDivByZero);
   } else if (std::isinf(vs2)) {
     return_value = 0.0;
@@ -880,10 +879,10 @@
     ScopedFPStatus status(rv_fp->host_fp_interface(),
                           FPRoundingMode::kRoundTowardsZero);
     T value = 1.0 / sqrt(vs2);
-    UInt uint_val = *reinterpret_cast<UInt *>(&value);
+    UInt uint_val = *reinterpret_cast<UInt*>(&value);
     UInt mask = FPTypeInfo<T>::kSigMask >> 7;
     uint_val = uint_val & ~mask;
-    return_value = *reinterpret_cast<T *>(&uint_val);
+    return_value = *reinterpret_cast<T*>(&uint_val);
   }
   return std::make_tuple(return_value, fflags);
 }
@@ -911,7 +910,7 @@
   if (vs2 == 0.0) return std::make_tuple(vs2, 0);
   if (std::isnan(vs2) || (vs2 < 0.0)) {
     auto val = FPTypeInfo<T>::kCanonicalNaN;
-    return std::make_tuple(*reinterpret_cast<const T *>(&val),
+    return std::make_tuple(*reinterpret_cast<const T*>(&val),
                            (uint32_t)FPExceptions::kInvalidOp);
   }
   T res = sqrt(vs2);
diff --git a/riscv/test/riscv_vector_instructions_test_base.h b/riscv/test/riscv_vector_instructions_test_base.h
index bc0892a..ca6bd7f 100644
--- a/riscv/test/riscv_vector_instructions_test_base.h
+++ b/riscv/test/riscv_vector_instructions_test_base.h
@@ -126,7 +126,7 @@
     child_instruction_ = new Instruction(kInstAddress, state_);
     child_instruction_->set_size(4);
     // Initialize a portion of memory with a known pattern.
-    auto *db = state_->db_factory()->Allocate(8192);
+    auto* db = state_->db_factory()->Allocate(8192);
     auto span = db->Get<uint8_t>();
     for (int i = 0; i < 8192; i++) {
       span[i] = i & 0xff;
@@ -163,10 +163,10 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the given instruction.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -174,22 +174,22 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the default instruction.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     AppendImmediateOperands<T>(instruction_, values);
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
   template <typename T>
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<T>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
@@ -197,25 +197,25 @@
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
   template <typename T>
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands<T>(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetRegisterValue(absl::string_view vreg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(vreg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(vreg_name).first;
     return reg->data_buffer()->Get<T>();
   }
 
   // named register and sets it to the corresponding value.
   template <typename T, typename RegisterType = RV32Register>
   void SetRegisterValues(
-      const std::vector<tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RegisterType>(reg_name).first;
-      auto *db =
+      const std::vector<tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RegisterType>(reg_name).first;
+      auto* db =
           state_->db_factory()->Allocate<typename RegisterType::ValueType>(1);
       db->template Set<T>(0, value);
       reg->SetDataBuffer(db);
@@ -225,43 +225,43 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendVectorRegisterOperands(Instruction *inst,
-                                    const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
-    for (auto &reg_no : sources) {
-      std::vector<RegisterBase *> reg_vec;
+  void AppendVectorRegisterOperands(Instruction* inst,
+                                    const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
+    for (auto& reg_no : sources) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorSourceOperand(
-          absl::Span<RegisterBase *>(reg_vec), absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorSourceOperand(absl::Span<RegisterBase*>(reg_vec),
+                                             absl::StrCat("v", reg_no));
       inst->AppendSource(op);
     }
-    for (auto &reg_no : destinations) {
-      std::vector<RegisterBase *> reg_vec;
+    for (auto& reg_no : destinations) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorDestinationOperand(
-          absl::Span<RegisterBase *>(reg_vec), 0, absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorDestinationOperand(
+          absl::Span<RegisterBase*>(reg_vec), 0, absl::StrCat("v", reg_no));
       inst->AppendDestination(op);
     }
   }
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendVectorRegisterOperands(const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
+  void AppendVectorRegisterOperands(const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
     AppendVectorRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetVectorRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -270,10 +270,10 @@
   // value.
   template <typename T>
   void SetVectorRegisterValues(
-      const std::vector<tuple<std::string, Span<const T>>> &values) {
-    for (auto &[vreg_name, span] : values) {
-      auto *vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
-      auto *db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
+      const std::vector<tuple<std::string, Span<const T>>>& values) {
+    for (auto& [vreg_name, span] : values) {
+      auto* vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
+      auto* db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
       db->template Set<T>(span);
       vreg->SetDataBuffer(db);
       db->DecRef();
@@ -281,7 +281,7 @@
   }
 
   // Initializes the semantic function of the instruction object.
-  void SetSemanticFunction(Instruction *inst,
+  void SetSemanticFunction(Instruction* inst,
                            Instruction::SemanticFunction fcn) {
     inst->set_semantic_function(fcn);
   }
@@ -301,7 +301,7 @@
 
   // Configure the vector unit according to the vtype and vlen values.
   void ConfigureVectorUnit(uint32_t vtype, uint32_t vlen) {
-    Instruction *inst = new Instruction(state_);
+    Instruction* inst = new Instruction(state_);
     AppendImmediateOperands<uint32_t>(inst, {vlen, vtype});
     SetSemanticFunction(inst, absl::bind_front(&Vsetvl, true, false));
     inst->Execute(nullptr);
@@ -326,14 +326,14 @@
   // Fill the span with random values.
   template <typename T>
   void FillArrayWithRandomValues(absl::Span<T> span) {
-    for (auto &val : span) {
+    for (auto& val : span) {
       val = RandomValue<T>();
     }
   }
 
   // Helper function for testing unary vector-vector instructions.
   template <typename Vd, typename Vs2>
-  void UnaryOpTestHelperV(absl::string_view name, int sew, Instruction *inst,
+  void UnaryOpTestHelperV(absl::string_view name, int sew, Instruction* inst,
                           std::function<Vd(Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2)) {
@@ -428,7 +428,7 @@
   // of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
   void BinaryOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -535,7 +535,7 @@
   // Helper function for testing vector-vector instructions that do not
   // use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
-  void BinaryOpTestHelperVV(absl::string_view name, int sew, Instruction *inst,
+  void BinaryOpTestHelperVV(absl::string_view name, int sew, Instruction* inst,
                             std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpWithMaskTestHelperVV<Vd, Vs2, Vs1>(
         name, sew, inst, [operation](Vs2 vs2, Vs1 vs1, bool mask_value) -> Vd {
@@ -550,7 +550,7 @@
   // the value of the mask bit.
   template <typename Vd, typename Vs2, typename Rs1, typename ScalarReg>
   void BinaryOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Rs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -664,7 +664,7 @@
   // Templated helper function that tests vector-scalar instructions that do
   // not use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1, typename ScalarReg>
-  void BinaryOpTestHelperVX(absl::string_view name, int sew, Instruction *inst,
+  void BinaryOpTestHelperVX(absl::string_view name, int sew, Instruction* inst,
                             std::function<Vd(Vs2, Vs1)> operation) {
     BinaryOpWithMaskTestHelperVX<Vd, Vs2, Vs1, ScalarReg>(
         name, sew, inst, [operation](Vs2 vs2, Vs1 vs1, bool mask_value) -> Vd {
@@ -679,7 +679,7 @@
   // of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
   void TernaryOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Vs1, Vd, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -800,7 +800,7 @@
   // Helper function for testing vector-vector instructions that do not
   // use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Vs1>
-  void TernaryOpTestHelperVV(absl::string_view name, int sew, Instruction *inst,
+  void TernaryOpTestHelperVV(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vs2, Vs1, Vd)> operation) {
     TernaryOpWithMaskTestHelperVV<Vd, Vs2, Vs1>(
         name, sew, inst,
@@ -816,7 +816,7 @@
   // the value of the mask bit.
   template <typename Vd, typename Vs2, typename Rs1, typename ScalarReg>
   void TernaryOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<Vd(Vs2, Rs1, Vd, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2) &&
@@ -946,7 +946,7 @@
   // Templated helper function that tests vector-scalar instructions that do
   // not use the value of the mask bit.
   template <typename Vd, typename Vs2, typename Rs1, typename ScalarReg>
-  void TernaryOpTestHelperVX(absl::string_view name, int sew, Instruction *inst,
+  void TernaryOpTestHelperVX(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vs2, Rs1, Vd)> operation) {
     TernaryOpWithMaskTestHelperVX<Vd, Vs2, Rs1, ScalarReg>(
         name, sew, inst,
@@ -962,7 +962,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskOpWithMaskTestHelperVV(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Vs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Vs1)) {
@@ -1061,7 +1061,7 @@
   // not use the mask bit.
   template <typename Vs2, typename Vs1>
   void BinaryMaskOpTestHelperVV(absl::string_view name, int sew,
-                                Instruction *inst,
+                                Instruction* inst,
                                 std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskOpWithMaskTestHelperVV<Vs2, Vs1>(
         name, sew, inst,
@@ -1077,7 +1077,7 @@
   // use the mask bit.
   template <typename Vs2, typename Rs1, typename ScalarReg>
   void BinaryMaskOpWithMaskTestHelperVX(
-      absl::string_view name, int sew, Instruction *inst,
+      absl::string_view name, int sew, Instruction* inst,
       std::function<uint8_t(Vs2, Rs1, bool)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vs2) && byte_sew != sizeof(Rs1)) {
@@ -1174,7 +1174,7 @@
   // use the mask bit.
   template <typename Vs2, typename Vs1, typename ScalarReg>
   void BinaryMaskOpTestHelperVX(absl::string_view name, int sew,
-                                Instruction *inst,
+                                Instruction* inst,
                                 std::function<uint8_t(Vs2, Vs1)> operation) {
     BinaryMaskOpWithMaskTestHelperVX<Vs2, Vs1, ScalarReg>(
         name, sew, inst,
@@ -1215,25 +1215,23 @@
     }
   }
 
-  RiscVVectorState *rv_vector() const { return rv_vector_; }
-  absl::Span<RVVectorRegister *> vreg() {
-    return absl::Span<RVVectorRegister *>(vreg_);
+  RiscVVectorState* rv_vector() const { return rv_vector_; }
+  absl::Span<RVVectorRegister*> vreg() {
+    return absl::Span<RVVectorRegister*>(vreg_);
   }
-  absl::Span<RV32Register *> xreg() {
-    return absl::Span<RV32Register *>(xreg_);
-  }
-  absl::BitGen &bitgen() { return bitgen_; }
-  Instruction *instruction() { return instruction_; }
+  absl::Span<RV32Register*> xreg() { return absl::Span<RV32Register*>(xreg_); }
+  absl::BitGen& bitgen() { return bitgen_; }
+  Instruction* instruction() { return instruction_; }
 
  protected:
-  RV32Register *xreg_[32];
-  RVVectorRegister *vreg_[32];
-  RVFpRegister *freg_[32];
-  RiscVState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
-  FlatDemandMemory *memory_;
-  RiscVVectorState *rv_vector_;
+  RV32Register* xreg_[32];
+  RVVectorRegister* vreg_[32];
+  RVFpRegister* freg_[32];
+  RiscVState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
+  FlatDemandMemory* memory_;
+  RiscVVectorState* rv_vector_;
   absl::BitGen bitgen_;
 };
 
diff --git a/riscv/test/riscv_vector_memory_instructions_test.cc b/riscv/test/riscv_vector_memory_instructions_test.cc
index 3eb40b0..eedd296 100644
--- a/riscv/test/riscv_vector_memory_instructions_test.cc
+++ b/riscv/test/riscv_vector_memory_instructions_test.cc
@@ -124,7 +124,7 @@
     child_instruction_ = new Instruction(kInstAddress, state_);
     child_instruction_->set_size(4);
     // Initialize a portion of memory with a known pattern.
-    auto *db = state_->db_factory()->Allocate(8192);
+    auto* db = state_->db_factory()->Allocate(8192);
     auto span = db->Get<uint8_t>();
     for (int i = 0; i < 8192; i++) {
       span[i] = i & 0xff;
@@ -151,10 +151,10 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the given instruction.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -162,46 +162,46 @@
   // Creates immediate operands with the values from the vector and appends them
   // to the default instruction.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     AppendImmediateOperands<T>(instruction_, values);
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetRegisterValue(absl::string_view vreg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(vreg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(vreg_name).first;
     return reg->data_buffer()->Get<T>();
   }
 
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(
-      const std::vector<tuple<std::string, const T>> &values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
+      const std::vector<tuple<std::string, const T>>& values) {
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -210,43 +210,43 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
-  void AppendVectorRegisterOperands(Instruction *inst,
-                                    const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
-    for (auto &reg_no : sources) {
-      std::vector<RegisterBase *> reg_vec;
+  void AppendVectorRegisterOperands(Instruction* inst,
+                                    const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
+    for (auto& reg_no : sources) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorSourceOperand(
-          absl::Span<RegisterBase *>(reg_vec), absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorSourceOperand(absl::Span<RegisterBase*>(reg_vec),
+                                             absl::StrCat("v", reg_no));
       inst->AppendSource(op);
     }
-    for (auto &reg_no : destinations) {
-      std::vector<RegisterBase *> reg_vec;
+    for (auto& reg_no : destinations) {
+      std::vector<RegisterBase*> reg_vec;
       for (int i = 0; (i < 8) && (i + reg_no < 32); i++) {
         std::string reg_name = absl::StrCat("v", i + reg_no);
         reg_vec.push_back(
             state_->GetRegister<RVVectorRegister>(reg_name).first);
       }
-      auto *op = new RV32VectorDestinationOperand(
-          absl::Span<RegisterBase *>(reg_vec), 0, absl::StrCat("v", reg_no));
+      auto* op = new RV32VectorDestinationOperand(
+          absl::Span<RegisterBase*>(reg_vec), 0, absl::StrCat("v", reg_no));
       inst->AppendDestination(op);
     }
   }
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
-  void AppendVectorRegisterOperands(const std::vector<int> &sources,
-                                    const std::vector<int> &destinations) {
+  void AppendVectorRegisterOperands(const std::vector<int>& sources,
+                                    const std::vector<int>& destinations) {
     AppendVectorRegisterOperands(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
   template <typename T>
   T GetVectorRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
+    auto* reg = state_->GetRegister<RVVectorRegister>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -255,10 +255,10 @@
   // value.
   template <typename T>
   void SetVectorRegisterValues(
-      const std::vector<tuple<std::string, Span<const T>>> &values) {
-    for (auto &[vreg_name, span] : values) {
-      auto *vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
-      auto *db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
+      const std::vector<tuple<std::string, Span<const T>>>& values) {
+    for (auto& [vreg_name, span] : values) {
+      auto* vreg = state_->GetRegister<RVVectorRegister>(vreg_name).first;
+      auto* db = state_->db_factory()->MakeCopyOf(vreg->data_buffer());
       db->template Set<T>(span);
       vreg->SetDataBuffer(db);
       db->DecRef();
@@ -266,7 +266,7 @@
   }
 
   // Initializes the semantic function of the instruction object.
-  void SetSemanticFunction(Instruction *inst,
+  void SetSemanticFunction(Instruction* inst,
                            Instruction::SemanticFunction fcn) {
     inst->set_semantic_function(fcn);
   }
@@ -286,7 +286,7 @@
 
   // Configure the vector unit according to the vtype and vlen values.
   void ConfigureVectorUnit(uint32_t vtype, uint32_t vlen) {
-    Instruction *inst = new Instruction(state_);
+    Instruction* inst = new Instruction(state_);
     AppendImmediateOperands<uint32_t>(inst, {vlen, vtype});
     SetSemanticFunction(inst, absl::bind_front(&Vsetvl, true, false));
     inst->Execute(nullptr);
@@ -296,7 +296,7 @@
   template <typename T>
   T ComputeValue(int address) {
     T value = 0;
-    uint8_t *ptr = reinterpret_cast<uint8_t *>(&value);
+    uint8_t* ptr = reinterpret_cast<uint8_t*>(&value);
     for (int j = 0; j < sizeof(T); j++) {
       ptr[j] = (address + j) & 0xff;
     }
@@ -824,7 +824,7 @@
         instruction_->Execute(nullptr);
 
         // Check memory values.
-        auto *data_db = state_->db_factory()->Allocate<T>(1);
+        auto* data_db = state_->db_factory()->Allocate<T>(1);
         uint64_t base = kDataStoreAddress;
         T value = 1;
         for (int i = 0; i < 8 * kVectorLengthInBytes / sizeof(T); i++) {
@@ -876,7 +876,7 @@
       }
     }
 
-    auto *data_db = state_->db_factory()->Allocate<ValueType>(1);
+    auto* data_db = state_->db_factory()->Allocate<ValueType>(1);
     // Iterate over different lmul values.
     for (int lmul_index = 0; lmul_index < 7; lmul_index++) {
       // Configure vector unit.
@@ -969,7 +969,7 @@
 
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
     // Can load all the data in one load, so set the data_db size accordingly.
-    auto *data_db =
+    auto* data_db =
         state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes * 8);
     // Iterate over legal values in the nf field.
     for (int nf = 1; nf < 8; nf++) {
@@ -1082,7 +1082,7 @@
 
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
 
-    auto *data_db = state_->db_factory()->Allocate<T>(1);
+    auto* data_db = state_->db_factory()->Allocate<T>(1);
     // Iterate over legal values in the nf field.
     for (int nf = 1; nf < 8; nf++) {
       int num_fields = nf + 1;
@@ -1205,7 +1205,7 @@
     int index_values_per_reg = kVectorLengthInBytes / sizeof(IndexType);
     int num_values_per_register = kVectorLengthInBytes / sizeof(T);
 
-    auto *data_db = state_->db_factory()->Allocate<T>(1);
+    auto* data_db = state_->db_factory()->Allocate<T>(1);
     // Iterate over legal values in the nf field.
     for (int nf = 1; nf < 8; nf++) {
       int num_fields = nf + 1;
@@ -1329,13 +1329,13 @@
   }
 
  protected:
-  RV32Register *xreg_[32];
-  RVVectorRegister *vreg_[32];
-  RiscVState *state_;
-  Instruction *instruction_;
-  Instruction *child_instruction_;
-  FlatDemandMemory *memory_;
-  RiscVVectorState *rv_vector_;
+  RV32Register* xreg_[32];
+  RVVectorRegister* vreg_[32];
+  RiscVState* state_;
+  Instruction* instruction_;
+  Instruction* child_instruction_;
+  FlatDemandMemory* memory_;
+  RiscVVectorState* rv_vector_;
 };
 
 // Test the vector configuration set instructions. There are three separate
@@ -1760,7 +1760,7 @@
 
   // Verify result.
   EXPECT_FALSE(rv_vector_->vector_exception());
-  auto *data_db = state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes);
+  auto* data_db = state_->db_factory()->Allocate<uint8_t>(kVectorLengthInBytes);
   state_->LoadMemory(instruction_, kDataStoreAddress, data_db, nullptr,
                      nullptr);
   auto span = data_db->Get<uint8_t>();
diff --git a/riscv/test/riscv_vector_opi_instructions_test.cc b/riscv/test/riscv_vector_opi_instructions_test.cc
index 28cefbe..9aba9d5 100644
--- a/riscv/test/riscv_vector_opi_instructions_test.cc
+++ b/riscv/test/riscv_vector_opi_instructions_test.cc
@@ -2042,8 +2042,8 @@
 }
 
 // This wrapper function factors out the main body of the Vmvr test.
-void VmvrWrapper(int num_reg, RiscVVectorInstructionsTest *tester,
-                 Instruction *inst) {
+void VmvrWrapper(int num_reg, RiscVVectorInstructionsTest* tester,
+                 Instruction* inst) {
   tester->SetSemanticFunction(absl::bind_front(&Vmvr, num_reg));
   // Number of elements per vector register.
   constexpr int vs2_size = kVectorLengthInBytes / sizeof(uint64_t);
@@ -2093,7 +2093,7 @@
 
 // Templated helper functions for Vssr testing.
 template <typename T>
-T VssrHelper(RiscVVectorInstructionsTest *tester, T vs2, T vs1,
+T VssrHelper(RiscVVectorInstructionsTest* tester, T vs2, T vs1,
              int rounding_mode) {
   using UT = typename MakeUnsigned<T>::type;
   int max_shift = (sizeof(T) << 3) - 1;
@@ -2111,8 +2111,8 @@
 // These wrapper functions simplify the test bodies, and make it a little
 // easier to avoid errors due to type and sew specifications.
 template <typename T>
-void VssrVVWrapper(absl::string_view base_name, Instruction *inst,
-                   RiscVVectorInstructionsTest *tester) {
+void VssrVVWrapper(absl::string_view base_name, Instruction* inst,
+                   RiscVVectorInstructionsTest* tester) {
   // Iterate across rounding modes.
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2124,8 +2124,8 @@
   }
 }
 template <typename T>
-void VssrVXWrapper(absl::string_view base_name, Instruction *inst,
-                   RiscVVectorInstructionsTest *tester) {
+void VssrVXWrapper(absl::string_view base_name, Instruction* inst,
+                   RiscVVectorInstructionsTest* tester) {
   // Iterate across rounding modes.
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2210,8 +2210,8 @@
 
 // Templated helper functions for Vnclip/Vnclipu instructions.
 template <typename T, typename WideT>
-T VnclipHelper(RiscVVectorInstructionsTest *tester, WideT vs2, T vs1, int rm,
-               RiscVVectorState *rv_vector) {
+T VnclipHelper(RiscVVectorInstructionsTest* tester, WideT vs2, T vs1, int rm,
+               RiscVVectorState* rv_vector) {
   auto vs1_16 = static_cast<WideT>(vs1);
   auto shifted = VssrHelper<WideT>(tester, vs2, vs1_16, rm);
   if (shifted < std::numeric_limits<T>::min()) {
@@ -2226,8 +2226,8 @@
 }
 
 template <typename T>
-void VnclipVVWrapper(absl::string_view base_name, Instruction *inst,
-                     RiscVVectorInstructionsTest *tester) {
+void VnclipVVWrapper(absl::string_view base_name, Instruction* inst,
+                     RiscVVectorInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2239,8 +2239,8 @@
   }
 }
 template <typename T>
-void VnclipVXWrapper(absl::string_view base_name, Instruction *inst,
-                     RiscVVectorInstructionsTest *tester) {
+void VnclipVXWrapper(absl::string_view base_name, Instruction* inst,
+                     RiscVVectorInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
@@ -2310,8 +2310,8 @@
 
 // Vector fractional multiply with rounding and saturation.
 template <typename T>
-T VsmulHelper(RiscVVectorInstructionsTest *tester, T vs2, T vs1, int rm,
-              RiscVVectorState *rv_vector) {
+T VsmulHelper(RiscVVectorInstructionsTest* tester, T vs2, T vs1, int rm,
+              RiscVVectorState* rv_vector) {
   using WT = typename WideType<T>::type;
   WT vs2_w = static_cast<WT>(vs2);
   WT vs1_w = static_cast<WT>(vs1);
@@ -2327,8 +2327,8 @@
 }
 
 template <typename T>
-void VsmulVVWrapper(absl::string_view base_name, Instruction *inst,
-                    RiscVVectorInstructionsTest *tester) {
+void VsmulVVWrapper(absl::string_view base_name, Instruction* inst,
+                    RiscVVectorInstructionsTest* tester) {
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
     tester->BinaryOpTestHelperVV<T, T, T>(
@@ -2339,8 +2339,8 @@
   }
 }
 template <typename T>
-void VsmulVXWrapper(absl::string_view base_name, Instruction *inst,
-                    RiscVVectorInstructionsTest *tester) {
+void VsmulVXWrapper(absl::string_view base_name, Instruction* inst,
+                    RiscVVectorInstructionsTest* tester) {
   for (int rm = 0; rm < 4; rm++) {
     tester->rv_vector()->set_vxrm(rm);
     tester->BinaryOpTestHelperVV<T, T, T>(
diff --git a/riscv/test/riscv_vector_opm_instructions_test.cc b/riscv/test/riscv_vector_opm_instructions_test.cc
index 1a6c396..786e12f 100644
--- a/riscv/test/riscv_vector_opm_instructions_test.cc
+++ b/riscv/test/riscv_vector_opm_instructions_test.cc
@@ -139,7 +139,7 @@
 
 // Helper functions for averaging add and subtract.
 template <typename T>
-T VaaddHelper(RiscVVectorOpmInstructionsTest *tester, T vs2, T vs1) {
+T VaaddHelper(RiscVVectorOpmInstructionsTest* tester, T vs2, T vs1) {
   // Create two sums, lower nibble, and the upper part. Then combine after
   // rounding.
   T vs2_l = vs2 & 0xf;
@@ -157,7 +157,7 @@
 }
 
 template <typename T>
-T VasubHelper(RiscVVectorOpmInstructionsTest *tester, T vs2, T vs1) {
+T VasubHelper(RiscVVectorOpmInstructionsTest* tester, T vs2, T vs1) {
   // Create two diffs, lower nibble, and the upper part. Then combine after
   // rounding.
   T vs2_l = vs2 & 0xf;
@@ -176,7 +176,7 @@
 
 // Vaaddu vector-vector test helper function.
 template <typename T>
-inline void VaadduVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VaadduVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaaddu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -187,7 +187,7 @@
 
 // Vaaddu vector-scalar test helper function.
 template <typename T>
-inline void VaadduVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VaadduVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaaddu);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -219,7 +219,7 @@
 
 // Vaadd vector-vector test helper function.
 template <typename T>
-inline void VaaddVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VaaddVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaadd);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -230,7 +230,7 @@
 
 // Vaadd vector-vector test helper function.
 template <typename T>
-inline void VaaddVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VaaddVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vaadd);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vaaddu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -262,7 +262,7 @@
 
 // Vasubu vector-vector test helper function.
 template <typename T>
-inline void VasubuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VasubuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasubu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vasubu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -272,7 +272,7 @@
 }
 // Vasubu vector-scalar test helper function.
 template <typename T>
-inline void VasubuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VasubuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasubu);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vasubu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -304,7 +304,7 @@
 
 // Vasub vector-vector test helper function.
 template <typename T>
-inline void VasubVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VasubVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasub);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vasub", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -314,7 +314,7 @@
 }
 // Vasub vector-scalar test helper function.
 template <typename T>
-inline void VasubVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VasubVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vasub);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vasub", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -397,7 +397,7 @@
 
 // Vdivu vector-vector test helper function.
 template <typename T>
-inline void VdivuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VdivuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdivu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vdivu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -408,7 +408,7 @@
 }
 // Vdivu vector-scalar test helper function.
 template <typename T>
-inline void VdivuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VdivuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdivu);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vdivu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -441,7 +441,7 @@
 
 // Vdiv vector-vector test helper function.
 template <typename T>
-inline void VdivVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VdivVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdiv);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vdiv", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -452,7 +452,7 @@
 }
 // Vdiv vector-scalar test helper function.
 template <typename T>
-inline void VdivVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VdivVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vdiv);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vdiv", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -485,7 +485,7 @@
 
 // Vremu vector-vector test helper function.
 template <typename T>
-inline void VremuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VremuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vremu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vremu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -496,7 +496,7 @@
 }
 // Vremu vector-scalar test helper function.
 template <typename T>
-inline void VremuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VremuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vremu);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vremu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -529,7 +529,7 @@
 
 // Vrem vector-vector test helper function.
 template <typename T>
-inline void VremVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VremVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vrem);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vrem", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -540,7 +540,7 @@
 }
 // Vrem vector-scalar test helper function.
 template <typename T>
-inline void VremVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VremVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vrem);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vrem", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -573,7 +573,7 @@
 
 // Vmulhu vector-vector test helper function.
 template <typename T>
-inline void VmulhuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulhu);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmulhu", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -586,7 +586,7 @@
 }
 // Vmulhu vector-scalar test helper function.
 template <typename T>
-inline void VmulhuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulhu);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vmulhu", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -621,7 +621,7 @@
 
 // Vmulh vector-vector test helper function.
 template <typename T>
-inline void VmulhVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulh);
   tester->BinaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmulh", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -635,7 +635,7 @@
 
 // Vmulh vector-scalar test helper function.
 template <typename T>
-inline void VmulhVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmulh);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vmulh", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -670,7 +670,7 @@
 
 // Vmul vector-vector test helper function.
 template <typename T>
-inline void VmulVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vmul);
   tester->BinaryOpTestHelperVV<T, T, T>(
@@ -682,7 +682,7 @@
 
 // Vmul vector-scalar test helper function.
 template <typename T>
-inline void VmulVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vmul);
   tester->BinaryOpTestHelperVX<T, T, T, RVScalarRegister>(
@@ -715,7 +715,7 @@
 
 // Vmulhsu vector-vector test helper function.
 template <typename T>
-inline void VmulhsuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhsuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using ST = typename std::make_signed<T>::type;
   tester->SetSemanticFunction(&Vmulhsu);
   tester->BinaryOpTestHelperVV<T, ST, T>(
@@ -730,7 +730,7 @@
 
 // Vmulhsu vector-scalar test helper function.
 template <typename T>
-inline void VmulhsuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmulhsuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using ST = typename std::make_signed<T>::type;
   tester->SetSemanticFunction(&Vmulhsu);
   tester->BinaryOpTestHelperVX<T, ST, T, RVScalarRegister>(
@@ -766,7 +766,7 @@
 
 // Vmadd vector-vector test helper function.
 template <typename T>
-inline void VmaddVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmaddVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmadd);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmadd", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -784,7 +784,7 @@
 
 // Vmadd vector-scalar test helper function.
 template <typename T>
-inline void VmaddVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmaddVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmadd);
   tester->TernaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vmadd", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -823,7 +823,7 @@
 
 // Vnmsub vector-vector test helper function.
 template <typename T>
-inline void VnmsubVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VnmsubVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsub);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vnmsub", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -841,7 +841,7 @@
 
 // Vnmsub vector-scalar test helper function.
 template <typename T>
-inline void VnmsubVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VnmsubVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsub);
   tester->TernaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vnmsub", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -880,7 +880,7 @@
 
 // Vmacc vector-vector test helper function.
 template <typename T>
-inline void VmaccVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmaccVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmacc);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vmacc", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -898,7 +898,7 @@
 
 // Vmacc vector-scalar test helper function.
 template <typename T>
-inline void VmaccVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VmaccVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vmacc);
   tester->TernaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vmacc", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -937,7 +937,7 @@
 
 // Vnmsac vector-vector test helper function.
 template <typename T>
-inline void VnmsacVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VnmsacVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsac);
   tester->TernaryOpTestHelperVV<T, T, T>(
       absl::StrCat("Vnmsac", sizeof(T) * 8, "vv"), /*sew*/ sizeof(T) * 8,
@@ -955,7 +955,7 @@
 
 // Vnmsac vector-scalar test helper function.
 template <typename T>
-inline void VnmsacVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VnmsacVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   tester->SetSemanticFunction(&Vnmsac);
   tester->TernaryOpTestHelperVX<T, T, T, RVScalarRegister>(
       absl::StrCat("Vnmsac", sizeof(T) * 8, "vx"), /*sew*/ sizeof(T) * 8,
@@ -994,7 +994,7 @@
 
 // Vwaddu vector-vector test helper function.
 template <typename T>
-inline void VwadduVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwadduVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1006,7 +1006,7 @@
 
 // Vwaddu vector-scalar test helper function.
 template <typename T>
-inline void VwadduVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwadduVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddu);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1037,7 +1037,7 @@
 
 // Vwsubu vector-vector test helper function.
 template <typename T>
-inline void VwsubuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1049,7 +1049,7 @@
 
 // Vwsubu vector-scalar test helper function.
 template <typename T>
-inline void VwsubuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubu);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1080,7 +1080,7 @@
 
 // Vwadd vector-vector test helper function.
 template <typename T>
-inline void VwaddVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwaddVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadd);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1092,7 +1092,7 @@
 
 // Vwadd vector-scalar test helper function.
 template <typename T>
-inline void VwaddVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwaddVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadd);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1123,7 +1123,7 @@
 
 // Vwsub vector-vector test helper function.
 template <typename T>
-inline void VwsubVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsub);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1138,7 +1138,7 @@
 
 // Vwsub vector-scalar test helper function.
 template <typename T>
-inline void VwsubVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsub);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1172,7 +1172,7 @@
 
 // Vwadduw vector-vector test helper function.
 template <typename T>
-inline void VwadduwVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwadduwVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadduw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1183,7 +1183,7 @@
 
 // Vwadduw vector-scalar test helper function.
 template <typename T>
-inline void VwadduwVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwadduwVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwadduw);
   tester->BinaryOpTestHelperVX<WT, WT, T, RVScalarRegister>(
@@ -1213,7 +1213,7 @@
 
 // Vwsubuw vector-vector test helper function.
 template <typename T>
-inline void VwsubuwVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubuwVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubuw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1224,7 +1224,7 @@
 
 // Vwsubuw vector-scalar test helper function.
 template <typename T>
-inline void VwsubuwVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubuwVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubuw);
   tester->BinaryOpTestHelperVX<WT, WT, T, RVScalarRegister>(
@@ -1254,7 +1254,7 @@
 
 // Vwaddw vector-vector test helper function.
 template <typename T>
-inline void VwaddwVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwaddwVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1265,7 +1265,7 @@
 
 // Vwaddw vector-scalar test helper function.
 template <typename T>
-inline void VwaddwVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwaddwVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwaddw);
   tester->BinaryOpTestHelperVX<WT, WT, T, RVScalarRegister>(
@@ -1295,7 +1295,7 @@
 
 // Vwsubw vector-vector test helper function.
 template <typename T>
-inline void VwsubwVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubwVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubw);
   tester->BinaryOpTestHelperVV<WT, WT, T>(
@@ -1306,7 +1306,7 @@
 
 // Vwsubw vector-scalar test helper function.
 template <typename T>
-inline void VwsubwVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwsubwVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwsubw);
   tester->BinaryOpTestHelperVX<WT, WT, T, RVScalarRegister>(
@@ -1336,7 +1336,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmuluVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmuluVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmulu);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1348,7 +1348,7 @@
 
 // Vwmulu vector-scalar test helper function.
 template <typename T>
-inline void VwmuluVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmuluVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmulu);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1379,7 +1379,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmulVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmulVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmul);
   tester->BinaryOpTestHelperVV<WT, T, T>(
@@ -1391,7 +1391,7 @@
 
 // Vwmul vector-scalar test helper function.
 template <typename T>
-inline void VwmulVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmulVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmul);
   tester->BinaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1422,7 +1422,7 @@
 
 // Vwmul vector-vector test helper function.
 template <typename T>
-inline void VwmulsuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmulsuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmulsu);
@@ -1435,7 +1435,7 @@
 
 // Vwmulsu vector-scalar test helper function.
 template <typename T>
-inline void VwmulsuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmulsuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmulsu);
@@ -1467,7 +1467,7 @@
 
 // Vmaccu vector-vector test helper function.
 template <typename T>
-inline void VwmaccuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmaccu);
   tester->TernaryOpTestHelperVV<WT, T, T>(
@@ -1479,7 +1479,7 @@
 
 // Vwmaccu vector-scalar test helper function.
 template <typename T>
-inline void VwmaccuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmaccu);
   tester->TernaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1508,7 +1508,7 @@
 
 // Vmacc vector-vector test helper function.
 template <typename T>
-inline void VwmaccVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmacc);
   tester->TernaryOpTestHelperVV<WT, T, T>(
@@ -1525,7 +1525,7 @@
 
 // Vwmacc vector-scalar test helper function.
 template <typename T>
-inline void VwmaccVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   tester->SetSemanticFunction(&Vwmacc);
   tester->TernaryOpTestHelperVX<WT, T, T, RVScalarRegister>(
@@ -1559,7 +1559,7 @@
 
 // Vmaccus vector-vector test helper function.
 template <typename T>
-inline void VwmaccusVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccusVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccus);
@@ -1577,7 +1577,7 @@
 
 // Vwmaccus vector-scalar test helper function.
 template <typename T>
-inline void VwmaccusVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccusVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccus);
@@ -1612,7 +1612,7 @@
 
 // Vmaccsu vector-vector test helper function.
 template <typename T>
-inline void VwmaccsuVVHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccsuVVHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccsu);
@@ -1630,7 +1630,7 @@
 
 // Vwmaccsu vector-scalar test helper function.
 template <typename T>
-inline void VwmaccsuVXHelper(RiscVVectorOpmInstructionsTest *tester) {
+inline void VwmaccsuVXHelper(RiscVVectorOpmInstructionsTest* tester) {
   using WT = typename WideType<T>::type;
   using UT = typename std::make_unsigned<T>::type;
   tester->SetSemanticFunction(&Vwmaccsu);
diff --git a/riscv/test/riscv_vector_permute_instructions_test.cc b/riscv/test/riscv_vector_permute_instructions_test.cc
index d649d59..f71a970 100644
--- a/riscv/test/riscv_vector_permute_instructions_test.cc
+++ b/riscv/test/riscv_vector_permute_instructions_test.cc
@@ -56,9 +56,9 @@
 
 // Helper function for vector-vector vrgather instructions.
 template <typename T, typename I>
-void VrgatherVVHelper(RiscVVectorPermuteInstructionsTest *tester,
-                      Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void VrgatherVVHelper(RiscVVectorPermuteInstructionsTest* tester,
+                      Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   // Configure vector unit for sew and maximum lmul.
   uint32_t vtype = 0;
   int max_regs = 8;
@@ -126,9 +126,9 @@
 
 // Helper function for vector-scalar vrgather instructions.
 template <typename T>
-void VrgatherVSHelper(RiscVVectorPermuteInstructionsTest *tester,
-                      Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void VrgatherVSHelper(RiscVVectorPermuteInstructionsTest* tester,
+                      Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   // Configure vector unit.
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
@@ -266,9 +266,9 @@
 
 // Helper function for slideup/down instructions.
 template <typename T>
-void SlideHelper(RiscVVectorPermuteInstructionsTest *tester, Instruction *inst,
+void SlideHelper(RiscVVectorPermuteInstructionsTest* tester, Instruction* inst,
                  bool is_slide_up) {
-  auto *rv_vector = tester->rv_vector();
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);
@@ -412,9 +412,9 @@
 }
 
 template <typename T>
-void Slide1Helper(RiscVVectorPermuteInstructionsTest *tester, Instruction *inst,
+void Slide1Helper(RiscVVectorPermuteInstructionsTest* tester, Instruction* inst,
                   bool is_slide_up) {
-  auto *rv_vector = tester->rv_vector();
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);
@@ -550,9 +550,9 @@
 }
 
 template <typename T>
-void CompressHelper(RiscVVectorPermuteInstructionsTest *tester,
-                    Instruction *inst) {
-  auto *rv_vector = tester->rv_vector();
+void CompressHelper(RiscVVectorPermuteInstructionsTest* tester,
+                    Instruction* inst) {
+  auto* rv_vector = tester->rv_vector();
   uint32_t vtype =
       (kSewSettingsByByteSize[sizeof(T)] << 3) | kLmulSettingByLogSize[7];
   tester->ConfigureVectorUnit(vtype, 2048);
diff --git a/riscv/test/riscv_vector_reduction_instructions_test.cc b/riscv/test/riscv_vector_reduction_instructions_test.cc
index ba51fcb..827419c 100644
--- a/riscv/test/riscv_vector_reduction_instructions_test.cc
+++ b/riscv/test/riscv_vector_reduction_instructions_test.cc
@@ -16,17 +16,17 @@
 
 #include <algorithm>
 #include <cstdint>
-#include <limits>
-#include <string>
+#include <functional>
 #include <vector>
 
 #include "absl/random/random.h"
+#include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
+#include "absl/types/span.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/generic/type_helpers.h"
 #include "riscv/riscv_register.h"
-#include "riscv/riscv_vector_state.h"
 #include "riscv/test/riscv_vector_instructions_test_base.h"
 
 namespace {
@@ -64,7 +64,7 @@
     : public RiscVVectorInstructionsTestBase {
  public:
   template <typename Vd, typename Vs2>
-  void ReductionOpTestHelper(absl::string_view name, int sew, Instruction *inst,
+  void ReductionOpTestHelper(absl::string_view name, int sew, Instruction* inst,
                              std::function<Vd(Vd, Vs2)> operation) {
     int byte_sew = sew / 8;
     if (byte_sew != sizeof(Vd) && byte_sew != sizeof(Vs2)) {
diff --git a/riscv/test/riscv_vector_true_test.cc b/riscv/test/riscv_vector_true_test.cc
index ec9139a..bb0d992 100644
--- a/riscv/test/riscv_vector_true_test.cc
+++ b/riscv/test/riscv_vector_true_test.cc
@@ -42,12 +42,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  RiscVVectorState *vstate_;
+  RiscVState* state_;
+  RiscVVectorState* vstate_;
 };
 
 TEST_F(RV32VectorTrueTest, Initial) {
-  auto *op = new RV32VectorTrueOperand(state_);
+  auto* op = new RV32VectorTrueOperand(state_);
   for (int i = 0; i < op->shape()[0]; ++i) {
     EXPECT_EQ(op->AsUint8(i), 0xff) << "element: " << i;
   }
@@ -55,8 +55,8 @@
 }
 
 TEST_F(RV32VectorTrueTest, Register) {
-  auto *op = new RV32VectorTrueOperand(state_);
-  auto *reg = op->GetRegister(0);
+  auto* op = new RV32VectorTrueOperand(state_);
+  auto* reg = op->GetRegister(0);
   auto span = reg->data_buffer()->Get<uint8_t>();
   for (int i = 0; i < op->shape()[0]; ++i) {
     EXPECT_EQ(span[i], 0xff) << "element: " << i;
diff --git a/riscv/test/riscv_vector_unary_instructions_test.cc b/riscv/test/riscv_vector_unary_instructions_test.cc
index 84953ea..50cdb86 100644
--- a/riscv/test/riscv_vector_unary_instructions_test.cc
+++ b/riscv/test/riscv_vector_unary_instructions_test.cc
@@ -568,7 +568,7 @@
 
 // Helper function for testing Viota instructions.
 template <typename T>
-void TestViota(RiscVVectorUnaryInstructionsTest *tester, Instruction *inst) {
+void TestViota(RiscVVectorUnaryInstructionsTest* tester, Instruction* inst) {
   // Set up vector unit.
   int byte_sew = sizeof(T);
   uint32_t vtype =
@@ -643,7 +643,7 @@
 
 // Helper function for testing Vid instructions.
 template <typename T>
-void TestVid(RiscVVectorUnaryInstructionsTest *tester, Instruction *inst) {
+void TestVid(RiscVVectorUnaryInstructionsTest* tester, Instruction* inst) {
   // Initialize the vector unit.
   int byte_sew = sizeof(T);
   uint32_t vtype =
diff --git a/riscv/test/riscv_zc64_instructions_test.cc b/riscv/test/riscv_zc64_instructions_test.cc
index 2d97701..52ea359 100644
--- a/riscv/test/riscv_zc64_instructions_test.cc
+++ b/riscv/test/riscv_zc64_instructions_test.cc
@@ -72,7 +72,7 @@
     instruction_->set_size(4);
     // Set the jump table address to 0x4000.
     state_->jvt()->Set(static_cast<uint64_t>(0x4000));
-    auto *db = state_->db_factory()->Allocate<uint64_t>(256);
+    auto* db = state_->db_factory()->Allocate<uint64_t>(256);
     auto db_span = db->Get<uint64_t>();
     for (auto i = 0; i < 256; ++i) {
       db_span[i] = 0x8000 + i * sizeof(uint64_t);
@@ -89,29 +89,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -120,8 +120,8 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
       reg->data_buffer()->template Set<T>(0, value);
     }
   }
@@ -134,7 +134,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV64Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV64Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -175,19 +175,19 @@
   }
 
   void ResetMemory() {
-    auto *db = state_->db_factory()->Allocate<uint8_t>(0x2000);
+    auto* db = state_->db_factory()->Allocate<uint8_t>(0x2000);
     std::memset(db->raw_ptr(), 0, 0x2000);
     state_->StoreMemory(instruction_, 0, db);
     db->DecRef();
   }
 
-  FlatDemandMemory *memory_;
-  RiscVState *state_;
-  Instruction *instruction_;
+  FlatDemandMemory* memory_;
+  RiscVState* state_;
+  Instruction* instruction_;
 };
 
 constexpr int kNumReg[] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13};
-constexpr char const *kRegMap[] = {kX1,  kX8,  kX9,  kX18, kX19, kX20, kX21,
+constexpr char const* kRegMap[] = {kX1,  kX8,  kX9,  kX18, kX19, kX20, kX21,
                                    kX22, kX23, kX24, kX25, kX26, kX27};
 constexpr int kStackAdjBase[] = {
     0, 0, 0, 0, 16, 16, 32, 32, 48, 48, 64, 64, 80, 80, 96, 112,
@@ -226,7 +226,7 @@
       instruction_->Execute(nullptr);
 
       // Fetch memory content.
-      auto *db = state_->db_factory()->Allocate<uint64_t>(13);
+      auto* db = state_->db_factory()->Allocate<uint64_t>(13);
       state_->LoadMemory(instruction_,
                          kMemAddress - kNumReg[rlist] * sizeof(uint64_t), db,
                          nullptr, nullptr);
@@ -255,7 +255,7 @@
 }
 
 TEST_F(RV64ZcInstructionTest, RV64ZCmpPop) {
-  auto *db = state_->db_factory()->Allocate<uint64_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint64_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
@@ -322,7 +322,7 @@
 }
 
 TEST_F(RV64ZcInstructionTest, RV64ZCmpPopRet) {
-  auto *db = state_->db_factory()->Allocate<uint64_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint64_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
@@ -391,7 +391,7 @@
 }
 
 TEST_F(RV64ZcInstructionTest, RV64ZCmpPopRetz) {
-  auto *db = state_->db_factory()->Allocate<uint64_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint64_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
diff --git a/riscv/test/riscv_zc_instructions_test.cc b/riscv/test/riscv_zc_instructions_test.cc
index 4412812..b2283f8 100644
--- a/riscv/test/riscv_zc_instructions_test.cc
+++ b/riscv/test/riscv_zc_instructions_test.cc
@@ -73,7 +73,7 @@
     instruction_->set_size(4);
     // Set the jump table address to 0x4000.
     state_->jvt()->Set(static_cast<uint32_t>(0x4000));
-    auto *db = state_->db_factory()->Allocate<uint32_t>(256);
+    auto* db = state_->db_factory()->Allocate<uint32_t>(256);
     auto db_span = db->Get<uint32_t>();
     for (auto i = 0; i < 256; ++i) {
       db_span[i] = 0x8000 + i * sizeof(uint64_t);
@@ -90,29 +90,29 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
     AppendRegisterOperands(instruction_, sources, destinations);
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(const std::vector<T> &values) {
+  void AppendImmediateOperands(const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       instruction_->AppendSource(src);
     }
   }
@@ -121,8 +121,8 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       reg->data_buffer()->template Set<T>(0, value);
     }
   }
@@ -135,7 +135,7 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
@@ -176,19 +176,19 @@
   }
 
   void ResetMemory() {
-    auto *db = state_->db_factory()->Allocate<uint8_t>(0x2000);
+    auto* db = state_->db_factory()->Allocate<uint8_t>(0x2000);
     std::memset(db->raw_ptr(), 0, 0x2000);
     state_->StoreMemory(instruction_, 0, db);
     db->DecRef();
   }
 
-  FlatDemandMemory *memory_;
-  RiscVState *state_;
-  Instruction *instruction_;
+  FlatDemandMemory* memory_;
+  RiscVState* state_;
+  Instruction* instruction_;
 };
 
 constexpr int kNumReg[] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13};
-constexpr char const *kRegMap[] = {kX1,  kX8,  kX9,  kX18, kX19, kX20, kX21,
+constexpr char const* kRegMap[] = {kX1,  kX8,  kX9,  kX18, kX19, kX20, kX21,
                                    kX22, kX23, kX24, kX25, kX26, kX27};
 constexpr int kStackAdjBase[] = {
     0, 0, 0, 0, 16, 16, 16, 16, 32, 32, 32, 32, 48, 48, 48, 64,
@@ -227,7 +227,7 @@
       instruction_->Execute(nullptr);
 
       // Fetch memory content.
-      auto *db = state_->db_factory()->Allocate<uint32_t>(13);
+      auto* db = state_->db_factory()->Allocate<uint32_t>(13);
       state_->LoadMemory(instruction_,
                          kMemAddress - kNumReg[rlist] * sizeof(uint32_t), db,
                          nullptr, nullptr);
@@ -256,7 +256,7 @@
 }
 
 TEST_F(RV32ZcInstructionTest, RV32ZCmpPop) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
@@ -323,7 +323,7 @@
 }
 
 TEST_F(RV32ZcInstructionTest, RV32ZCmpPopRet) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
@@ -392,7 +392,7 @@
 }
 
 TEST_F(RV32ZcInstructionTest, RV32ZCmpPopRetz) {
-  auto *db = state_->db_factory()->Allocate<uint32_t>(13);
+  auto* db = state_->db_factory()->Allocate<uint32_t>(13);
   // Test each combination of rlist and spimm6.
   for (int rlist = 4; rlist < 16; ++rlist) {
     for (int spimm6 = 0; spimm6 < 64; spimm6 += 16) {
diff --git a/riscv/test/riscv_zfh_instructions_test.cc b/riscv/test/riscv_zfh_instructions_test.cc
index 1630e05..28c1df6 100644
--- a/riscv/test/riscv_zfh_instructions_test.cc
+++ b/riscv/test/riscv_zfh_instructions_test.cc
@@ -152,13 +152,13 @@
   template <typename DestRegisterType, typename LhsRegisterType, typename R,
             typename LHS>
   void UnaryOpWithFflagsMixedTestHelper(
-      absl::string_view name, Instruction *inst,
+      absl::string_view name, Instruction* inst,
       absl::Span<const absl::string_view> reg_prefixes, int delta_position,
       std::function<std::tuple<R, uint32_t>(LHS, int)> operation);
 
   template <typename R, typename LHS, typename MHS, typename RHS>
   void TernaryOpWithFflagsFPTestHelper(
-      absl::string_view name, Instruction *inst,
+      absl::string_view name, Instruction* inst,
       absl::Span<const absl::string_view> reg_prefixes, int delta_position,
       std::function<std::tuple<R, uint32_t>(LHS, MHS, RHS)> operation);
 
@@ -188,7 +188,7 @@
 template <typename AddressType, typename ValueType>
 void RVZfhInstructionTestBase<XRegister>::SetupMemory(AddressType address,
                                                       ValueType value) {
-  DataBuffer *mem_db =
+  DataBuffer* mem_db =
       this->state_->db_factory()->template Allocate<ValueType>(1);
   mem_db->Set<ValueType>(0, value);
   this->state_->StoreMemory(this->instruction_, address, mem_db);
@@ -207,7 +207,7 @@
   this->template AppendRegisterOperands<RVFpRegister>(this->child_instruction_,
                                                       {}, {kFrdName});
 
-  ImmediateOperand<int16_t> *offset_source_operand =
+  ImmediateOperand<int16_t>* offset_source_operand =
       new ImmediateOperand<int16_t>(offset);
   this->instruction_->AppendSource(offset_source_operand);
 
@@ -251,7 +251,7 @@
 template <typename DestRegisterType, typename LhsRegisterType, typename R,
           typename LHS>
 void RVZfhInstructionTestBase<XRegister>::UnaryOpWithFflagsMixedTestHelper(
-    absl::string_view name, Instruction *inst,
+    absl::string_view name, Instruction* inst,
     absl::Span<const absl::string_view> reg_prefixes, int delta_position,
     std::function<std::tuple<R, uint32_t>(LHS, int)> operation) {
   using LhsInt = typename FPTypeInfo<LHS>::IntType;
@@ -273,33 +273,33 @@
     this->template AppendRegisterOperands<RVFpRegister>({}, {kRdName});
   }
   this->template AppendRegisterOperands<XRegister>({kRmName}, {});
-  auto *flag_op =
+  auto* flag_op =
       this->rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
   this->instruction_->AppendDestination(flag_op);
   if constexpr (std::is_integral<LHS>::value) {
-    for (auto &lhs : lhs_span) {
+    for (auto& lhs : lhs_span) {
       lhs = absl::Uniform(absl::IntervalClosed, this->bitgen_,
                           std::numeric_limits<LHS>::min(),
                           std::numeric_limits<LHS>::max());
     }
-    *reinterpret_cast<LHS *>(&lhs_span[0]) = 0;
-    *reinterpret_cast<LHS *>(&lhs_span[1]) = 1;
-    *reinterpret_cast<LHS *>(&lhs_span[2]) = 2;
-    *reinterpret_cast<LHS *>(&lhs_span[3]) = 4;
-    *reinterpret_cast<LHS *>(&lhs_span[4]) = 8;
-    *reinterpret_cast<LHS *>(&lhs_span[5]) = 16;
-    *reinterpret_cast<LHS *>(&lhs_span[6]) = 1024;
-    *reinterpret_cast<LHS *>(&lhs_span[7]) = 65000;
+    *reinterpret_cast<LHS*>(&lhs_span[0]) = 0;
+    *reinterpret_cast<LHS*>(&lhs_span[1]) = 1;
+    *reinterpret_cast<LHS*>(&lhs_span[2]) = 2;
+    *reinterpret_cast<LHS*>(&lhs_span[3]) = 4;
+    *reinterpret_cast<LHS*>(&lhs_span[4]) = 8;
+    *reinterpret_cast<LHS*>(&lhs_span[5]) = 16;
+    *reinterpret_cast<LHS*>(&lhs_span[6]) = 1024;
+    *reinterpret_cast<LHS*>(&lhs_span[7]) = 65000;
   } else {
     this->template FillArrayWithRandomFPValues<LHS>(lhs_span);
-    *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-    *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-    *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-    *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-    *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+    *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+    *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+    *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+    *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
   }
   for (int i = 0; i < kTestValueLength; i++) {
     if constexpr (std::is_integral<LHS>::value) {
@@ -349,7 +349,7 @@
 template <typename XRegister>
 template <typename R, typename LHS, typename MHS, typename RHS>
 void RVZfhInstructionTestBase<XRegister>::TernaryOpWithFflagsFPTestHelper(
-    absl::string_view name, Instruction *inst,
+    absl::string_view name, Instruction* inst,
     absl::Span<const absl::string_view> reg_prefixes, int delta_position,
     std::function<std::tuple<R, uint32_t>(LHS, MHS, RHS)> operation) {
   using LhsRegisterType = RVFpRegister;
@@ -386,42 +386,42 @@
   } else {
     this->template AppendRegisterOperands<RVFpRegister>({}, {kRdName});
   }
-  TestRoundingModeSourceOperand *rm_source_operand =
+  TestRoundingModeSourceOperand* rm_source_operand =
       new TestRoundingModeSourceOperand();
   this->instruction_->AppendSource(rm_source_operand);
-  auto *flag_op =
+  auto* flag_op =
       this->rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
   this->instruction_->AppendDestination(flag_op);
   this->template FillArrayWithRandomFPValues<LHS>(lhs_span);
   this->template FillArrayWithRandomFPValues<MHS>(mhs_span);
   this->template FillArrayWithRandomFPValues<RHS>(rhs_span);
   using LhsInt = typename FPTypeInfo<LHS>::IntType;
-  *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
-  *reinterpret_cast<LhsInt *>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
-  *reinterpret_cast<LhsInt *>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
-  *reinterpret_cast<LhsInt *>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
-  *reinterpret_cast<LhsInt *>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
-  *reinterpret_cast<LhsInt *>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
-  *reinterpret_cast<LhsInt *>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
-  *reinterpret_cast<LhsInt *>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
+  *reinterpret_cast<LhsInt*>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
+  *reinterpret_cast<LhsInt*>(&lhs_span[1]) = FPTypeInfo<LHS>::kSNaN;
+  *reinterpret_cast<LhsInt*>(&lhs_span[2]) = FPTypeInfo<LHS>::kPosInf;
+  *reinterpret_cast<LhsInt*>(&lhs_span[3]) = FPTypeInfo<LHS>::kNegInf;
+  *reinterpret_cast<LhsInt*>(&lhs_span[4]) = FPTypeInfo<LHS>::kPosZero;
+  *reinterpret_cast<LhsInt*>(&lhs_span[5]) = FPTypeInfo<LHS>::kNegZero;
+  *reinterpret_cast<LhsInt*>(&lhs_span[6]) = FPTypeInfo<LHS>::kPosDenorm;
+  *reinterpret_cast<LhsInt*>(&lhs_span[7]) = FPTypeInfo<LHS>::kNegDenorm;
   using MhsInt = typename FPTypeInfo<MHS>::IntType;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 0]) = FPTypeInfo<MHS>::kQNaN;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 1]) = FPTypeInfo<MHS>::kSNaN;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 2]) = FPTypeInfo<MHS>::kPosInf;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 3]) = FPTypeInfo<MHS>::kNegInf;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 4]) = FPTypeInfo<MHS>::kPosZero;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 5]) = FPTypeInfo<MHS>::kNegZero;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 6]) = FPTypeInfo<MHS>::kPosDenorm;
-  *reinterpret_cast<MhsInt *>(&mhs_span[8 + 7]) = FPTypeInfo<MHS>::kNegDenorm;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 0]) = FPTypeInfo<MHS>::kQNaN;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 1]) = FPTypeInfo<MHS>::kSNaN;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 2]) = FPTypeInfo<MHS>::kPosInf;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 3]) = FPTypeInfo<MHS>::kNegInf;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 4]) = FPTypeInfo<MHS>::kPosZero;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 5]) = FPTypeInfo<MHS>::kNegZero;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 6]) = FPTypeInfo<MHS>::kPosDenorm;
+  *reinterpret_cast<MhsInt*>(&mhs_span[8 + 7]) = FPTypeInfo<MHS>::kNegDenorm;
   using RhsInt = typename FPTypeInfo<RHS>::IntType;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 0]) = FPTypeInfo<RHS>::kQNaN;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 1]) = FPTypeInfo<RHS>::kSNaN;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 2]) = FPTypeInfo<RHS>::kPosInf;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 3]) = FPTypeInfo<RHS>::kNegInf;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 4]) = FPTypeInfo<RHS>::kPosZero;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 5]) = FPTypeInfo<RHS>::kNegZero;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 6]) = FPTypeInfo<RHS>::kPosDenorm;
-  *reinterpret_cast<RhsInt *>(&rhs_span[16 + 7]) = FPTypeInfo<RHS>::kNegDenorm;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 0]) = FPTypeInfo<RHS>::kQNaN;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 1]) = FPTypeInfo<RHS>::kSNaN;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 2]) = FPTypeInfo<RHS>::kPosInf;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 3]) = FPTypeInfo<RHS>::kNegInf;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 4]) = FPTypeInfo<RHS>::kPosZero;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 5]) = FPTypeInfo<RHS>::kNegZero;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 6]) = FPTypeInfo<RHS>::kPosDenorm;
+  *reinterpret_cast<RhsInt*>(&rhs_span[16 + 7]) = FPTypeInfo<RHS>::kNegDenorm;
   for (int i = 0; i < kTestValueLength; i++) {
     this->template SetNaNBoxedRegisterValues<LHS, LhsRegisterType>(
         {{kR1Name, lhs_span[i]}});
@@ -680,13 +680,13 @@
     // Configure source and destination operands for the instruction.
     AppendRegisterOperands<RVFpRegister>({"f1"}, {"f5"});
     instruction_->AppendSource(new TestRoundingModeSourceOperand());
-    auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
+    auto* flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     assert(instruction_->SourcesSize() == 2);
     assert(instruction_->DestinationsSize() == 2);
 
     // Set all operands to known values before executing the instruction.
-    static_cast<TestRoundingModeSourceOperand *>(instruction_->Source(1))
+    static_cast<TestRoundingModeSourceOperand*>(instruction_->Source(1))
         ->SetRoundingMode(static_cast<FPRoundingMode>(rm));
     rv_fp_->SetRoundingMode(static_cast<FPRoundingMode>(rm));
     SetNaNBoxedRegisterValues<U, RVFpRegister>({{"f1", input_val}});
@@ -701,8 +701,8 @@
   }
 
   template <FPRoundingMode>
-  void RoundingConversionTestHelper(uint32_t, uint16_t, uint32_t &, uint32_t,
-                                    uint16_t, uint32_t &);
+  void RoundingConversionTestHelper(uint32_t, uint16_t, uint32_t&, uint32_t,
+                                    uint16_t, uint32_t&);
 
   template <FPRoundingMode rm>
   void RoundingPointTest(uint16_t);
@@ -713,8 +713,8 @@
 template <FPRoundingMode rm>
 void RV32ZfhInstructionTest::RoundingConversionTestHelper(
     uint32_t float_uint_before, uint16_t half_uint_before,
-    uint32_t &first_expected_fflags, uint32_t float_uint_after,
-    uint16_t half_uint_after, uint32_t &second_expected_fflags) {
+    uint32_t& first_expected_fflags, uint32_t float_uint_after,
+    uint16_t half_uint_after, uint32_t& second_expected_fflags) {
   float input_val;
   HalfFP expected_val;
   HalfFP actual_val;
diff --git a/riscv/test/riscv_zicond_instructions_test.cc b/riscv/test/riscv_zicond_instructions_test.cc
index 576a331..5f45406 100644
--- a/riscv/test/riscv_zicond_instructions_test.cc
+++ b/riscv/test/riscv_zicond_instructions_test.cc
@@ -60,7 +60,7 @@
   template <typename RegisterType>
   typename RegisterType::ValueType GetRegisterValue(
       absl::string_view reg_name) {
-    RegisterType *reg;
+    RegisterType* reg;
     if constexpr (std::is_same_v<RegisterType, RV32Register>) {
       reg = rv32_regs_[reg_name];
     } else {
@@ -72,21 +72,21 @@
   }
 
   template <typename RegisterType>
-  void AppendRegisterOperands(const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    absl::flat_hash_map<std::string, RegisterType *> *regs;
+  void AppendRegisterOperands(const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    absl::flat_hash_map<std::string, RegisterType*>* regs;
     if constexpr (std::is_same_v<RegisterType, RV32Register>) {
       regs = &rv32_regs_;
     } else {
       regs = &rv64_regs_;
     }
     for (auto src : sources) {
-      auto *reg = (*regs)[src];
+      auto* reg = (*regs)[src];
       CHECK_NE(reg, nullptr);
       instruction_->AppendSource(reg->CreateSourceOperand());
     }
     for (auto dest : destinations) {
-      auto *reg = (*regs)[dest];
+      auto* reg = (*regs)[dest];
       CHECK_NE(reg, nullptr);
       instruction_->AppendDestination(reg->CreateDestinationOperand(0));
     }
@@ -97,16 +97,16 @@
       const std::vector<
           std::tuple<std::string, typename RegisterType::ValueType>>
           values) {
-    absl::flat_hash_map<std::string, RegisterType *> *regs;
+    absl::flat_hash_map<std::string, RegisterType*>* regs;
     if constexpr (std::is_same_v<RegisterType, RV32Register>) {
       regs = &rv32_regs_;
     } else {
       regs = &rv64_regs_;
     }
-    for (auto &[reg_name, value] : values) {
-      auto *reg = (*regs)[reg_name];
+    for (auto& [reg_name, value] : values) {
+      auto* reg = (*regs)[reg_name];
       CHECK_NE(reg, nullptr);
-      auto *db =
+      auto* db =
           state_.db_factory()->Allocate<typename RegisterType::ValueType>(1);
       db->template Set<typename RegisterType::ValueType>(0, value);
       reg->SetDataBuffer(db);
@@ -114,13 +114,13 @@
     }
   }
 
-  Instruction *instruction() { return instruction_; }
+  Instruction* instruction() { return instruction_; }
 
  private:
   TestState state_;
-  Instruction *instruction_;
-  absl::flat_hash_map<std::string, RV32Register *> rv32_regs_;
-  absl::flat_hash_map<std::string, RV64Register *> rv64_regs_;
+  Instruction* instruction_;
+  absl::flat_hash_map<std::string, RV32Register*> rv32_regs_;
+  absl::flat_hash_map<std::string, RV64Register*> rv64_regs_;
 };
 
 TEST_F(RiscVZicondInstructionTest, RV32CzeroEqz) {
diff --git a/riscv/test/riscv_zicsr_instructions_test.cc b/riscv/test/riscv_zicsr_instructions_test.cc
index 38f29c4..6aab6e3 100644
--- a/riscv/test/riscv_zicsr_instructions_test.cc
+++ b/riscv/test/riscv_zicsr_instructions_test.cc
@@ -71,25 +71,25 @@
 
   // Appends the source and destination operands for the register names
   // given in the two vectors.
-  void AppendRegisterOperands(Instruction *inst,
-                              const std::vector<std::string> &sources,
-                              const std::vector<std::string> &destinations) {
-    for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+  void AppendRegisterOperands(Instruction* inst,
+                              const std::vector<std::string>& sources,
+                              const std::vector<std::string>& destinations) {
+    for (auto& reg_name : sources) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
-    for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    for (auto& reg_name : destinations) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   // Appends immediate source operands with the given values.
   template <typename T>
-  void AppendImmediateOperands(Instruction *inst,
-                               const std::vector<T> &values) {
+  void AppendImmediateOperands(Instruction* inst,
+                               const std::vector<T>& values) {
     for (auto value : values) {
-      auto *src = new ImmediateOperand<T>(value);
+      auto* src = new ImmediateOperand<T>(value);
       inst->AppendSource(src);
     }
   }
@@ -98,9 +98,9 @@
   // named register and sets it to the corresponding value.
   template <typename T>
   void SetRegisterValues(const std::vector<std::tuple<std::string, T>> values) {
-    for (auto &[reg_name, value] : values) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
-      auto *db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
+    for (auto& [reg_name, value] : values) {
+      auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto* db = state_->db_factory()->Allocate<RV32Register::ValueType>(1);
       db->Set<T>(0, value);
       reg->SetDataBuffer(db);
       db->DecRef();
@@ -115,14 +115,14 @@
   // Returns the value of the named register.
   template <typename T>
   T GetRegisterValue(absl::string_view reg_name) {
-    auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+    auto* reg = state_->GetRegister<RV32Register>(reg_name).first;
     return reg->data_buffer()->Get<T>(0);
   }
 
   FlatDemandMemory memory_;
-  RiscV32SimpleCsr *csr_;
-  RiscVState *state_;
-  Instruction *instruction_;
+  RiscV32SimpleCsr* csr_;
+  RiscVState* state_;
+  Instruction* instruction_;
 };
 
 constexpr uint32_t kCsrValue1 = 0xaaaa5555;
@@ -137,7 +137,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrw) {
   auto result = state_->csr_set()->GetCsr(kUScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -157,7 +157,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrs) {
   auto result = state_->csr_set()->GetCsr(kUScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -176,7 +176,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrc) {
   auto result = state_->csr_set()->GetCsr(kUScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -195,7 +195,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrwNr) {
   auto result = state_->csr_set()->GetCsr(kUScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
@@ -214,7 +214,7 @@
 TEST_F(ZicsrInstructionsTest, RiscVZiCsrrNw) {
   auto result = state_->csr_set()->GetCsr(kUScratchValue);
   CHECK_OK(result);
-  auto *csr = result.value();
+  auto* csr = result.value();
   CHECK_NE(csr, nullptr);
   csr->Set(kCsrValue1);
   SetRegisterValues<uint32_t>({{kX1, kCsrValue2}, {kX3, 0}});
diff --git a/riscv/test/zfh_encoding.h b/riscv/test/zfh_encoding.h
index cf875fc..9cb724a 100644
--- a/riscv/test/zfh_encoding.h
+++ b/riscv/test/zfh_encoding.h
@@ -58,7 +58,7 @@
   using XRegister = ::mpact::sim::riscv::RV32Register;
   using SelfEncoding = ZfhEncoding<32>;
   static constexpr int kXLen = 32;
-  static constexpr const char *const *kOpcodeNames =
+  static constexpr const char* const* kOpcodeNames =
       ::mpact::sim::riscv::zfh32::kOpcodeNames;
 };
 
@@ -78,7 +78,7 @@
   using XRegister = ::mpact::sim::riscv::RV64Register;
   using SelfEncoding = ZfhEncoding<64>;
   static constexpr int kXLen = 64;
-  static constexpr const char *const *kOpcodeNames =
+  static constexpr const char* const* kOpcodeNames =
       ::mpact::sim::riscv::zfh64::kOpcodeNames;
 };
 
@@ -98,7 +98,7 @@
   using Extractors = typename ZfhTraits<XLen>::Extractors;
   using XRegister = typename ZfhTraits<XLen>::XRegister;
 
-  explicit ZfhEncoding(RiscVState *state)
+  explicit ZfhEncoding(RiscVState* state)
       : state_(state),
         inst_word_(0),
         opcode_(OpcodeEnum::kNone),
@@ -167,24 +167,24 @@
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  ::mpact::sim::generic::PredicateOperandInterface *GetPredicate(
+  ::mpact::sim::generic::PredicateOperandInterface* GetPredicate(
       SlotEnum, int, OpcodeEnum, PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override {
     return nullptr;
   }
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum opcode,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum opcode,
                                               DestOpEnum dest_op, int dest_no,
                                               int latency) override {
     int index = static_cast<int>(dest_op);
@@ -198,7 +198,7 @@
     return (iter->second)(latency);
   }
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum opcode,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum opcode,
                                     SourceOpEnum source_op,
                                     int source_no) override {
     int index = static_cast<int>(source_op);
@@ -217,25 +217,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -243,8 +243,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 }  // namespace mpact::sim::riscv::zfh
 
diff --git a/riscv/test/zfh_encoding_test.cc b/riscv/test/zfh_encoding_test.cc
index 357375a..737f06b 100644
--- a/riscv/test/zfh_encoding_test.cc
+++ b/riscv/test/zfh_encoding_test.cc
@@ -132,11 +132,11 @@
   static constexpr RiscVXlen rvXLen = RiscVXlen::RV32;
   static constexpr int kXLen = 32;
   static constexpr int slot = static_cast<int>(SlotEnum::kRiscv32Zfh);
-  static constexpr const char *const *kSourceOpNames =
+  static constexpr const char* const* kSourceOpNames =
       ::mpact::sim::riscv::zfh32::kSourceOpNames;
-  static constexpr const char *const *kDestOpNames =
+  static constexpr const char* const* kDestOpNames =
       ::mpact::sim::riscv::zfh32::kDestOpNames;
-  static constexpr const char *const *kComplexResourceNames =
+  static constexpr const char* const* kComplexResourceNames =
       ::mpact::sim::riscv::zfh32::kComplexResourceNames;
 };
 
@@ -152,11 +152,11 @@
   static constexpr RiscVXlen rvXLen = RiscVXlen::RV64;
   static constexpr int kXLen = 64;
   static constexpr int slot = static_cast<int>(SlotEnum::kRiscv64Zfh);
-  static constexpr const char *const *kSourceOpNames =
+  static constexpr const char* const* kSourceOpNames =
       ::mpact::sim::riscv::zfh64::kSourceOpNames;
-  static constexpr const char *const *kDestOpNames =
+  static constexpr const char* const* kDestOpNames =
       ::mpact::sim::riscv::zfh64::kDestOpNames;
-  static constexpr const char *const *kComplexResourceNames =
+  static constexpr const char* const* kComplexResourceNames =
       ::mpact::sim::riscv::zfh64::kComplexResourceNames;
 };
 
@@ -189,8 +189,8 @@
   typename ConfigT::OpcodeEnum GetOpcode();
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  ZfhEncoding<ConfigT::kXLen> *enc_;
+  RiscVState* state_;
+  ZfhEncoding<ConfigT::kXLen>* enc_;
   absl::BitGen gen_;
   typename ConfigT::SlotEnum expected_slot_;
 };
@@ -209,7 +209,7 @@
   using XRegister = typename ConfigT::XRegister;
   using XValue = typename ConfigT::XValue;
   XValue register_value = register_index ? absl::Uniform<XValue>(gen_) : 0;
-  XRegister *rs1_reg;
+  XRegister* rs1_reg;
   std::tie(rs1_reg, std::ignore) = state_->GetRegister<XRegister>(
       absl::StrCat("x", static_cast<uint32_t>(register_index)));
   rs1_reg->data_buffer()->template Set<XValue>(0, register_value);
@@ -254,7 +254,7 @@
   using XValue = typename ConfigT::XValue;
   using XRegister = typename ConfigT::XRegister;
   std::unique_ptr<RegisterDestinationOperand<XRegister>> dst(
-      static_cast<RegisterDestinationOperand<XRegister> *>(enc_->GetDestination(
+      static_cast<RegisterDestinationOperand<XRegister>*>(enc_->GetDestination(
           expected_slot_, 0, opcode_enum, ConfigT::DestOpEnum::kRd, 0, 0)));
   std::unique_ptr<DataBuffer> db(dst->CopyDataBuffer());
   return db->template Get<XValue>(0);
@@ -271,7 +271,7 @@
     uint32_t frd_adjustment = static_cast<uint32_t>(frd_index) << frd_offset;
 
     // Set the register value with a test value.
-    RVFpRegister *frd_reg;
+    RVFpRegister* frd_reg;
     std::tie(frd_reg, std::ignore) =
         state_->GetRegister<RVFpRegister>(absl::StrCat("f", frd_index));
     frd_reg->data_buffer()->Set<uint64_t>(0, expected_value);
@@ -279,7 +279,7 @@
     // Parse the instruction and get the destination operand.
     enc_->ParseInstruction(base_instruction | frd_adjustment);
     std::unique_ptr<RegisterDestinationOperand<RVFpRegister>> dst(
-        static_cast<RegisterDestinationOperand<RVFpRegister> *>(
+        static_cast<RegisterDestinationOperand<RVFpRegister>*>(
             enc_->GetDestination(expected_slot_, 0, opcode_enum,
                                  ConfigT::DestOpEnum::kFrd, 0, 0)));
 
@@ -307,7 +307,7 @@
     RegisterValue expected_value = absl::Uniform<RegisterValue>(gen_);
 
     // Set the register value with a test value.
-    RVFpRegister *frs1_reg;
+    RVFpRegister* frs1_reg;
     std::tie(frs1_reg, std::ignore) =
         state_->GetRegister<RVFpRegister>(absl::StrCat("f", frs1_index));
     frs1_reg->data_buffer()->Set<RegisterValue>(0, expected_value);
@@ -365,7 +365,7 @@
 TYPED_TEST_SUITE(ZfhEncodingTest, MyTypes);
 
 TYPED_TEST(ZfhEncodingTest, SourceOperands) {
-  auto &getters = this->enc_->source_op_getters();
+  auto& getters = this->enc_->source_op_getters();
   for (int i = *TypeParam::SourceOpEnum::kNone;
        i < *TypeParam::SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i))
@@ -375,7 +375,7 @@
 }
 
 TYPED_TEST(ZfhEncodingTest, DestOperands) {
-  auto &getters = this->enc_->dest_op_getters();
+  auto& getters = this->enc_->dest_op_getters();
   for (int i = *TypeParam::DestOpEnum::kNone;
        i < *TypeParam::DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i))
@@ -388,7 +388,7 @@
 // them.
 
 TYPED_TEST(ZfhEncodingTest, ComplexResources) {
-  auto &getters = this->enc_->source_op_getters();
+  auto& getters = this->enc_->source_op_getters();
   for (int i = *TypeParam::ComplexResourceEnum::kNone;
        i < *TypeParam::ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i))
@@ -411,7 +411,7 @@
         (sign ? 0x8000'0000 : 0) | ((expected_imm & 0x0000'07FF) << 20);
     this->enc_->ParseInstruction(kFlh | imm_adjustment);
     std::unique_ptr<ImmediateOperand<int32_t>> src(
-        static_cast<ImmediateOperand<int32_t> *>(this->enc_->GetSource(
+        static_cast<ImmediateOperand<int32_t>*>(this->enc_->GetSource(
             this->expected_slot_, 0, TypeParam::OpcodeEnum::kFlh,
             TypeParam::SourceOpEnum::kIImm12, 0)));
     EXPECT_EQ(src->AsInt32(0), expected_imm);
@@ -451,7 +451,7 @@
                               ((expected_imm & 0x0000'07E0) << 20);
     this->enc_->ParseInstruction(kFsh | imm_adjustment);
     std::unique_ptr<ImmediateOperand<int32_t>> src(
-        static_cast<ImmediateOperand<int32_t> *>(this->enc_->GetSource(
+        static_cast<ImmediateOperand<int32_t>*>(this->enc_->GetSource(
             this->expected_slot_, 0, TypeParam::OpcodeEnum::kFsh,
             TypeParam::SourceOpEnum::kSImm12, 0)));
     EXPECT_EQ(src->AsInt32(0), expected_imm);
@@ -491,14 +491,14 @@
   for (uint32_t rd_index = 1; rd_index < 32; ++rd_index) {
     uint32_t rd_adjustment = rd_index << 7;
     XValue expected_value = absl::Uniform<XValue>(this->gen_);
-    XRegister *rd_reg;
+    XRegister* rd_reg;
     std::tie(rd_reg, std::ignore) =
         this->state_->template GetRegister<XRegister>(
             absl::StrCat("x", rd_index));
     rd_reg->data_buffer()->template Set<XValue>(0, expected_value);
     this->enc_->ParseInstruction(kFmvXh | rd_adjustment);
     std::unique_ptr<RegisterDestinationOperand<XRegister>> dst(
-        static_cast<RegisterDestinationOperand<XRegister> *>(
+        static_cast<RegisterDestinationOperand<XRegister>*>(
             this->enc_->GetDestination(this->expected_slot_, 0,
                                        TypeParam::OpcodeEnum::kFmvXh,
                                        TypeParam::DestOpEnum::kRd, 0, 0)));
diff --git a/riscv/test/zvbb_encoding_test.cc b/riscv/test/zvbb_encoding_test.cc
index 64f7be6..7a477c0 100644
--- a/riscv/test/zvbb_encoding_test.cc
+++ b/riscv/test/zvbb_encoding_test.cc
@@ -80,12 +80,12 @@
   }
 
   FlatDemandMemory memory_;
-  RiscVState *state_;
-  ZVBBEncoding *enc_;
+  RiscVState* state_;
+  ZVBBEncoding* enc_;
 };
 
 TEST_F(ZVBBEncodingTest, SourceOperands) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *SourceOpEnum::kNone; i < *SourceOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
                                      << " (" << kSourceOpNames[i] << ")";
@@ -93,7 +93,7 @@
 }
 
 TEST_F(ZVBBEncodingTest, DestOperands) {
-  auto &getters = enc_->dest_op_getters();
+  auto& getters = enc_->dest_op_getters();
   for (int i = *DestOpEnum::kNone; i < *DestOpEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No dest operand for enum value " << i
                                      << " (" << kDestOpNames[i] << ")";
@@ -101,7 +101,7 @@
 }
 
 TEST_F(ZVBBEncodingTest, SimpleResources) {
-  auto &getters = enc_->simple_resource_getters();
+  auto& getters = enc_->simple_resource_getters();
   for (int i = *SimpleResourceEnum::kNone;
        i < *SimpleResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
@@ -110,7 +110,7 @@
 }
 
 TEST_F(ZVBBEncodingTest, ComplexResources) {
-  auto &getters = enc_->source_op_getters();
+  auto& getters = enc_->source_op_getters();
   for (int i = *ComplexResourceEnum::kNone;
        i < *ComplexResourceEnum::kPastMaxValue; ++i) {
     EXPECT_TRUE(getters.contains(i)) << "No source operand for enum value " << i
diff --git a/riscv/zvbb_encoding.cc b/riscv/zvbb_encoding.cc
index 3ac6038..648a4f2 100644
--- a/riscv/zvbb_encoding.cc
+++ b/riscv/zvbb_encoding.cc
@@ -32,7 +32,7 @@
 
 using ::mpact::sim::generic::operator*;  // NOLINT: clang-tidy false positive.
 
-ZVBBEncoding::ZVBBEncoding(RiscVState *state)
+ZVBBEncoding::ZVBBEncoding(RiscVState* state)
     : state_(state),
       inst_word_(0),
       opcode_(OpcodeEnum::kNone),
@@ -85,18 +85,18 @@
   format_ = format;
 }
 
-ResourceOperandInterface *ZVBBEncoding::GetComplexResourceOperand(
+ResourceOperandInterface* ZVBBEncoding::GetComplexResourceOperand(
     SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
     int end) {
   return nullptr;
 }
 
-ResourceOperandInterface *ZVBBEncoding::GetSimpleResourceOperand(
-    SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) {
+ResourceOperandInterface* ZVBBEncoding::GetSimpleResourceOperand(
+    SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec, int end) {
   return nullptr;
 }
 
-DestinationOperandInterface *ZVBBEncoding::GetDestination(SlotEnum, int,
+DestinationOperandInterface* ZVBBEncoding::GetDestination(SlotEnum, int,
                                                           OpcodeEnum opcode,
                                                           DestOpEnum dest_op,
                                                           int dest_no,
@@ -112,7 +112,7 @@
   return (iter->second)(latency);
 }
 
-SourceOperandInterface *ZVBBEncoding::GetSource(SlotEnum, int,
+SourceOperandInterface* ZVBBEncoding::GetSource(SlotEnum, int,
                                                 OpcodeEnum opcode,
                                                 SourceOpEnum source_op,
                                                 int source_no) {
diff --git a/riscv/zvbb_encoding.h b/riscv/zvbb_encoding.h
index bc84053..0330ef7 100644
--- a/riscv/zvbb_encoding.h
+++ b/riscv/zvbb_encoding.h
@@ -36,30 +36,30 @@
 // instructions according to the operand fields in the encoding.
 class ZVBBEncoding : public ZVBBEncodingBase, public RiscVEncodingCommon {
  public:
-  explicit ZVBBEncoding(RiscVState *state);
+  explicit ZVBBEncoding(RiscVState* state);
   ~ZVBBEncoding() override;
 
   void ParseInstruction(uint32_t inst_word);
   OpcodeEnum GetOpcode(SlotEnum, int) override { return opcode_; }
   FormatEnum GetFormat(SlotEnum, int) { return format_; }
 
-  PredicateOperandInterface *GetPredicate(SlotEnum, int, OpcodeEnum,
+  PredicateOperandInterface* GetPredicate(SlotEnum, int, OpcodeEnum,
                                           PredOpEnum) override {
     return nullptr;
   }
 
-  ResourceOperandInterface *GetSimpleResourceOperand(
-      SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec,
+  ResourceOperandInterface* GetSimpleResourceOperand(
+      SlotEnum, int, OpcodeEnum, SimpleResourceVector& resource_vec,
       int end) override;
 
-  ResourceOperandInterface *GetComplexResourceOperand(
+  ResourceOperandInterface* GetComplexResourceOperand(
       SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin,
       int end) override;
 
-  SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
+  SourceOperandInterface* GetSource(SlotEnum, int, OpcodeEnum, SourceOpEnum op,
                                     int source_no) override;
 
-  DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum,
+  DestinationOperandInterface* GetDestination(SlotEnum, int, OpcodeEnum,
                                               DestOpEnum op, int dest_no,
                                               int latency) override;
 
@@ -68,25 +68,25 @@
   }
 
   // Methods inherited from RiscVEncodingCommon.
-  RiscVState *state() const override { return state_; }
-  generic::SimpleResourcePool *resource_pool() override {
+  RiscVState* state() const override { return state_; }
+  generic::SimpleResourcePool* resource_pool() override {
     return resource_pool_;
   }
   uint32_t inst_word() const override { return inst_word_; }
 
-  const SourceOpGetterMap &source_op_getters() { return source_op_getters_; }
-  const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; }
-  const SimpleResourceGetterMap &simple_resource_getters() {
+  const SourceOpGetterMap& source_op_getters() { return source_op_getters_; }
+  const DestOpGetterMap& dest_op_getters() { return dest_op_getters_; }
+  const SimpleResourceGetterMap& simple_resource_getters() {
     return simple_resource_getters_;
   }
-  const ComplexResourceGetterMap &complex_resource_getters() {
+  const ComplexResourceGetterMap& complex_resource_getters() {
     return complex_resource_getters_;
   }
 
  private:
   std::string GetSimpleResourceName(SimpleResourceEnum resource_enum);
 
-  RiscVState *state_;
+  RiscVState* state_;
   uint32_t inst_word_;
   OpcodeEnum opcode_;
   FormatEnum format_;
@@ -94,8 +94,8 @@
   DestOpGetterMap dest_op_getters_;
   SimpleResourceGetterMap simple_resource_getters_;
   ComplexResourceGetterMap complex_resource_getters_;
-  generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr;
-  generic::SimpleResourcePool *resource_pool_ = nullptr;
+  generic::SimpleResourceDelayLine* resource_delay_line_ = nullptr;
+  generic::SimpleResourcePool* resource_pool_ = nullptr;
 };
 
 }  // namespace mpact::sim::riscv::zvbb