// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// RiscV 32 bit G + V instruction decoder.
decoder RiscV32GV {
  namespace mpact::sim::riscv::encoding;
  opcode_enum = "isa32v::OpcodeEnum";
  includes {
    #include "riscv/riscv32gv_decoder.h"
  }
  // Group these instruction groups in the same decoder function.
  RiscV32GV = {RiscVGInst32, RiscVVInst32};
  // Keep this separate (different base format).
  RiscVCInst16;
};

decoder RiscV32GVZB {
  namespace mpact::sim::riscv::isa32gvzb;
  opcode_enum = "isa32gvzb::OpcodeEnum";
  includes {
    #include "riscv/riscv32gvzb_decoder.h"
  }
  // Group these instruction groups in the same decoder function.
  RiscV32GVZB = {RiscVGInst32, RiscVVInst32, RiscVZbaInst32, RiscVZbbInst32,
                 RiscVZbcInst32, RiscVZbsInst32};
  // Keep this separate (different base format).
  RiscVCInst16;
}

#include "riscv32zb.bin_fmt"
#include "riscv32g.bin_fmt"
#include "riscv_vector.bin_fmt"