// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

isa RVM23 {
  namespace mpact::sim::riscv::rvm23;
  slots {
    rvm23;
  }
}

#include "riscv32g.isa"
#include "riscv32zb.isa"
#include "riscv_vector.isa"
#include "riscv_zc.isa"
#include "riscv_zicbop.isa"
#include "riscv_zicond.isa"
#include "riscv_zimop.isa"
#include "riscv_zhintpause.isa"
#include "riscv_zihintntl.isa"

slot rvm23 :
  riscv32i,
  riscv32m,
  riscv32_amo_arithmetic,
  riscv32f,
  riscv32d,
  riscv32_hints,
  zicsr,
  zfencei,
  privileged,
  riscv_vector,
  riscv32_zb,
  riscv32_zicond,
  riscv32_zimop,
  riscv_zcmop,
  riscv_zhintpause,
  riscv_zihintntl,
  riscv_czihintntl,
  riscv_zca32,
  riscv_zcb32,
  riscv_zcf32,
  riscv_zcmp32,
  riscv_zcmt32,
  riscv_zicbop32 {
  default opcode =
    disasm: "Illegal instruction at 0x%(@:08x)",
    semfunc: "&RiscVIllegalInstruction";
}