)]}'
{
  "commit": "dc18e39c1f73a994230f4bc484cfd9cb0481e746",
  "tree": "2e56df16462cb114d746061f1df9a48188a54d29",
  "parents": [
    "f4b42c9e213be2c193d7cc1c32a48efb7d1f1884"
  ],
  "author": {
    "name": "MPACT-Sim team",
    "email": "no-reply@google.com",
    "time": "Wed Mar 11 08:13:38 2026 -0500"
  },
  "committer": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Thu Apr 02 14:45:37 2026 -0500"
  },
  "message": "Fix vlm and vsm to respect vl and vstart\n\nThis change ensures that the vector load-mask (vlm.v) and vector store-mask (vsm.v) instructions correctly adhere to the vector length (vl) and start element (vstart) registers.\n\nPreviously, these instructions used the full byte length of a vector register, regardless of the vl setting. This could lead to incorrect data being loaded or stored.\n\nNow matches Spike vlm.v vsm.v behavior.\n\nPiperOrigin-RevId: 881974860\nChange-Id: Ia0fee4ae809ec95b56f837ffc42d39c148a7e2a0\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "51447967c6f15bdc6a3ace36699172a904934913",
      "old_mode": 33188,
      "old_path": "riscv/riscv_vector_memory_instructions.cc",
      "new_id": "6dacaeff478c96186820316dcb365ed924b796c8",
      "new_mode": 33188,
      "new_path": "riscv/riscv_vector_memory_instructions.cc"
    },
    {
      "type": "modify",
      "old_id": "180d39ca95337e734277041841c09fa86f249501",
      "old_mode": 33188,
      "old_path": "riscv/test/riscv_vector_memory_instructions_test.cc",
      "new_id": "c906d3c86ca753d912ff601e9be87a71fafb39ce",
      "new_mode": 33188,
      "new_path": "riscv/test/riscv_vector_memory_instructions_test.cc"
    }
  ]
}