)]}'
{
  "commit": "df3dfc0ea5a37f89884463de2aba2da13c1a21a0",
  "tree": "6522e869feda3b4d5526225911d04fbfd82ae1ec",
  "parents": [
    "40f07c0126cb93ac596c5ced47b95842411944c7"
  ],
  "author": {
    "name": "MPACT-Sim team",
    "email": "no-reply@google.com",
    "time": "Thu Jan 29 17:07:44 2026 -0600"
  },
  "committer": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Thu Feb 12 10:59:09 2026 -0600"
  },
  "message": "Compensate for instruction increment when writing to counter CSRs\n\n- Derive RiscVPerformanceCounterCsr{High} from RiscVCounterCsr\n- Decrement offset in Set to account for the retiring instruction.\n- High::Set handles carry and propagates offset adjustments for high counter CSRs.\n- Add unit tests for minstret and minstreth to verify write compensation.\n\nPiperOrigin-RevId: 862918613\nChange-Id: I04dc67e1137dc9d82402006411d91a6e3c894423\n",
  "tree_diff": [
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}