)]}'
{
  "commit": "e4f80486918f7689c296c4d56464d3fd8f67957b",
  "tree": "79516ec461f21a69b250d66f66c75c7aaf7cef85",
  "parents": [
    "949e6453f7c8409e47db50d9bd1d3651a1985223"
  ],
  "author": {
    "name": "MPACT-Sim team",
    "email": "no-reply@google.com",
    "time": "Thu Jun 25 17:06:35 2026 -0700"
  },
  "committer": {
    "name": "Build Agent",
    "email": "build@coralpnu.local",
    "time": "Mon Aug 31 09:03:13 2026 -0700"
  },
  "message": "Implement RISC-V Vector Matrix Extension (Zvt) Support\n\nThis CL introduces simulation support for the RISC-V Vector Matrix Extension (Zvt / VME v0.3 draft) within the CoralNPU simulator.\n\nKey Additions:\n- Architectural State: Models the square matrix tile state and implements the unprivileged `mtype` CSR.\n- Instruction Semantics: Adds Zvtbase configuration (`msetmtype`, etc.), tile manipulation (`vtzero`, `vtmv`, `vtle`, `vtse`), and matrix multiply operations (Int8, Uint8, Fp32, Bf16).\n- Simulator Integration: Introduces the `kCoralNPUZvt` architecture, integrating the new instruction decoders and state into the simulation lifecycle.\n\nPiperOrigin-RevId: 938271097\nChange-Id: I819b10e3f16daede817c9c6ab226f61fbb7dbeae\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "50dbdb35031e2821a2e34bc5eb2e0e4e4d579cb8",
      "old_mode": 33188,
      "old_path": "riscv/BUILD",
      "new_id": "b0a7f83e8eb5a48bf94b0146ef9060d32e42dbff",
      "new_mode": 33188,
      "new_path": "riscv/BUILD"
    },
    {
      "type": "modify",
      "old_id": "83a6e87d84b47693020ba7e1c8dda85d90dc5385",
      "old_mode": 33188,
      "old_path": "riscv/riscv_format32.bin_fmt",
      "new_id": "e3c38bbb296b7e64db31cfefe566ba1386500a03",
      "new_mode": 33188,
      "new_path": "riscv/riscv_format32.bin_fmt"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "dde5ca3eada472dc002c909e0c09d1641c9b04c3",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt.bin_fmt"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "db77d9e69bda5db02e9920878d901d03a1bb9659",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt.isa"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "cabe02ba1b6ccd17d465569d45b499e20dee769c",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt_getters.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9a7965b736f7d2089867888f4054d14bab9fd5ee",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt_instructions.cc"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "94779de842cecdffbfb318a9c76f16f52277afef",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt_instructions.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a00168d4d107a7dd12a93ef1f575cdb9c70e96ce",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt_state.cc"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "40a10071a9412ec8ca3ee3374528838aca401143",
      "new_mode": 33188,
      "new_path": "riscv/riscv_zvt_state.h"
    }
  ]
}