)]}'
{
  "commit": "e55a178befefc87dc60f4848295f1bf5f6265455",
  "tree": "5f44695169494da85b25f5d1959064712bab651a",
  "parents": [
    "0847906365add42bf96dae420ce369094ffb692e"
  ],
  "author": {
    "name": "MPACT-Sim team",
    "email": "no-reply@google.com",
    "time": "Thu Sep 03 12:45:07 2026 -0700"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Tue Sep 08 14:13:09 2026 -0700"
  },
  "message": "fix(mpact): fix vector instruction bugs and refine trap logic\n\nRefine RVV implementation in mpact simulator to address several\ninstruction bugs and trap handling mismatches:\n\n1. Trap Handling: Append \"\u0026\u0026 is_interrupt\" to existing trap conditions\n   to resolve PC mismatch in ecall.\n2. Mask Search: Correct the implementation for Vmsbf, Vmsif, and Vmsof\n   mask search instructions.\n3. Bitwise Ops: Update BitwiseMaskBinaryOp for vmand, vmnor, and vmxor.\n4. vsetvli: Fix x0, x0 logic to preserve current_vl when max_vector_length\n   remains unchanged.\n5. Reduction: Fix data truncation in Vwredsum/u by aligning the\n   accumulator with the destination\u0027s widening width.\n6. Vslide:\n   - Introduced is_down flag and corrected Vslideup/down logic.\n   - Refined execution logic for Vslide1up/down single-element slide.\n\n(Backported from mpact-riscv-vsi commit 6dac0e2a09d0845f1499f46ca2d05d24e1306605)\nNote: The VlIndexed fix was omitted from this backport as it was natively fixed in google3 already.\nPiperOrigin-RevId: 975873345\n",
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