diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt
index 8f8c6ff..701a2b3 100644
--- a/riscv/riscv32g.bin_fmt
+++ b/riscv/riscv32g.bin_fmt
@@ -251,12 +251,12 @@
   fcvt_dw  : RType  : func7 == 0b110'1001, rs2 == 0, opcode == 0b101'0011;
   fcvt_dwu : RType  : func7 == 0b110'1001, rs2 == 1, opcode == 0b101'0011;
   // RiscV32 CSR manipulation instructions.
-  csrrw    : IType  : func3 == 0b001, rd != 0,  opcode == 0b111'0011;
+  csrrw    : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd != 0,  opcode == 0b111'0011;
   csrrs    : IType  : func3 == 0b010, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrc    : IType  : func3 == 0b011, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrs_nr : IType  : func3 == 0b010, rs1 != 0, rd == 0, opcode == 0b111'0011;
   csrrc_nr : IType  : func3 == 0b011, rs1 != 0, rd == 0, opcode == 0b111'0011;
-  csrrw_nr : IType  : func3 == 0b001, rd == 0,  opcode == 0b111'0011;
+  csrrw_nr : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd == 0,  opcode == 0b111'0011;
   csrrs_nw : IType  : func3 == 0b010, rs1 == 0, opcode == 0b111'0011;
   csrrc_nw : IType  : func3 == 0b011, rs1 == 0, opcode == 0b111'0011;
   csrrwi   : IType  : func3 == 0b101, rd != 0,  opcode == 0b111'0011;
@@ -267,7 +267,7 @@
   csrrwi_nr: IType  : func3 == 0b101, rd == 0,  opcode == 0b111'0011;
   csrrsi_nw: IType  : func3 == 0b110, rs1 == 0, opcode == 0b111'0011;
   csrrci_nw: IType  : func3 == 0b111, rs1 == 0, opcode == 0b111'0011;
-  unimp    : IType  : func3 == 0b001, rs1 == 0, rd == 0, opcode == 0b111'0011;
+  unimp    : IType  : func3 == 0b001, u_imm12 == 0b1100'0000'0000, rs1 == 0, rd == 0, opcode == 0b111'0011;
   // RiscV32 Privileged instructions.
   uret    : Inst32Format  : bits == 0b000'0000'00010'00000'000'00000, opcode == 0b111'0011;
   sret    : Inst32Format  : bits == 0b000'1000'00010'00000'000'00000, opcode == 0b111'0011;
diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt
index 3c98c51..7e331c0 100644
--- a/riscv/riscv64g.bin_fmt
+++ b/riscv/riscv64g.bin_fmt
@@ -314,12 +314,12 @@
   fmv_xd   : RType  : func7 == 0b111'0001, rs2 == 0b00000, func3 == 0b000, opcode == 0b101'0011;
   fmv_dx   : RType  : func7 == 0b111'1001, rs2 == 0b00000, func3 == 0b000, opcode == 0b101'0011;
   // RiscV32 CSR manipulation instructions.
-  csrrw    : IType  : func3 == 0b001, rd != 0,  opcode == 0b111'0011;
+  csrrw    : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd != 0,  opcode == 0b111'0011;
   csrrs    : IType  : func3 == 0b010, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrc    : IType  : func3 == 0b011, rs1 != 0, rd != 0, opcode == 0b111'0011;
   csrrs_nr : IType  : func3 == 0b010, rs1 != 0, rd == 0, opcode == 0b111'0011;
   csrrc_nr : IType  : func3 == 0b011, rs1 != 0, rd == 0, opcode == 0b111'0011;
-  csrrw_nr : IType  : func3 == 0b001, rd == 0,  opcode == 0b111'0011;
+  csrrw_nr : IType  : func3 == 0b001, u_imm12 != 0b1100'0000'0000, rd == 0,  opcode == 0b111'0011;
   csrrs_nw : IType  : func3 == 0b010, rs1 == 0, opcode == 0b111'0011;
   csrrc_nw : IType  : func3 == 0b011, rs1 == 0, opcode == 0b111'0011;
   csrrwi   : IType  : func3 == 0b101, rd != 0,  opcode == 0b111'0011;
@@ -330,7 +330,7 @@
   csrrwi_nr: IType  : func3 == 0b101, rd == 0,  opcode == 0b111'0011;
   csrrsi_nw: IType  : func3 == 0b110, rs1 == 0, opcode == 0b111'0011;
   csrrci_nw: IType  : func3 == 0b111, rs1 == 0, opcode == 0b111'0011;
-  unimp    : IType  : func3 == 0b001, rd == 0, rs1 == 0, opcode == 0b111'0011;
+  unimp    : IType  : func3 == 0b001, u_imm12 == 0b1100'0000'0000, rd == 0, rs1 == 0, opcode == 0b111'0011;
   // RiscV32 Privileged instructions.
   uret    : Inst32Format  : bits == 0b000'0000'00010'00000'000'00000, opcode == 0b111'0011;
   sret    : Inst32Format  : bits == 0b000'1000'00010'00000'000'00000, opcode == 0b111'0011;
diff --git a/riscv/test/riscv32g_encoding_test.cc b/riscv/test/riscv32g_encoding_test.cc
index b130664..e77f4be 100644
--- a/riscv/test/riscv32g_encoding_test.cc
+++ b/riscv/test/riscv32g_encoding_test.cc
@@ -406,7 +406,7 @@
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32g, 0), OpcodeEnum::kCsrrsiNw);
   enc_->ParseInstruction(kCsrci);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32g, 0), OpcodeEnum::kCsrrciNw);
-  enc_->ParseInstruction(kCsrw);
+  enc_->ParseInstruction(kCsrw | 0xc00'00000);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv32g, 0), OpcodeEnum::kUnimp);
 }
 
diff --git a/riscv/test/riscv64g_encoding_test.cc b/riscv/test/riscv64g_encoding_test.cc
index eedefa7..5380649 100644
--- a/riscv/test/riscv64g_encoding_test.cc
+++ b/riscv/test/riscv64g_encoding_test.cc
@@ -448,6 +448,8 @@
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kCsrrsiNw);
   enc_->ParseInstruction(kCsrci);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kCsrrciNw);
+  enc_->ParseInstruction(kCsrw | 0xc00'00000);
+  EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kUnimp);
 }
 
 TEST_F(RiscV64GEncodingTest, RV64MOpcodes) {
@@ -680,6 +682,8 @@
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kCnop);
   enc_->ParseInstruction(kCebreak);
   EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kCebreak);
+  enc_->ParseInstruction(0x0000);
+  EXPECT_EQ(enc_->GetOpcode(SlotEnum::kRiscv64g, 0), OpcodeEnum::kCunimp);
 }
 
 TEST_F(RiscV64GEncodingTest, RV64PrivilegedOpcodes) {