diff --git a/other/BUILD b/other/BUILD
index 4ed5735..74c5553 100644
--- a/other/BUILD
+++ b/other/BUILD
@@ -20,6 +20,32 @@
 )
 
 cc_library(
+    name = "riscv_simple_state",
+    srcs = [
+        "riscv_simple_state.cc",
+    ],
+    hdrs = [
+        "riscv_simple_state.h",
+        "riscv_register.h",
+    ],
+    deps = [
+        "@com_google_absl//absl/container:flat_hash_map",
+        "@com_google_absl//absl/functional:any_invocable",
+        "@com_google_absl//absl/log",
+        "@com_google_absl//absl/log:check",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/status:statusor",
+        "@com_google_absl//absl/strings",
+        "@com_google_absl//absl/types:any",
+        "@mpact-sim//mpact/sim/generic:arch_state",
+        "@mpact-sim//mpact/sim/generic:core",
+        "@mpact-sim//mpact/sim/generic:instruction",
+        "@mpact-sim//mpact/sim/generic:type_helpers",
+        "@mpact-sim//mpact/sim/util/memory",
+    ],
+)
+
+cc_library(
     name = "rv32i_top",
     srcs = [
         "rv32i_top.cc",
@@ -28,6 +54,7 @@
         "rv32i_top.h",
     ],
     deps = [
+        ":riscv_simple_state",
         "//riscv_full_decoder/solution:riscv32i_decoder",
         "//riscv_isa_decoder/solution:riscv32i_isa",
         "@com_google_absl//absl/functional:bind_front",
@@ -36,7 +63,6 @@
         "@com_google_absl//absl/strings",
         "@mpact-riscv//riscv:riscv32_htif_semihost",
         "@mpact-riscv//riscv:riscv_breakpoint",
-        "@mpact-riscv//riscv:riscv_state",
         "@mpact-sim//mpact/sim/generic:component",
         "@mpact-sim//mpact/sim/generic:core",
         "@mpact-sim//mpact/sim/generic:core_debug_interface",
@@ -51,7 +77,6 @@
         "rv32i_sim.cc",
     ],
     copts = ["-O3"],
-    args = ["other/hello_rv32i.elf"],
     data = [
         "hello_rv32i.elf",
     ],
@@ -69,3 +94,4 @@
         "@mpact-sim//mpact/sim/util/program_loader:elf_loader",
     ],
 )
+
diff --git a/other/riscv_register.h b/other/riscv_register.h
new file mode 100644
index 0000000..3f47190
--- /dev/null
+++ b/other/riscv_register.h
@@ -0,0 +1,45 @@
+// Copyright 2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef MPACT_SIM_CODELABS_OTHER_RISCV_REGISTER_H_
+#define MPACT_SIM_CODELABS_OTHER_RISCV_REGISTER_H_
+
+#include <any>
+#include <string>
+#include <vector>
+
+#include "mpact/sim/generic/data_buffer.h"
+#include "mpact/sim/generic/operand_interface.h"
+#include "mpact/sim/generic/register.h"
+#include "mpact/sim/generic/state_item.h"
+
+// File contains shorthand type definitions for RiscV32G registers.
+
+namespace mpact {
+namespace sim {
+namespace riscv {
+
+class RiscVState;
+
+// The value type of the register must be an unsigned integer type.
+using RV32Register = generic::Register<uint32_t>;
+using RV64Register = generic::Register<uint64_t>;
+
+using RVXRegister = RV32Register;
+
+}  // namespace riscv
+}  // namespace sim
+}  // namespace mpact
+
+#endif // MPACT_SIM_CODELABS_OTHER_RISCV_REGISTER_H_
diff --git a/other/riscv_simple_state.cc b/other/riscv_simple_state.cc
new file mode 100644
index 0000000..3f80efd
--- /dev/null
+++ b/other/riscv_simple_state.cc
@@ -0,0 +1,142 @@
+// Copyright 2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "other/riscv_simple_state.h"
+
+#include <iostream>
+#include <limits>
+#include <string>
+#include <vector>
+
+#include "absl/log/check.h"
+#include "absl/log/log.h"
+#include "mpact/sim/generic/type_helpers.h"
+#include "mpact/sim/util/memory/flat_demand_memory.h"
+#include "other/riscv_register.h"
+
+namespace mpact {
+namespace sim {
+namespace riscv {
+
+RiscVState::RiscVState(absl::string_view id, RiscVXlen xlen,
+                       util::MemoryInterface *memory,
+                       util::AtomicMemoryOpInterface *atomic_memory)
+    : ArchState(id),
+      xlen_(xlen),
+      memory_(memory),
+      atomic_memory_(atomic_memory) {
+  if (memory_ == nullptr) {
+    memory_ = owned_memory_ = new util::FlatDemandMemory(0);
+  }
+
+  DataBuffer *db = nullptr;
+  switch (xlen_) {
+    case RiscVXlen::RV32: {
+      auto *pc32 = GetRegister<RV32Register>(kPcName).first;
+      pc_src_operand_ = pc32->CreateSourceOperand();
+      pc_dst_operand_ = pc32->CreateDestinationOperand(0);
+      pc_ = pc32;
+      db = db_factory()->Allocate<RV32Register::ValueType>(1);
+      db->Set<uint32_t>(0, 0);
+      break;
+    }
+    default:
+      LOG(ERROR) << "Unsupported xlen";
+      return;
+  }
+
+  set_pc_operand(pc_src_operand_);
+  pc_->SetDataBuffer(db);
+  db->DecRef();
+}
+
+RiscVState::~RiscVState() {
+  delete pc_src_operand_;
+  delete pc_dst_operand_;
+  delete owned_memory_;
+}
+
+void RiscVState::LoadMemory(const Instruction *inst, uint64_t address,
+                            DataBuffer *db, Instruction *child_inst,
+                            ReferenceCount *context) {
+  memory_->Load(address, db, child_inst, context);
+}
+
+void RiscVState::LoadMemory(const Instruction *inst, DataBuffer *address_db,
+                            DataBuffer *mask_db, int el_size, DataBuffer *db,
+                            Instruction *child_inst, ReferenceCount *context) {
+  memory_->Load(address_db, mask_db, el_size, db, child_inst, context);
+}
+
+void RiscVState::StoreMemory(const Instruction *inst, uint64_t address,
+                             DataBuffer *db) {
+  memory_->Store(address, db);
+}
+
+void RiscVState::StoreMemory(const Instruction *inst, DataBuffer *address_db,
+                             DataBuffer *mask_db, int el_size, DataBuffer *db) {
+  memory_->Store(address_db, mask_db, el_size, db);
+}
+
+void RiscVState::Fence(const Instruction *inst, int fm, int predecessor,
+                       int successor) {
+  // TODO: Add fence operation once operations have non-zero latency.
+}
+
+void RiscVState::FenceI(const Instruction *inst) {
+  // TODO: Add instruction fence operation when needed.
+}
+
+void RiscVState::ECall(const Instruction *inst) {
+  if (on_ecall_ != nullptr) {
+    auto res = on_ecall_(inst);
+    if (res) return;
+  }
+  std::string where = (inst != nullptr)
+                          ? absl::StrCat(absl::Hex(inst->address()))
+                          : "unknown location";
+
+  LOG(ERROR) << "ECall called without handler at address: " << where;
+  LOG(ERROR) << "Treating as nop";
+}
+
+void RiscVState::EBreak(const Instruction *inst) {
+  for (auto &handler : on_ebreak_) {
+    bool res = handler(inst);
+    if (res) return;
+  }
+  std::string where = (inst != nullptr)
+                          ? absl::StrCat(absl::Hex(inst->address()))
+                          : "unknown location";
+
+  LOG(ERROR) << "EBreak called without handler at address: " << where;
+  LOG(ERROR) << "Treating as nop";
+}
+
+void RiscVState::WFI(const Instruction *inst) {
+  if (on_wfi_ != nullptr) {
+    bool res = on_wfi_(inst);
+    if (res) return;
+  }
+
+  std::string where = (inst != nullptr)
+                          ? absl::StrCat(absl::Hex(inst->address()))
+                          : "unknown location";
+
+  LOG(INFO) << "No handler for wfi: treating as nop: " << where;
+}
+
+}  // namespace riscv
+}  // namespace sim
+}  // namespace mpact
diff --git a/other/riscv_simple_state.h b/other/riscv_simple_state.h
new file mode 100644
index 0000000..07c94e9
--- /dev/null
+++ b/other/riscv_simple_state.h
@@ -0,0 +1,209 @@
+// Copyright 2023 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef MPACT_SIM_CODELABS_OTHER_RISCV_SIMPLE_STATE_H_
+#define MPACT_SIM_CODELABS_OTHER_RISCV_SIMPLE_STATE_H_
+
+#include <cstddef>
+#include <cstdint>
+#include <limits>
+#include <string>
+#include <utility>
+#include <vector>
+
+#include "absl/functional/any_invocable.h"
+#include "absl/status/status.h"
+#include "absl/strings/string_view.h"
+#include "mpact/sim/generic/arch_state.h"
+#include "mpact/sim/generic/data_buffer.h"
+#include "mpact/sim/generic/instruction.h"
+#include "mpact/sim/generic/operand_interface.h"
+#include "mpact/sim/generic/ref_count.h"
+#include "mpact/sim/generic/type_helpers.h"
+#include "mpact/sim/util/memory/flat_demand_memory.h"
+#include "mpact/sim/util/memory/memory_interface.h"
+#include "other/riscv_register.h"
+
+namespace mpact {
+namespace sim {
+namespace riscv {
+
+using ArchState = ::mpact::sim::generic::ArchState;
+using DataBuffer = ::mpact::sim::generic::DataBuffer;
+using Instruction = ::mpact::sim::generic::Instruction;
+using ReferenceCount = ::mpact::sim::generic::ReferenceCount;
+
+// A simple load context class for convenience.
+struct LoadContext : public generic::ReferenceCount {
+  explicit LoadContext(DataBuffer *vdb) : value_db(vdb) {}
+  ~LoadContext() override {
+    if (value_db != nullptr) value_db->DecRef();
+  }
+
+  // Override the base class method so that the data buffer can be DecRef'ed
+  // when the context object is recycled.
+  void OnRefCountIsZero() override {
+    if (value_db != nullptr) value_db->DecRef();
+    value_db = nullptr;
+    // Call the base class method.
+    generic::ReferenceCount::OnRefCountIsZero();
+  }
+  // Data buffers for the value loaded from memory (byte, half, word, etc.).
+  DataBuffer *value_db = nullptr;
+};
+
+// Supported values of Xlen.
+enum class RiscVXlen : uint64_t {
+  RV32 = 0b01,
+  RVUnknown = 4,
+};
+
+// Class that extends ArchState with RiscV specific methods. These methods
+// implement RiscV specific memory operations, memory/IO fencing, system
+// calls and software breakpoints.
+class RiscVState : public ArchState {
+ public:
+  static constexpr char kXregPrefix[] = "x";
+  static constexpr char kVregPrefix[] = "v";
+  static constexpr char kNextPcName[] = "next_pc";
+  static constexpr char kPcName[] = "pc";
+
+  RiscVState(absl::string_view id, RiscVXlen xlen,
+             util::MemoryInterface *memory,
+             util::AtomicMemoryOpInterface *atomic_memory);
+  RiscVState(absl::string_view id, RiscVXlen xlen,
+             util::MemoryInterface *memory)
+      : RiscVState(id, xlen, memory, nullptr) {}
+  RiscVState(absl::string_view id, RiscVXlen xlen)
+      : RiscVState(id, xlen, nullptr, nullptr) {}
+  ~RiscVState() override;
+
+  // Deleted Constructors and operators.
+  RiscVState(const RiscVState &) = delete;
+  RiscVState(RiscVState &&) = delete;
+  RiscVState &operator=(const RiscVState &) = delete;
+  RiscVState &operator=(RiscVState &&) = delete;
+
+  // Return a pair consisting of pointer to the named register and a bool that
+  // is true if the register had to be created, and false if it was found
+  // in the register map (or if nullptr is returned).
+  template <typename RegisterType>
+  std::pair<RegisterType *, bool> GetRegister(absl::string_view name) {
+    // If the register already exists, return a pointer to the register.
+    auto ptr = registers()->find(std::string(name));
+    if (ptr != registers()->end())
+      return std::make_pair(static_cast<RegisterType *>(ptr->second), false);
+    // Create a new register and return a pointer to the object.
+    return std::make_pair(AddRegister<RegisterType>(name), true);
+  }
+
+  // Add register alias.
+  template <typename RegisterType>
+  absl::Status AddRegisterAlias(absl::string_view current_name,
+                                absl::string_view new_name) {
+    auto ptr = registers()->find(std::string(current_name));
+    if (ptr == registers()->end()) {
+      return absl::NotFoundError(
+          absl::StrCat("Register '", current_name, "' does not exist."));
+    }
+    AddRegister(new_name, ptr->second);
+    return absl::OkStatus();
+  }
+
+  // Methods called by instruction semantic functions to load from memory.
+  void LoadMemory(const Instruction *inst, uint64_t address, DataBuffer *db,
+                  Instruction *child_inst, ReferenceCount *context);
+  void LoadMemory(const Instruction *inst, DataBuffer *address_db,
+                  DataBuffer *mask_db, int el_size, DataBuffer *db,
+                  Instruction *child_inst, ReferenceCount *context);
+  // Methods called by instruction semantic functions to store to memory.
+  void StoreMemory(const Instruction *inst, uint64_t address, DataBuffer *db);
+  void StoreMemory(const Instruction *inst, DataBuffer *address_db,
+                   DataBuffer *mask_db, int el_size, DataBuffer *db);
+  // Called by the fence instruction semantic function to signal a fence
+  // operation.
+  void Fence(const Instruction *inst, int fm, int predecessor, int successor);
+  // Synchronize instruction and data streams.
+  void FenceI(const Instruction *inst);
+  // System call.
+  void ECall(const Instruction *inst);
+  // Breakpoint.
+  void EBreak(const Instruction *inst);
+  // WFI
+  void WFI(const Instruction *inst);
+  // Trap.
+  void Trap(bool is_interrupt, uint64_t trap_value, uint64_t exception_code,
+            uint64_t epc, const Instruction *inst);
+  // Add ebreak handler.
+  void AddEbreakHandler(absl::AnyInvocable<bool(const Instruction *)> handler) {
+    on_ebreak_.emplace_back(std::move(handler));
+  }
+
+  // Accessors.
+  void set_memory(util::MemoryInterface *memory) { memory_ = memory; }
+  util::MemoryInterface *memory() const { return memory_; }
+  util::AtomicMemoryOpInterface *atomic_memory() const {
+    return atomic_memory_;
+  }
+
+  // Setters for handlers for ecall, and trap. The handler returns true
+  // if the instruction/event was handled, and false otherwise.
+
+  void set_on_ecall(absl::AnyInvocable<bool(const Instruction *)> callback) {
+    on_ecall_ = std::move(callback);
+  }
+
+  void set_on_wfi(absl::AnyInvocable<bool(const Instruction *)> callback) {
+    on_wfi_ = std::move(callback);
+  }
+
+  void set_on_trap(
+      absl::AnyInvocable<bool(bool /*is_interrupt*/, uint64_t /*trap_value*/,
+                              uint64_t /*exception_code*/, uint64_t /*epc*/,
+                              const Instruction *)>
+          callback) {
+    on_trap_ = std::move(callback);
+  }
+
+  int flen() const { return flen_; }
+  RiscVXlen xlen() const { return xlen_; }
+
+  // Getters for select CSRs.
+
+ private:
+  RiscVXlen xlen_;
+  // Program counter register.
+  generic::RegisterBase *pc_;
+  // Operands used to access pc values generically. Note, the pc value may read
+  // as the address of the next instruction during execution of an instruction,
+  // so the address of the instruction executing should be used instead.
+  generic::SourceOperandInterface *pc_src_operand_ = nullptr;
+  generic::DestinationOperandInterface *pc_dst_operand_ = nullptr;
+  int flen_ = 0;
+  util::FlatDemandMemory *owned_memory_ = nullptr;
+  util::MemoryInterface *memory_ = nullptr;
+  util::AtomicMemoryOpInterface *atomic_memory_ = nullptr;
+  std::vector<absl::AnyInvocable<bool(const Instruction *)>> on_ebreak_;
+  absl::AnyInvocable<bool(const Instruction *)> on_ecall_;
+  absl::AnyInvocable<bool(bool, uint64_t, uint64_t, uint64_t,
+                          const Instruction *)>
+      on_trap_;
+  absl::AnyInvocable<bool(const Instruction *)> on_wfi_;
+};
+
+}  // namespace riscv
+}  // namespace sim
+}  // namespace mpact
+
+#endif // MPACT_SIM_CODELABS_OHTER_RISCV_SIMPLE_STATE_H_
diff --git a/other/rv32i_top.h b/other/rv32i_top.h
index 8db0dbc..641244b 100644
--- a/other/rv32i_top.h
+++ b/other/rv32i_top.h
@@ -27,10 +27,10 @@
 #include "mpact/sim/util/memory/flat_demand_memory.h"
 #include "mpact/sim/util/memory/memory_interface.h"
 #include "mpact/sim/util/memory/memory_watcher.h"
+#include "other/riscv_simple_state.h"
 #include "riscv/riscv32_htif_semihost.h"
 #include "riscv/riscv_breakpoint.h"
 #include "riscv/riscv_register.h"
-#include "riscv/riscv_state.h"
 #include "riscv_full_decoder/solution/riscv32_decoder.h"
 #include "riscv_isa_decoder/solution/riscv32i_enums.h"
 
diff --git a/riscv_full_decoder/BUILD b/riscv_full_decoder/BUILD
index eb61ee6..7a1f1d0 100644
--- a/riscv_full_decoder/BUILD
+++ b/riscv_full_decoder/BUILD
@@ -30,10 +30,10 @@
         "riscv32i_encoding.h",
     ],
     deps = [
+        "//other:riscv_simple_state",
         "//riscv_bin_decoder/solution:riscv32i_bin_fmt",
         "//riscv_isa_decoder/solution:riscv32i_isa",
         "//riscv_semantic_functions/solution:riscv32i",
-        "@mpact-riscv//riscv:riscv_state",
         "@mpact-sim//mpact/sim/generic:arch_state",
         "@mpact-sim//mpact/sim/generic:core",
         "@mpact-sim//mpact/sim/generic:instruction",
diff --git a/riscv_full_decoder/riscv32_decoder.h b/riscv_full_decoder/riscv32_decoder.h
index 410378c..1daa07e 100644
--- a/riscv_full_decoder/riscv32_decoder.h
+++ b/riscv_full_decoder/riscv32_decoder.h
@@ -24,7 +24,7 @@
 #include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/generic/program_error.h"
 #include "mpact/sim/util/memory/memory_interface.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 #include "riscv_full_decoder/riscv32i_encoding.h"
 #include "riscv_isa_decoder/solution/riscv32i_decoder.h"
 
diff --git a/riscv_full_decoder/riscv32i_encoding.cc b/riscv_full_decoder/riscv32i_encoding.cc
index 1ae6a37..0b7109e 100644
--- a/riscv_full_decoder/riscv32i_encoding.cc
+++ b/riscv_full_decoder/riscv32i_encoding.cc
@@ -21,8 +21,8 @@
 #include "mpact/sim/generic/immediate_operand.h"
 #include "mpact/sim/generic/literal_operand.h"
 #include "mpact/sim/generic/operand_interface.h"
-#include "riscv/riscv_register.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
+#include "other/riscv_register.h"
 
 namespace mpact {
 namespace sim {
diff --git a/riscv_full_decoder/riscv32i_encoding.h b/riscv_full_decoder/riscv32i_encoding.h
index 8d00498..93c7762 100644
--- a/riscv_full_decoder/riscv32i_encoding.h
+++ b/riscv_full_decoder/riscv32i_encoding.h
@@ -22,7 +22,7 @@
 
 #include "absl/functional/any_invocable.h"
 #include "mpact/sim/generic/operand_interface.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 #include "riscv_isa_decoder/solution/riscv32i_decoder.h"
 #include "riscv_isa_decoder/solution/riscv32i_enums.h"
 
diff --git a/riscv_full_decoder/solution/BUILD b/riscv_full_decoder/solution/BUILD
index cca8c97..1212c0e 100644
--- a/riscv_full_decoder/solution/BUILD
+++ b/riscv_full_decoder/solution/BUILD
@@ -30,6 +30,7 @@
         "riscv32i_encoding.h",
     ],
     deps = [
+        "//other:riscv_simple_state",
         "//riscv_bin_decoder/solution:riscv32i_bin_fmt",
         "//riscv_isa_decoder/solution:riscv32i_isa",
         "//riscv_semantic_functions/solution:riscv32i",
@@ -38,7 +39,6 @@
         "@com_google_absl//absl/functional:bind_front",
         "@com_google_absl//absl/memory",
         "@com_google_absl//absl/strings",
-        "@mpact-riscv//riscv:riscv_state",
         "@mpact-sim//mpact/sim/generic:arch_state",
         "@mpact-sim//mpact/sim/generic:core",
         "@mpact-sim//mpact/sim/generic:instruction",
diff --git a/riscv_full_decoder/solution/riscv32_decoder.h b/riscv_full_decoder/solution/riscv32_decoder.h
index ccae230..725031c 100644
--- a/riscv_full_decoder/solution/riscv32_decoder.h
+++ b/riscv_full_decoder/solution/riscv32_decoder.h
@@ -23,7 +23,7 @@
 #include "mpact/sim/generic/decoder_interface.h"
 #include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/util/memory/memory_interface.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 #include "riscv_full_decoder/solution/riscv32i_encoding.h"
 #include "riscv_isa_decoder/solution/riscv32i_decoder.h"
 
diff --git a/riscv_full_decoder/solution/riscv32i_encoding.cc b/riscv_full_decoder/solution/riscv32i_encoding.cc
index b0a3ca0..f264b79 100644
--- a/riscv_full_decoder/solution/riscv32i_encoding.cc
+++ b/riscv_full_decoder/solution/riscv32i_encoding.cc
@@ -20,8 +20,8 @@
 #include "mpact/sim/generic/immediate_operand.h"
 #include "mpact/sim/generic/literal_operand.h"
 #include "mpact/sim/generic/operand_interface.h"
-#include "riscv/riscv_register.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_register.h"
+#include "other/riscv_simple_state.h"
 #include "riscv_bin_decoder/solution/riscv32i_bin_decoder.h"
 
 namespace mpact {
@@ -39,16 +39,16 @@
 template <typename RegType>
 inline DestinationOperandInterface *GetRegisterDestinationOp(
     RiscVState *state, const std::string &name, int latency) {
-  auto [reg_ptr, unused] = state->GetRegister<RegType>(name);
-  return reg_ptr->CreateDestinationOperand(latency);
+  auto *reg = state->GetRegister<RegType>(name).first;
+  return reg->CreateDestinationOperand(latency);
 }
 
 template <typename RegType>
 inline DestinationOperandInterface *GetRegisterDestinationOp(
     RiscVState *state, const std::string &name, int latency,
     const std::string &op_name) {
-  auto [reg_ptr, unused] = state->GetRegister<RegType>(name);
-  return reg_ptr->CreateDestinationOperand(latency, op_name);
+  auto *reg = state->GetRegister<RegType>(name).first;
+  return reg->CreateDestinationOperand(latency, op_name);
 }
 
 template <typename RegType>
diff --git a/riscv_full_decoder/solution/riscv32i_encoding.h b/riscv_full_decoder/solution/riscv32i_encoding.h
index 6aaa07c..60e389e 100644
--- a/riscv_full_decoder/solution/riscv32i_encoding.h
+++ b/riscv_full_decoder/solution/riscv32i_encoding.h
@@ -22,7 +22,7 @@
 
 #include "absl/functional/any_invocable.h"
 #include "mpact/sim/generic/operand_interface.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 #include "riscv_isa_decoder/solution/riscv32i_decoder.h"
 #include "riscv_isa_decoder/solution/riscv32i_enums.h"
 
diff --git a/riscv_isa_decoder/riscv32i.isa b/riscv_isa_decoder/riscv32i.isa
index 56f809f..1ecbd1f 100644
--- a/riscv_isa_decoder/riscv32i.isa
+++ b/riscv_isa_decoder/riscv32i.isa
@@ -7,6 +7,9 @@
   slots { riscv32; }
 }
 
+// First disasm fragment is 15 char wide and left justified.
+disasm widths = {-15};
+
 // The RiscV 'I' instructions.
 slot riscv32i {
   // Include file that contains the declarations of the semantic functions for
@@ -25,17 +28,17 @@
     // Add the instruction definition for the instructions in the codelab
     // at the place holders below.
     //
-    // Note Exercise 1 does not involve adding instructions.
+    // Note "Initial Build" does not involve adding instructions.
 
-    // Exercise 2, Add Register-Register ALU Instructions.
+    // Add Register-Register ALU Instructions.
 
-    // Exercise 3, Add ALU Instructions with Immediates.
+    // Add ALU Instructions with Immediates.
 
-    // Exercise 4, Add Branch and Jump-And-Link Instructions.
+    // Add Branch and Jump-And-Link Instructions.
 
-    // Exercise 5, Add Store Instructions.
+    // Add Store Instructions.
 
-    // Exercise 6, Add Load Instructions.
+    // Add Load Instructions.
 
     // End of Excercises.
     fence{: imm12 : },
diff --git a/riscv_isa_decoder/solution/riscv32i.isa b/riscv_isa_decoder/solution/riscv32i.isa
index 5ce4c9e..708a991 100644
--- a/riscv_isa_decoder/solution/riscv32i.isa
+++ b/riscv_isa_decoder/solution/riscv32i.isa
@@ -5,6 +5,8 @@
   slots { riscv32; }
 }
 
+disasm widths = {-15};
+
 // The RiscV 'I' instructions.
 slot riscv32i {
   // Include file that contains the declarations of the semantic functions for
diff --git a/riscv_semantic_functions/BUILD b/riscv_semantic_functions/BUILD
index 97c914a..73c8cb8 100644
--- a/riscv_semantic_functions/BUILD
+++ b/riscv_semantic_functions/BUILD
@@ -31,7 +31,7 @@
     ],
     copts = ["-O3"],
     deps = [
-        "@mpact-riscv//riscv:riscv_state",
+        "//other:riscv_simple_state",
         "@mpact-sim//mpact/sim/generic:arch_state",
         "@mpact-sim//mpact/sim/generic:core",
         "@mpact-sim//mpact/sim/generic:instruction",
diff --git a/riscv_semantic_functions/rv32i_instructions.cc b/riscv_semantic_functions/rv32i_instructions.cc
index 18a746f..d665404 100644
--- a/riscv_semantic_functions/rv32i_instructions.cc
+++ b/riscv_semantic_functions/rv32i_instructions.cc
@@ -20,7 +20,7 @@
 #include "mpact/sim/generic/arch_state.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/instruction_helpers.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 
 namespace mpact {
 namespace sim {
diff --git a/riscv_semantic_functions/solution/BUILD b/riscv_semantic_functions/solution/BUILD
index 97c914a..73c8cb8 100644
--- a/riscv_semantic_functions/solution/BUILD
+++ b/riscv_semantic_functions/solution/BUILD
@@ -31,7 +31,7 @@
     ],
     copts = ["-O3"],
     deps = [
-        "@mpact-riscv//riscv:riscv_state",
+        "//other:riscv_simple_state",
         "@mpact-sim//mpact/sim/generic:arch_state",
         "@mpact-sim//mpact/sim/generic:core",
         "@mpact-sim//mpact/sim/generic:instruction",
diff --git a/riscv_semantic_functions/solution/rv32i_instructions.cc b/riscv_semantic_functions/solution/rv32i_instructions.cc
index 3be4551..696115d 100644
--- a/riscv_semantic_functions/solution/rv32i_instructions.cc
+++ b/riscv_semantic_functions/solution/rv32i_instructions.cc
@@ -21,7 +21,7 @@
 #include "mpact/sim/generic/arch_state.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/instruction_helpers.h"
-#include "riscv/riscv_state.h"
+#include "other/riscv_simple_state.h"
 
 namespace mpact {
 namespace sim {