)]}'
{
  "commit": "0f7ae7b70dd4a7b348681c566e3cff27b5fad16b",
  "tree": "9158cbf0e7a02af76210948c73604ec2bf3e9088",
  "parents": [
    "8e53693215ca5f09eabb652f006b86bdfc384f01"
  ],
  "author": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Fri Sep 06 12:21:17 2024 -0700"
  },
  "committer": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Fri Sep 06 12:51:23 2024 -0700"
  },
  "message": "This adds additional bit manipulation instructions to the RiscV 64 bit simulator.\nIt also factors out some of the encoding initializers so that they can be\nreused across multiple decoders without having to replicate them.\n\nThis also fixes a decoding issue due to underspecified encodings of some vector memory instructions.\n\nPiperOrigin-RevId: 671853580\nChange-Id: I12a9951cf4f74b1334a3c962bee8b89f64aab62f\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "75511a5336b8090ffb5a7994e7dd0458bd22839d",
      "old_mode": 33188,
      "old_path": "mpact/sim/decoder/BUILD",
      "new_id": "d84909f9ffbdf04bdf26efcb019b43cae2815135",
      "new_mode": 33188,
      "new_path": "mpact/sim/decoder/BUILD"
    },
    {
      "type": "modify",
      "old_id": "2c6d8932de2e12c21f6beed539f06eab32dbd156",
      "old_mode": 33188,
      "old_path": "mpact/sim/decoder/opcode.cc",
      "new_id": "bdc6bcf3c7ca1beef86468c3566a6d185ecd3974",
      "new_mode": 33188,
      "new_path": "mpact/sim/decoder/opcode.cc"
    }
  ]
}