)]}'
{
  "commit": "1c3a3d60275bff55db18da012806afddebcbb6ee",
  "tree": "f5734458f225870252a1a724ad3fdb695048b1fd",
  "parents": [
    "38ca080d4ae9f399f0888e3fda3affaec0dc08f9"
  ],
  "author": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Fri Dec 13 15:21:15 2024 -0800"
  },
  "committer": {
    "name": "Tor Jeremiassen",
    "email": "torerik@google.com",
    "time": "Fri Dec 13 15:38:22 2024 -0800"
  },
  "message": "This adds the ability to specify an instruction encoding as specializing that of another.\n\nIn some cases, there is a desire to specialize some instructions with specific operand\nvalues to different mnemonics, even though the decoding of that instruction would match\nthe \"general\" instruction. For instance, in RiscV the \u0027rdcycle t5\u0027 instruction is the same\nas \u0027csrrs t5, zero, cycle\u0027, or even \u0027csrrs t5, cycle\u0027. The new capability allows this\nto be expressed in the bin_fmt file as:\n\n  rdcycle : specializes csrrs_nw : u_imm12 \u003d\u003d 0xc00;\n\nWhich means that rdcycle has the same encoding as csrrs_nw, with one added constraint.\nThe generated decoder will now contain code to check for rdcycle whenever a csrrs_nw\ninstruction is matched, and prefer to return that opcode as opposed to the more generic\ncsrrs_nw opcode. Multiple such specializations can be added for an opcode. There is no\norder in which they are considered, except that the base opcode will be considered last.\n\nPiperOrigin-RevId: 706018484\nChange-Id: I2a5393a33d96ab3023b04defef24dd83111f527c\n",
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