tree f5734458f225870252a1a724ad3fdb695048b1fd
parent 38ca080d4ae9f399f0888e3fda3affaec0dc08f9
author Tor Jeremiassen <torerik@google.com> 1734132075 -0800
committer Tor Jeremiassen <torerik@google.com> 1734133102 -0800

This adds the ability to specify an instruction encoding as specializing that of another.

In some cases, there is a desire to specialize some instructions with specific operand
values to different mnemonics, even though the decoding of that instruction would match
the "general" instruction. For instance, in RiscV the 'rdcycle t5' instruction is the same
as 'csrrs t5, zero, cycle', or even 'csrrs t5, cycle'. The new capability allows this
to be expressed in the bin_fmt file as:

  rdcycle : specializes csrrs_nw : u_imm12 == 0xc00;

Which means that rdcycle has the same encoding as csrrs_nw, with one added constraint.
The generated decoder will now contain code to check for rdcycle whenever a csrrs_nw
instruction is matched, and prefer to return that opcode as opposed to the more generic
csrrs_nw opcode. Multiple such specializations can be added for an opcode. There is no
order in which they are considered, except that the base opcode will be considered last.

PiperOrigin-RevId: 706018484
Change-Id: I2a5393a33d96ab3023b04defef24dd83111f527c