diff --git a/mpact/sim/util/gdbserver/gdbserver.cc b/mpact/sim/util/gdbserver/gdbserver.cc
index 7cf1dbf..173c75c 100644
--- a/mpact/sim/util/gdbserver/gdbserver.cc
+++ b/mpact/sim/util/gdbserver/gdbserver.cc
@@ -961,23 +961,41 @@
     return SendError(absl::StrCat("Register not found: ", register_number));
   }
   const std::string& register_name = it->second;
-  auto result = core_debug_interfaces_[thread_index]->GetRegisterDataBuffer(
-      register_name);
-  if (!result.ok()) {
-    return SendError(result.status().message());
+  auto reg_bitsize_it = reg_bitsize_map_.find(register_number);
+  int byte_size = 0;
+  if (reg_bitsize_it != reg_bitsize_map_.end()) {
+    byte_size = reg_bitsize_it->second / 8;
   }
-  std::string response;
-  int bitsize = result.value()->size<uint8_t>() * 8;
-  for (const auto& byte : result.value()->Get<uint8_t>()) {
-    absl::StrAppend(&response, absl::Hex(byte, absl::kZeroPad2));
-  }
-  if (reg_bitsize_map_.contains(register_number) &&
-      reg_bitsize_map_[register_number] > bitsize) {
-    for (int i = 0; i < (reg_bitsize_map_[register_number] - bitsize); i += 8) {
+  if ((byte_size != 0) && (byte_size <= sizeof(uint64_t))) {
+    // Read using the standard read register function.
+    auto result =
+        core_debug_interfaces_[thread_index]->ReadRegister(register_name);
+    if (!result.ok()) {
+      return SendError(result.status().message());
+    }
+    uint64_t value = result.value();
+    uint8_t* bytes = reinterpret_cast<uint8_t*>(&value);
+    std::string response;
+    for (int i = 0; i < byte_size; ++i) {
+      absl::StrAppend(&response, absl::Hex(bytes[i], absl::kZeroPad2));
+    }
+    Respond(response);
+  } else {
+    auto result = core_debug_interfaces_[thread_index]->GetRegisterDataBuffer(
+        register_name);
+    if (!result.ok()) {
+      return SendError(result.status().message());
+    }
+    std::string response;
+    int db_size = result.value()->size<uint8_t>();
+    for (const auto& byte : result.value()->Get<uint8_t>()) {
+      absl::StrAppend(&response, absl::Hex(byte, absl::kZeroPad2));
+    }
+    for (int i = db_size; i < byte_size; ++i) {
       absl::StrAppend(&response, "00");
     }
+    Respond(response);
   }
-  Respond(response);
 }
 
 void GdbServer::GdbWriteRegister(int thread_id,
diff --git a/mpact/sim/util/gdbserver/test/gdbserver_test.cc b/mpact/sim/util/gdbserver/test/gdbserver_test.cc
index 275882f..15a8d87 100644
--- a/mpact/sim/util/gdbserver/test/gdbserver_test.cc
+++ b/mpact/sim/util/gdbserver/test/gdbserver_test.cc
@@ -125,7 +125,82 @@
     return 64 / 8;
   }
   std::string_view GetLLDBHostInfo() const override { return ""; }
-  std::string_view GetGdbTargetXml() const override { return ""; }
+  std::string_view GetGdbTargetXml() const override {
+    return "<?xml version=\"1.0\"?>\n"
+           "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">\n"
+           "<target version=\"1.0\">\n"
+           "  <architecture>testarch</architecture>\n"
+           "  <reg bitsize=\"64\" name=\"pc\" regnum=\"32\" />\n"
+           "  <feature name=\"org.gnu.gdb.testarch.cpu\">\n"
+           "    <reg bitsize=\"64\" name=\"x0\" regnum=\"0\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x1\" regnum=\"1\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x2\" regnum=\"2\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x3\" regnum=\"3\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x4\" regnum=\"4\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x5\" regnum=\"5\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x6\" regnum=\"6\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x7\" regnum=\"7\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x8\" regnum=\"8\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x9\" regnum=\"9\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x10\" regnum=\"10\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x11\" regnum=\"11\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x12\" regnum=\"12\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x13\" regnum=\"13\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x14\" regnum=\"14\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x15\" regnum=\"15\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x16\" regnum=\"16\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x17\" regnum=\"17\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x18\" regnum=\"18\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x19\" regnum=\"19\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x20\" regnum=\"20\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x21\" regnum=\"21\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x22\" regnum=\"22\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x23\" regnum=\"23\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x24\" regnum=\"24\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x25\" regnum=\"25\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x26\" regnum=\"26\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x27\" regnum=\"27\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x28\" regnum=\"28\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x29\" regnum=\"29\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x30\" regnum=\"30\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"x31\" regnum=\"31\" "
+           "type=\"uint64\"/>\n"
+           "    <reg bitsize=\"64\" name=\"pc\" regnum=\"32\" "
+           "type=\"code_ptr\"/>\n"
+           "  </feature>\n"
+           "</target>\n";
+  }
 
  private:
   DebugRegisterMap debug_register_map_;
@@ -401,7 +476,7 @@
   memcpy(db->raw_ptr(), &reg_val, 8);
 
   // Reading register 32 ('pc', hex '20').
-  EXPECT_CALL(mock_core_, GetRegisterDataBuffer("pc")).WillOnce(Return(db));
+  EXPECT_CALL(mock_core_, ReadRegister("pc")).WillOnce(Return(0x1234));
 
   std::thread server_fiber([&]() { gdb_server_->Connect(port); });
 
diff --git a/mpact/sim/util/memory/flat_demand_memory.cc b/mpact/sim/util/memory/flat_demand_memory.cc
index c53d952..841d85f 100644
--- a/mpact/sim/util/memory/flat_demand_memory.cc
+++ b/mpact/sim/util/memory/flat_demand_memory.cc
@@ -50,10 +50,9 @@
   int size_in_units = db->size<uint8_t>() >> addressable_unit_shift_;
   uint64_t high = address + size_in_units;
   if (address < base_address_ || high > max_address_) [[unlikely]] {
-    LOG(ERROR) << absl::StrFormat(
+    LOG(WARNING) << absl::StrFormat(
         "Load access [%x, %x] out of bounds [%x, %x]\n", address, high,
         base_address_, max_address_);
-    ABSL_HARDENING_ASSERT(false);
   }
   if (size_in_units <= 0) [[unlikely]] {
     LOG(ERROR) << absl::StrFormat("Size in units %d is not positive\n",