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mpact / collateral / 459de9db50c760a8f7c61a8227f62262c29e6a29 / . / tpu_recision / third_party / llvm / llvm / test / CodeGen / GoogleTPU / vnsel.ll
blob: 1c94d474ef2b9811d94a8be6ae51e22482707377 [file] [log] [blame]
; RUN: llc < %s -mcpu=tensorcore-vf -asm-verbose=false -disable-cgp | FileCheck %s --check-prefix=CHECK-VF
; RUN: llc < %s -mcpu=tensorcore-jf -asm-verbose=false -disable-cgp | FileCheck %s
; RUN: llc < %s -mcpu=tensorcore-pf -asm-verbose=false -disable-cgp | FileCheck %s
; REQUIRES: tpu
target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
target triple = "googletpu"
; CHECK-VF: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x i32> @vselrr_i32(<1024 x i1> %mask, <1024 x i32> %x, <1024 x i32> %y) {
%r = select <1024 x i1> %mask, <1024 x i32> %x, <1024 x i32> %y
ret <1024 x i32> %r
}
; CHECK-VF: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x float> @vselrr_float(<1024 x i1> %mask, <1024 x float> %x, <1024 x float> %y) {
%r = select <1024 x i1> %mask, <1024 x float> %x, <1024 x float> %y
ret <1024 x float> %r
}
; CHECK-VF: v{{[0-9]+}} = vnsel vm{{[0-9]+}}, $0x2a, v{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vimm.s32 $0x2a
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x i32> @vnselri_i32(<1024 x i1> %mask, <1024 x i32> %x) {
%y0 = insertelement <1024 x i32> undef, i32 42, i32 0
%y = shufflevector <1024 x i32> %y0, <1024 x i32> undef, <1024 x i32> zeroinitializer
%r = select <1024 x i1> %mask, <1024 x i32> %x, <1024 x i32> %y
ret <1024 x i32> %r
}
; CHECK-VF: v{{[0-9]+}} = vnsel vm{{[0-9]+}}, $0x42280000, v{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vimm.f32 $42.0
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x float> @vnselri_float(<1024 x i1> %mask, <1024 x float> %x) {
%y0 = insertelement <1024 x float> undef, float 42.0, i32 0
%y = shufflevector <1024 x float> %y0, <1024 x float> undef, <1024 x i32> zeroinitializer
%r = select <1024 x i1> %mask, <1024 x float> %x, <1024 x float> %y
ret <1024 x float> %r
}
; CHECK-VF: v{{[0-9]+}} = vnsel vm{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vmov s{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x i32> @vnselrs_i32(<1024 x i1> %mask, <1024 x i32> %x, i32 %s) {
%y0 = insertelement <1024 x i32> undef, i32 %s, i32 0
%y = shufflevector <1024 x i32> %y0, <1024 x i32> undef, <1024 x i32> zeroinitializer
%r = select <1024 x i1> %mask, <1024 x i32> %x, <1024 x i32> %y
ret <1024 x i32> %r
}
; CHECK-VF: v{{[0-9]+}} = vnsel vm{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vmov s{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x float> @vnselrs_float(<1024 x i1> %mask, <1024 x float> %x, float %s) {
%y0 = insertelement <1024 x float> undef, float %s, i32 0
%y = shufflevector <1024 x float> %y0, <1024 x float> undef, <1024 x i32> zeroinitializer
%r = select <1024 x i1> %mask, <1024 x float> %x, <1024 x float> %y
ret <1024 x float> %r
}
; CHECK-VF: v{{[0-9]+}} = vnsel vm{{[0-9]+}}, $0x2a, v{{[0-9]+}}
; CHECK: v{{[0-9]+}} = vimm.s32 $0x2a
; CHECK: v{{[0-9]+}} = vsel vm{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}};
define <1024 x i32> @vnselri_i32_1(<1024 x i1> %mask, <1024 x i32> %x) {
%r = select <1024 x i1> %mask, <1024 x i32> %x, <1024 x
i32> <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42 , i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42 , i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42,
i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
ret <1024 x i32> %r
}