Fixed issue where some registers weren't given the right type. Templating the function to obtain the registers alleviates this. PiperOrigin-RevId: 712965975 Change-Id: Ia88fdf5d84576aac6307ab55c13b34820dac07ea

diff --git a/riscv/BUILD b/riscv/BUILD
index 5167147..cd96797 100644
--- a/riscv/BUILD
+++ b/riscv/BUILD

@@ -268,6 +268,7 @@
         "@com_google_absl//absl/status",
         "@com_google_absl//absl/strings",
         "@com_google_absl//absl/strings:str_format",
+        "@com_google_absl//absl/types:span",
         "@com_google_mpact-sim//mpact/sim/generic:arch_state",
         "@com_google_mpact-sim//mpact/sim/generic:core",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",

diff --git a/riscv/riscv_vector_permute_instructions.cc b/riscv/riscv_vector_permute_instructions.cc
index 9192c88..bf993d7 100644
--- a/riscv/riscv_vector_permute_instructions.cc
+++ b/riscv/riscv_vector_permute_instructions.cc

@@ -15,8 +15,11 @@
 #include "riscv/riscv_vector_permute_instructions.h"
 
 #include <algorithm>
+#include <cstdint>
 
 #include "absl/log/log.h"
+#include "absl/strings/str_cat.h"
+#include "absl/types/span.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/instruction.h"
 #include "riscv/riscv_register.h"

diff --git a/riscv/test/riscv_fp_test_base.h b/riscv/test/riscv_fp_test_base.h
index fc653da..f427a52 100644
--- a/riscv/test/riscv_fp_test_base.h
+++ b/riscv/test/riscv_fp_test_base.h

@@ -332,24 +332,26 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
+  template <typename T>
   void AppendRegisterOperands(Instruction *inst,
                               const std::vector<std::string> &sources,
                               const std::vector<std::string> &destinations) {
     for (auto &reg_name : sources) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto *reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendSource(reg->CreateSourceOperand());
     }
     for (auto &reg_name : destinations) {
-      auto *reg = state_->GetRegister<RV32Register>(reg_name).first;
+      auto *reg = state_->GetRegister<T>(reg_name).first;
       inst->AppendDestination(reg->CreateDestinationOperand(0));
     }
   }
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
+  template <typename T>
   void AppendRegisterOperands(const std::vector<std::string> &sources,
                               const std::vector<std::string> &destinations) {
-    AppendRegisterOperands(instruction_, sources, destinations);
+    AppendRegisterOperands<T>(instruction_, sources, destinations);
   }
 
   // named register and sets it to the corresponding value.
@@ -437,7 +439,8 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[1], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name}, {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     using LhsInt = typename FPTypeInfo<LHS>::IntType;
     *reinterpret_cast<LhsInt *>(&lhs_span[0]) = FPTypeInfo<LHS>::kQNaN;
@@ -488,7 +491,8 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[1], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
@@ -553,7 +557,8 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[2], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kR2Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name, kR2Name}, {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
@@ -615,7 +620,8 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[2], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kR2Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name, kR2Name}, {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);
@@ -684,7 +690,9 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[3], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kR2Name, kR3Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name, kR2Name, kR3Name},
+                                         {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     FillArrayWithRandomFPValues<LHS>(lhs_span);
     FillArrayWithRandomFPValues<MHS>(mhs_span);
     FillArrayWithRandomFPValues<RHS>(rhs_span);
@@ -745,7 +753,9 @@
     const std::string kRdName = absl::StrCat(reg_prefixes[3], 5);
     // This is used for the rounding mode operand.
     const std::string kRmName = absl::StrCat("x", 10);
-    AppendRegisterOperands({kR1Name, kR2Name, kR3Name, kRmName}, {kRdName});
+    AppendRegisterOperands<RVFpRegister>({kR1Name, kR2Name, kR3Name},
+                                         {kRdName});
+    AppendRegisterOperands<RV32Register>({kRmName}, {});
     auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     FillArrayWithRandomFPValues<LHS>(lhs_span);

diff --git a/riscv/test/riscv_vector_fp_compare_instructions_test.cc b/riscv/test/riscv_vector_fp_compare_instructions_test.cc
index 87648ef..7ef13c2 100644
--- a/riscv/test/riscv_vector_fp_compare_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_compare_instructions_test.cc

@@ -228,7 +228,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {});
-    AppendRegisterOperands({kFs1Name}, {});
+    AppendRegisterOperands<Fs1>({kFs1Name}, {});
     AppendVectorRegisterOperands({kVmask}, {kVd});
     // Initialize input values.
     FillArrayWithRandomValues<Vs2>(vs2_span);

diff --git a/riscv/test/riscv_vector_fp_instructions_test.cc b/riscv/test/riscv_vector_fp_instructions_test.cc
index 0aa2d50..c23519c 100644
--- a/riscv/test/riscv_vector_fp_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_instructions_test.cc

@@ -330,7 +330,7 @@
     auto vs2_span = Span<Vs2>(vs2_value);
     auto vd_span = Span<Vd>(vd_value);
     AppendVectorRegisterOperands({kVs2}, {kVd});
-    AppendRegisterOperands({kFs1Name}, {});
+    AppendRegisterOperands<RVFpRegister>({kFs1Name}, {});
     AppendVectorRegisterOperands({kVd, kVmask}, {kVd});
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});

diff --git a/riscv/test/riscv_vector_fp_test_utilities.h b/riscv/test/riscv_vector_fp_test_utilities.h
index 96c8120..9ab9d3a 100644
--- a/riscv/test/riscv_vector_fp_test_utilities.h
+++ b/riscv/test/riscv_vector_fp_test_utilities.h

@@ -628,7 +628,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {kVd});
-    AppendRegisterOperands({kFs1Name}, {});
+    AppendRegisterOperands<Fs1>({kFs1Name}, {});
     auto *flag_op = rv_fp_->fflags()->CreateSetDestinationOperand(0, "fflags");
     instruction_->AppendDestination(flag_op);
     AppendVectorRegisterOperands({kVmask}, {});
@@ -797,7 +797,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {kVd});
-    AppendRegisterOperands({kFs1Name}, {});
+    AppendRegisterOperands<Fs1>({kFs1Name}, {});
     AppendVectorRegisterOperands({kVmask}, {});
     SetVectorRegisterValues<uint8_t>(
         {{kVmaskName, Span<const uint8_t>(kA5Mask)}});

diff --git a/riscv/test/riscv_vector_fp_unary_instructions_test.cc b/riscv/test/riscv_vector_fp_unary_instructions_test.cc
index 6fb2b30..e3ee470 100644
--- a/riscv/test/riscv_vector_fp_unary_instructions_test.cc
+++ b/riscv/test/riscv_vector_fp_unary_instructions_test.cc

@@ -610,7 +610,7 @@
 // Test vfmv.f.s instruction - move element 0 to scalar fp register.
 TEST_F(RiscVFPUnaryInstructionsTest, VfmvToScalar) {
   SetSemanticFunction(&Vfmvfs);
-  AppendRegisterOperands({}, {kFs1Name});
+  AppendRegisterOperands<RVFpRegister>({}, {kFs1Name});
   AppendVectorRegisterOperands({kVs2}, {});
   for (int byte_sew : {1, 2, 4, 8}) {
     int vlen = kVectorLengthInBytes / byte_sew;
@@ -650,7 +650,7 @@
 // Test vfmv.f.s instruction - move scalar fp register to element 0.
 TEST_F(RiscVFPUnaryInstructionsTest, VfmvFromScalar) {
   SetSemanticFunction(&Vfmvsf);
-  AppendRegisterOperands({kFs1Name}, {});
+  AppendRegisterOperands<RVFpRegister>({kFs1Name}, {});
   AppendVectorRegisterOperands({}, {kVd});
   for (int byte_sew : {1, 2, 4, 8}) {
     int vlen = kVectorLengthInBytes / byte_sew;

diff --git a/riscv/test/riscv_vector_instructions_test_base.h b/riscv/test/riscv_vector_instructions_test_base.h
index a243929..7ba43ce 100644
--- a/riscv/test/riscv_vector_instructions_test_base.h
+++ b/riscv/test/riscv_vector_instructions_test_base.h

@@ -180,6 +180,7 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the given instruction.
+  template <typename T>
   void AppendRegisterOperands(Instruction *inst,
                               const std::vector<std::string> &sources,
                               const std::vector<std::string> &destinations) {
@@ -195,9 +196,10 @@
 
   // Creates source and destination scalar register operands for the registers
   // named in the two vectors and append them to the default instruction.
+  template <typename T>
   void AppendRegisterOperands(const std::vector<std::string> &sources,
                               const std::vector<std::string> &destinations) {
-    AppendRegisterOperands(instruction_, sources, destinations);
+    AppendRegisterOperands<T>(instruction_, sources, destinations);
   }
 
   // Returns the value of the named vector register.
@@ -564,7 +566,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {});
-    AppendRegisterOperands({kRs1Name}, {});
+    AppendRegisterOperands<Rs1>({kRs1Name}, {});
     AppendVectorRegisterOperands({kVmask}, {kVd});
     // Initialize input values.
     FillArrayWithRandomValues<Vs2>(vs2_span);
@@ -833,7 +835,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {});
-    AppendRegisterOperands({kRs1Name}, {});
+    AppendRegisterOperands<Rs1>({kRs1Name}, {});
     AppendVectorRegisterOperands({kVd, kVmask}, {kVd});
     // Initialize input values.
     FillArrayWithRandomValues<Vd>(vd_span);
@@ -1090,7 +1092,7 @@
     Vs2 vs2_value[vs2_size * 8];
     auto vs2_span = Span<Vs2>(vs2_value);
     AppendVectorRegisterOperands({kVs2}, {});
-    AppendRegisterOperands({kRs1Name}, {});
+    AppendRegisterOperands<Rs1>({kRs1Name}, {});
     AppendVectorRegisterOperands({kVmask}, {kVd});
     // Initialize input values.
     FillArrayWithRandomValues<Vs2>(vs2_span);

diff --git a/riscv/test/riscv_vector_permute_instructions_test.cc b/riscv/test/riscv_vector_permute_instructions_test.cc
index 5cebdab..d649d59 100644
--- a/riscv/test/riscv_vector_permute_instructions_test.cc
+++ b/riscv/test/riscv_vector_permute_instructions_test.cc

@@ -14,6 +14,8 @@
 
 #include "riscv/riscv_vector_permute_instructions.h"
 
+#include <cstdint>
+
 #include "absl/random/random.h"
 #include "googlemock/include/gmock/gmock.h"
 #include "mpact/sim/generic/instruction.h"
@@ -208,7 +210,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, VrgatherVS8) {
   SetSemanticFunction(&Vrgather);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   VrgatherVSHelper<uint8_t>(this, instruction_);
 }
@@ -216,7 +218,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, VrgatherVS16) {
   SetSemanticFunction(&Vrgather);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   VrgatherVSHelper<uint16_t>(this, instruction_);
 }
@@ -224,7 +226,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, VrgatherVS32) {
   SetSemanticFunction(&Vrgather);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   VrgatherVSHelper<uint32_t>(this, instruction_);
 }
@@ -232,7 +234,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, VrgatherVS64) {
   SetSemanticFunction(&Vrgather);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   VrgatherVSHelper<uint64_t>(this, instruction_);
 }
@@ -347,7 +349,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslideup8) {
   SetSemanticFunction(&Vslideup);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint8_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -355,7 +357,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslideup16) {
   SetSemanticFunction(&Vslideup);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint16_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -363,7 +365,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslideup32) {
   SetSemanticFunction(&Vslideup);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint32_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -371,7 +373,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslideup64) {
   SetSemanticFunction(&Vslideup);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint64_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -380,7 +382,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslidedown8) {
   SetSemanticFunction(&Vslidedown);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint8_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -388,7 +390,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslidedown16) {
   SetSemanticFunction(&Vslidedown);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint16_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -396,7 +398,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslidedown32) {
   SetSemanticFunction(&Vslidedown);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint32_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -404,7 +406,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslidedown64) {
   SetSemanticFunction(&Vslidedown);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   SlideHelper<uint64_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -486,7 +488,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1up8) {
   SetSemanticFunction(&Vslide1up);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint8_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -494,7 +496,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1up16) {
   SetSemanticFunction(&Vslide1up);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint16_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -502,7 +504,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1up32) {
   SetSemanticFunction(&Vslide1up);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint32_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -510,7 +512,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1up64) {
   SetSemanticFunction(&Vslide1up);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint64_t>(this, instruction_, /*is_slide_up*/ true);
 }
@@ -518,7 +520,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1down8) {
   SetSemanticFunction(&Vslide1down);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint8_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -526,7 +528,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1down16) {
   SetSemanticFunction(&Vslide1down);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint16_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -534,7 +536,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1down32) {
   SetSemanticFunction(&Vslide1down);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint32_t>(this, instruction_, /*is_slide_up*/ false);
 }
@@ -542,7 +544,7 @@
 TEST_F(RiscVVectorPermuteInstructionsTest, Vslide1down64) {
   SetSemanticFunction(&Vslide1down);
   AppendVectorRegisterOperands({kVs2}, {});
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({kVmask}, {kVd});
   Slide1Helper<uint64_t>(this, instruction_, /*is_slide_up*/ false);
 }

diff --git a/riscv/test/riscv_vector_unary_instructions_test.cc b/riscv/test/riscv_vector_unary_instructions_test.cc
index 8ff9f2c..84953ea 100644
--- a/riscv/test/riscv_vector_unary_instructions_test.cc
+++ b/riscv/test/riscv_vector_unary_instructions_test.cc

@@ -101,7 +101,7 @@
 // Test move vector element 0 to scalar register.
 TEST_F(RiscVVectorUnaryInstructionsTest, VmvToScalar) {
   SetSemanticFunction(&VmvToScalar);
-  AppendRegisterOperands({}, {kRs1Name});
+  AppendRegisterOperands<RV32Register>({}, {kRs1Name});
   AppendVectorRegisterOperands({kVs2}, {});
   for (int byte_sew : {1, 2, 4, 8}) {
     int vlen = kVectorLengthInBytes / byte_sew;
@@ -151,7 +151,7 @@
 // Test move scalar to vector element 0.
 TEST_F(RiscVVectorUnaryInstructionsTest, VmvFromScalar) {
   SetSemanticFunction(&VmvFromScalar);
-  AppendRegisterOperands({kRs1Name}, {});
+  AppendRegisterOperands<RV32Register>({kRs1Name}, {});
   AppendVectorRegisterOperands({}, {kVs2});
   for (int byte_sew : {1, 2, 4, 8}) {
     int vlen = kVectorLengthInBytes / byte_sew;
@@ -219,7 +219,7 @@
   uint32_t vtype = (kSewSettingsByByteSize[1] << 3) | kLmulSettingByLogSize[7];
   SetSemanticFunction(&Vcpop);
   AppendVectorRegisterOperands({kVs2, kVmask}, {});
-  AppendRegisterOperands({}, {kRdName});
+  AppendRegisterOperands<RV32Register>({}, {kRdName});
   for (int vlen : {1, 8, 32, 48, 127, 200}) {
     ConfigureVectorUnit(vtype, vlen);
     // All 1s for mask and vector.
@@ -240,7 +240,7 @@
 TEST_F(RiscVVectorUnaryInstructionsTest, Vfirst) {
   SetSemanticFunction(&Vfirst);
   AppendVectorRegisterOperands({kVs2, kVmask}, {});
-  AppendRegisterOperands({}, {kRdName});
+  AppendRegisterOperands<RV32Register>({}, {kRdName});
   uint8_t reg_value[kVectorLengthInBytes];
   // Set vtype to byte vector, and vector lmul to 8.
   uint32_t vtype = (kSewSettingsByByteSize[1] << 3) | kLmulSettingByLogSize[7];