Adding cache prefetch instructions (as no-ops). Fixed some encoding issues. PiperOrigin-RevId: 693797021 Change-Id: I1432a4c6d9ceeca67bc384bf3c3dc95713ac3e10
diff --git a/riscv/BUILD b/riscv/BUILD index 276a42e..da0d359 100644 --- a/riscv/BUILD +++ b/riscv/BUILD
@@ -258,6 +258,7 @@ srcs = [ "riscv_zc_instructions.cc", "riscv_zhintpause_instructions.cc", + "riscv_zicbop_instructions.cc", "riscv_zicond_instructions.cc", "riscv_zihintntl_instructions.cc", "riscv_zimop_instructions.cc", @@ -265,6 +266,7 @@ hdrs = [ "riscv_zc_instructions.h", "riscv_zhintpause_instructions.h", + "riscv_zicbop_instructions.h", "riscv_zicond_instructions.h", "riscv_zihintntl_instructions.h", "riscv_zimop_instructions.h", @@ -377,6 +379,7 @@ "riscv_vector.isa", "riscv_zc.isa", "riscv_zhintpause.isa", + "riscv_zicbop.isa", "riscv_zicond.isa", "riscv_zihintntl.isa", "riscv_zimop.isa", @@ -386,8 +389,8 @@ deps = [ ":riscv_bitmanip_instructions", ":riscv_g", - ":riscv_rvm23_instructions", ":riscv_v", + ":rvm23_instructions", "@com_google_absl//absl/functional:bind_front", ], ) @@ -402,6 +405,7 @@ "riscv32zb.bin_fmt", "riscv_zc.bin_fmt", "riscv_zhintpause.bin_fmt", + "riscv_zicbop.bin_fmt", "riscv_zicond.bin_fmt", "riscv_zihintntl.bin_fmt", "riscv_zimop.bin_fmt",
diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt index d281e06..4123920 100644 --- a/riscv/riscv32g.bin_fmt +++ b/riscv/riscv32g.bin_fmt
@@ -154,7 +154,7 @@ slti : IType : func3 == 0b010, opcode == 0b001'0011; sltiu : IType : func3 == 0b011, opcode == 0b001'0011; xori : IType : func3 == 0b100, opcode == 0b001'0011; - ori : IType : func3 == 0b110, opcode == 0b001'0011; + ori : IType : func3 == 0b110, rd != 0b00000, opcode == 0b001'0011; andi : IType : func3 == 0b111, opcode == 0b001'0011; slli : RType : func7 == 0b000'0000, func3==0b001, opcode == 0b001'0011; srli : RType : func7 == 0b000'0000, func3==0b101, opcode == 0b001'0011;
diff --git a/riscv/riscv_zc.bin_fmt b/riscv/riscv_zc.bin_fmt index 76c3ea9..dc47da8 100644 --- a/riscv/riscv_zc.bin_fmt +++ b/riscv/riscv_zc.bin_fmt
@@ -17,96 +17,6 @@ // Compact instruction formats. -format Inst16Format[16] { - fields: - unsigned func3[3]; - unsigned bits[11]; - unsigned op[2]; -}; - -format CA[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func2[2]; - unsigned fs2p[3]; - unsigned op[2]; - overlays: - unsigned uimm2[2] = func2; - unsigned uimm1[1] = func2[0]; - unsigned func5[5] = func2, fs2p; - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, fs2p; - unsigned rd[5] = 0b01, rs1p; -}; - -format CB[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned func2[2] = [11, 10]; - unsigned func5[5] = [12..10, 6..5]; - unsigned shamt[6] = [12, 6..2]; - unsigned rs2p[3] = [4..2]; - unsigned rs2[5] = 0b10, [4..2]; - signed bimm[9] = imm3[2], imm5[4..3, 0], imm3[1..0], imm5[2..1], 0b0; -}; - -format CI[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm1[1]; - unsigned rs1[5]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned rd[5] = rs1; - signed imm6[6] = imm1, imm5; - unsigned uimm6[6] = imm1, imm5; - signed imm18[18] = imm1, imm5, 0b0000'0000'0000; - signed ci_imm10[10] = imm1, imm5[2..1, 3, 0, 4], 0b0000; - unsigned ci_imm_w[8] = imm5[1..0], imm1, imm5[4..2], 0b00; - unsigned ci_imm_d[9] = imm5[2..0], imm1, imm5[4..3], 0b000; -}; - -format CIW[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm8[8]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned rd[5] = 0b01, rdp; - unsigned ciw_imm10[10] = imm8[5..2, 7..6, 0, 1], 0b00; -}; - -format CJ[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm11[11]; - unsigned op[2]; - overlays: - signed jimm[12] = imm11[10, 6, 8..7, 4, 5, 0, 9, 3..1], 0b0; -}; - -format CL[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned cl_rs1[5] = 0b01, rs1p; - unsigned cl_rd[5] = 0b01, rdp; - unsigned cl_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cl_imm_d[8] = imm2, imm3, 0b000; -}; format CLB[16] : Inst16Format { fields: @@ -134,14 +44,6 @@ unsigned uimm2[2] = uimm1, 0b0; }; -format CMJT[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned index[8]; - unsigned op[2]; - overlays: -}; - format CMMV[16] : Inst16Format { fields: unsigned func6[6]; @@ -156,35 +58,12 @@ format CMPP[16] : Inst16Format { fields: - unsigned func6[6]; - unsigned func2[2]; + unsigned func8[8]; unsigned rlist[4]; unsigned spimm[2]; unsigned op[2]; }; -format CR[16] : Inst16Format { - fields: - unsigned func4[4]; - unsigned rs1[5]; - unsigned rs2[5]; - unsigned op[2]; -}; - -format CS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned cs_rs1[5] = 0b01, rs1p; - unsigned cs_rs2[5] = 0b01, rs2p; - unsigned cs_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cs_imm_d[8] = imm2, imm3, 0b000; -}; format CSB[16] : Inst16Format { fields: @@ -212,17 +91,6 @@ unsigned uimm2[2] = uimm1, 0b0; }; -format CSS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm6[6]; - unsigned rs2[5]; - unsigned op[2]; - overlays: - unsigned css_imm_w[8] = imm6[1..0], imm6[5..2], 0b00; - unsigned css_imm_d[9] = imm6[2..0], imm6[5..3], 0b000; -}; - format CU[16] : Inst16Format { fields: unsigned func6[6]; @@ -235,7 +103,7 @@ }; // Non floating point compact instructions from "C". -instruction group RiscVZca[16] : Inst16Format { +instruction group RiscVCZca[16] : Inst16Format { caddi4spn : CIW: func3 == 0b000, op == 0b00, imm8 != 0; clw : CL : func3 == 0b010, op == 0b00; csw : CS : func3 == 0b110, op == 0b00; @@ -266,7 +134,7 @@ } // Single-precision floating point compact instructions from "C". -instruction group RiscVZcf[16] : Inst16Format { +instruction group RiscVCZcf[16] : Inst16Format { cflw : CL : func3 == 0b011, op == 0b00; cfsw : CS : func3 == 0b111, op == 0b00; cflwsp : CI : func3 == 0b011, op == 0b10; @@ -274,7 +142,7 @@ } // Double-precision floating point compact instructions from "C". -instruction group RiscVZcd[16] : Inst16Format { +instruction group RiscVCZcd[16] : Inst16Format { cfld : CL : func3 == 0b001, op == 0b00; cfldsp : CI : func3 == 0b001, op == 0b10; cfsd : CS : func3 == 0b101, op == 0b00; @@ -282,32 +150,33 @@ } // Simple code-size saving instructions that are easy to implement on all CPUs. -instruction group RiscVZcb32[16] : Inst16Format { +instruction group RiscVCZcb32[16] : Inst16Format { c_lbu : CLB : func6 == 0b100'000, op == 0b00; - c_lhu : CLH : func6 == 0b100'001, func2[1] == 0b0, op == 0b00; - c_lh : CLH : func6 == 0b100'001, func2[1] == 0b1, op == 0b00; - c_sb : CSB : func6 == 0b100'010, op2 == 0b00; - c_sh : CSH : func6 == 0b100'011, func2[1] == 0b0, op == 0b00; - c_zext_b : CU : func6 == 0b100'111, func5 == 0b11000, op = 0b01; + c_lhu : CLH : func6 == 0b100'001, func1 == 0b0, op == 0b00; + c_lh : CLH : func6 == 0b100'001, func1 == 0b1, op == 0b00; + c_sb : CSB : func6 == 0b100'010, op == 0b00; + c_sh : CSH : func6 == 0b100'011, func1 == 0b0, op == 0b00; + c_zext_b : CU : func6 == 0b100'111, func5 == 0b11000, op == 0b01; c_sext_b : CU : func6 == 0b100'111, func5 == 0b11001, op == 0b01; c_zext_h : CU : func6 == 0b100'111, func5 == 0b11010, op == 0b01; c_sext_h : CU : func6 == 0b100'111, func5 == 0b11011, op == 0b01; - c_not : CU : func6 == 0b100'111, func5 == 0b11101, op == 0b01;; + c_not : CU : func6 == 0b100'111, func5 == 0b11101, op == 0b01; c_mul : CA : func6 == 0b100'111, func2 == 0b10, op == 0b01; } // For 64 bit CPUs the zext_w instruction is added. instruction group RiscV64Zcb64[64] : Inst16Format { - c_zext_w : CU : func6 == 0b100'111, func5 = 0b11100, op == 0b01; + c_zext_w : CU : func6 == 0b100'111, func5 == 0b11100, op == 0b01; } // Push/pop/register move instructions. Incompatible with Zcf and Zcd. -instruction group RiscVZcmp[16] : Inst16Format { +instruction group RiscVCZcmp[16] : Inst16Format { cm_push : CMPP : func8 == 0b101'11000, rlist > 3, op == 0b10; cm_pop : CMPP : func8 == 0b101'11010, rlist > 3,op == 0b10; cm_popret : CMPP : func8 == 0b101'11110, rlist > 3,op == 0b10; cm_popretz : CMPP : func8 == 0b101'11100, rlist > 3, op == 0b10; - cm_mvsa01 : CMMV : func6 == 0b101'011, func2 == 0b01, rs1p != rs2p, op == 0b10; + cm_mvsa01 : CMMV : func6 == 0b101'011, func2 == 0b01, op == 0b10; + // cm_mvsa01 : CMMV : func6 == 0b101'011, func2 == 0b01, rs1p != rs2p, op == 0b10; cm_mva01s : CMMV : func6 == 0b101'011, func2 == 0b11, op == 0b10; } @@ -319,7 +188,7 @@ } // Jump table instructions. -instruction group RiscVZcmt[16] : Inst16Format { +instruction group RiscVCZcmt[16] : Inst16Format { cm_jt : CMJT : func6 == 0b101'000, index < 32, op == 0b10; cm_jalt : CMJT : func6 == 0b101'000, index >= 32,op == 0b10; } \ No newline at end of file
diff --git a/riscv/riscv_zc.isa b/riscv/riscv_zc.isa index e386ae4..18921e7 100644 --- a/riscv/riscv_zc.isa +++ b/riscv/riscv_zc.isa
@@ -174,20 +174,20 @@ } default size = 2; opcodes { - cflwsp{(: x2, I_ci_uimm6x4 : ), (: : c3frd)}, - resources:{next_pc,x2 : cfrd[0..]}, + cflwsp{(: x2, I_ci_uimm6x4 : ), (: : frd)}, + resources:{next_pc, x2 : frd[0..]}, disasm: "flw", "%frd, %I_ci_uimm6x4(%x2)", semfunc: "&RV32::RiscVILw", "&RV32::RiscVILwChild"; cfswsp{: x2, I_css_uimm6x4, cfrs2 : }, - resources: {next_pc,x2, cfrs2}, + resources: {next_pc, x2, cfrs2}, disasm: "fsw", "%cfrs2, %I_css_uimm6x4(%x2)", semfunc: "&RV32::RiscVISw"; cflw{(: c3rs1, I_cl_uimm5x4 : ), (: : c3frd)}, - resources: {next_pc,c3rs1 : c3frd[0..]}, + resources: {next_pc, c3rs1 : c3frd[0..]}, disasm: "flw", "%c3frd, %I_cl_uimm5x4(%c3rs1)", semfunc: "&RV32::RiscVILw", "&RV32::RiscVILwChild"; cfsw{: c3rs1, I_cl_uimm5x4, c3frs2 : }, - resources: {next_pc,c3rs1, c3frs2}, + resources: {next_pc, c3rs1, c3frs2}, disasm: "fsw", "%c3frs2, %I_cl_uimm5x4(%c3rs1)", semfunc: "&RV32::RiscVISw"; } @@ -212,20 +212,20 @@ } default size = 2; opcodes { - cfldsp{(: x2, I_ci_uimm6x8 : ), (: : c3drd)}, - resources:{next_pc,x2 : drd[0..]}, + cfldsp{(: x2, I_ci_uimm6x8 : ), (: : drd)}, + resources:{next_pc, x2 : drd[0..]}, disasm: "fld", "%drd, %I_ci_uimm6x8(%x2)", semfunc: "&RV64::RiscVILd", "&RV64::RiscVILdChild"; cfsdsp{: x2, I_css_uimm6x8, cdrs2 : }, - resources: {next_pc,x2, cdrs2}, + resources: {next_pc, x2, cdrs2}, disasm: "fsd", "%cdrs2, %I_css_uimm6x8(%x2)", semfunc: "&RV64::RiscVISd"; cfld{(: c3rs1, I_cl_uimm5x8 : ), (: : c3drd)}, - resources: {next_pc,c3rs1 : c3drd[0..]}, + resources: {next_pc, c3rs1 : c3drd[0..]}, disasm: "fld", "%c3drd, %I_cl_uimm5x8(%c3rs1)", semfunc: "&RV64::RiscVILd", "&RV64::RiscVILdChild"; cfsd{: c3rs1, I_cl_uimm5x8, c3drs2 : }, - resources: {next_pc,c3rs1, c3drs2}, + resources: {next_pc, c3rs1, c3drs2}, disasm: "fsd", "%c3drs2, %I_cl_uimm5x8(%c3rs1)", semfunc: "&RV32::RiscVDSd"; }
diff --git a/riscv/riscv_zicbop.bin_fmt b/riscv/riscv_zicbop.bin_fmt new file mode 100644 index 0000000..312248a --- /dev/null +++ b/riscv/riscv_zicbop.bin_fmt
@@ -0,0 +1,34 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file defines the encoding for the cache prefetch instructions in the +// Zicbop extension. + +format ZICBOP[32] : Inst32Format { + fields: + unsigned offset[7]; + unsigned func5[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned imm5[5]; + unsigned op[7]; + overlays: + unsigned bop_uimm12[12] = offset, 0b00000; +} + +instruction group RiscVZicbop[32] : Inst32Format { + prefetch_i : ZICBOP : func5 == 0b00000, func3 == 0b110, imm5 == 0b00000, op == 0b001'0011; + prefetch_r : ZICBOP : func5 == 0b00001, func3 == 0b110, imm5 == 0b00000, op == 0b001'0010; + prefetch_w : ZICBOP : func5 == 0b00011, func3 == 0b110, imm5 == 0b00000, op == 0b001'0001; +}
diff --git a/riscv/riscv_zicbop.isa b/riscv/riscv_zicbop.isa new file mode 100644 index 0000000..b0c68ae --- /dev/null +++ b/riscv/riscv_zicbop.isa
@@ -0,0 +1,48 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// This file defines the cache prefetch instructions in the Zicbop extension. + +slot riscv_zicbop32 { + includes { + #include "riscv/riscv_zicbop_instructions.h" + } + default size = 4; + opcodes { + prefetch_i{: rs1, bop_uimm12: }, + resources: { rs1 :}, + disasm: "prefetch.i", "%bop_uimm12(%rs1)", + semfunc: "&RV32::RiscVPrefetchI"; + prefetch_r{: rs1, bop_uimm12: }, + resources: { rs1 :}, + disasm: "prefetch.r", "%bop_uimm12(%rs1)", + semfunc: "&RV32::RiscVPrefetchR"; + prefetch_w{: rs1, bop_uimm12: }, + resources: { rs1 :}, + disasm: "prefetch.w", "%bop_uimm12(%rs1)", + semfunc: "&RV32::RiscVPrefetchW"; + } +} + +slot riscv_zicbop64 : riscv_zicbop32 { + includes { + #include "riscv/riscv_zicbop_instructions.h" + } + default size = 4; + opcodes { + prefetch_i = override, semfunc: "&RV64::RiscVPrefetchI"; + prefetch_r = override, semfunc: "&RV64::RiscVPrefetchR"; + prefetch_w = override, semfunc: "&RV64::RiscVPrefetchW"; + } +}
diff --git a/riscv/riscv_zicbop_instructions.cc b/riscv/riscv_zicbop_instructions.cc new file mode 100644 index 0000000..e8a68e3 --- /dev/null +++ b/riscv/riscv_zicbop_instructions.cc
@@ -0,0 +1,45 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "riscv/riscv_zicbop_instructions.h" + +#include "mpact/sim/generic/instruction.h" + +// This file contains the definitions of the instruction semantic functions +// for the cache prefetch instructions in the Zicbop extension. For now, these +// instructions are implemented as no-ops. + +namespace mpact::sim::riscv { + +using ::mpact::sim::generic::Instruction; + +namespace RV32 { + +// These instructions are not implemented for now. +void RiscVPrefetchI(const Instruction *inst) { /* empty */ } +void RiscVPrefetchR(const Instruction *inst) { /* empty */ } +void RiscVPrefetchW(const Instruction *inst) { /* empty */ } + +} // namespace RV32 + +namespace RV64 { + +// These instructions are not implemented for now. +void RiscVPrefetchI(const Instruction *inst) { /* empty */ } +void RiscVPrefetchR(const Instruction *inst) { /* empty */ } +void RiscVPrefetchW(const Instruction *inst) { /* empty */ } + +} // namespace RV64 + +} // namespace mpact::sim::riscv
diff --git a/riscv/riscv_zicbop_instructions.h b/riscv/riscv_zicbop_instructions.h new file mode 100644 index 0000000..f603a37 --- /dev/null +++ b/riscv/riscv_zicbop_instructions.h
@@ -0,0 +1,49 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef THIRD_PARTY_MPACT_RISCV_RISCV_ZICBOP_INSTRUCTIONS_H_ +#define THIRD_PARTY_MPACT_RISCV_RISCV_ZICBOP_INSTRUCTIONS_H_ + +#include "mpact/sim/generic/instruction.h" + +// This file contains the declarations of the instruction semantic functions +// for the cache prefetch instructions in the Zicbop extension. + +namespace mpact::sim::riscv { + +using ::mpact::sim::generic::Instruction; + +namespace RV32 { + +// Each of these instructions take two source operands, rs1 and a 12 bit +// immediate offset. +void RiscVPrefetchI(const Instruction *inst); +void RiscVPrefetchR(const Instruction *inst); +void RiscVPrefetchW(const Instruction *inst); + +} // namespace RV32 + +namespace RV64 { + +// Each of these instructions take two source operands, rs1 and a 12 bit +// immediate offset. +void RiscVPrefetchI(const Instruction *inst); +void RiscVPrefetchR(const Instruction *inst); +void RiscVPrefetchW(const Instruction *inst); + +} // namespace RV64 + +} // namespace mpact::sim::riscv + +#endif // THIRD_PARTY_MPACT_RISCV_RISCV_ZICBOP_INSTRUCTIONS_H_
diff --git a/riscv/rvm23.bin_fmt b/riscv/rvm23.bin_fmt index fab85ed..e8bdf11 100644 --- a/riscv/rvm23.bin_fmt +++ b/riscv/rvm23.bin_fmt
@@ -32,21 +32,25 @@ RiscVZimop, RiscVZhintpause, RiscVZihintntl, + // Cache prefetch instructions. + RiscVZicbop, }; RVM23Inst16 = { RiscVZcmop, RiscVCZihintntl, - RiscVCZca32, + RiscVCZca, + RiscVCZcf, RiscVCZcb32, - RiscVCZcmp32, - RiscVCZcmt32, + RiscVCZcmp, + RiscVCZcmt, }; } #include "riscv/riscv32g.bin_fmt" #include "riscv/riscv32zb.bin_fmt" -#include "riscv/riscv_zicond.bin_fmt" -#include "riscv/riscv_zimop.bin_fmt" -#include "riscv/riscv_zhintpause.bin_fmt" -#include "riscv/riscv_zihintntl.bin_fmt" #include "riscv/riscv_zc.bin_fmt" +#include "riscv/riscv_zhintpause.bin_fmt" +#include "riscv/riscv_zicbop.bin_fmt" +#include "riscv/riscv_zicond.bin_fmt" +#include "riscv/riscv_zihintntl.bin_fmt" +#include "riscv/riscv_zimop.bin_fmt"
diff --git a/riscv/rvm23.isa b/riscv/rvm23.isa index c298097..d71a93c 100644 --- a/riscv/rvm23.isa +++ b/riscv/rvm23.isa
@@ -23,6 +23,7 @@ #include "riscv/riscv32zb.isa" #include "riscv/riscv_vector.isa" #include "riscv/riscv_zc.isa" +#include "riscv/riscv_zicbop.isa" #include "riscv/riscv_zicond.isa" #include "riscv/riscv_zimop.isa" #include "riscv/riscv_zhintpause.isa" @@ -47,8 +48,10 @@ riscv_czihintntl, riscv_zca32, riscv_zcb32, + riscv_zcf32, riscv_zcmp32, - riscv_zcmt32 { + riscv_zcmt32, + riscv_zicbop32 { default opcode = disasm: "Illegal instruction at 0x%(@:08x)", semfunc: "&RiscVIllegalInstruction";