riscv/riscv_zfh.bin_fmt

// Copyright 2025 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

#include "riscv/riscv32g.bin_fmt"

decoder ZFH {
  namespace mpact::sim::riscv::zfh;
  opcode_enum = "OpcodeEnum";
  includes {
    #include "riscv/zfh_decoder.h"
  }
  RiscVZfhInst32 = { RiscVZfhminInst32 };
}

instruction group RiscVZfhminInst32[32] : Inst32Format {
  flh     : IType : func3 == 0b001,  opcode == 0b000'0111;
  fsh     : SType : func3 == 0b001,  opcode == 0b010'0111;
  fmv_xh  : RType : func7 == 0b1110010, rs2 == 0, func3 == 0b000, opcode == 0b1010011;
  fmv_hx  : RType : func7 == 0b1111010, rs2 == 0, func3 == 0b000, opcode == 0b1010011;
  fcvt_sh : RType : func7 == 0b0100000, rs2 == 0b00010, opcode == 0b1010011;
  fcvt_hs : RType : func7 == 0b0100010, rs2 == 0b00000, opcode == 0b1010011;
  fcvt_dh : RType : func7 == 0b0100001, rs2 == 0b00010, opcode == 0b1010011;
  fcvt_hd : RType : func7 == 0b0100010, rs2 == 0b00001, opcode == 0b1010011;
};