No public description PiperOrigin-RevId: 784632110 Change-Id: I55f13c33e1e7ffb792e54f2baac90967322c8bef
diff --git a/repos.bzl b/repos.bzl index f35fa83..3353463 100644 --- a/repos.bzl +++ b/repos.bzl
@@ -22,7 +22,7 @@ if not native.existing_rule("com_google_mpact-sim"): http_archive( name = "com_google_mpact-sim", - sha256 = "9edadc9d8a418ad2d75f550e7306dfadca54a8ade0ad47c4e2fcef01a61917ca", - strip_prefix = "mpact-sim-cb5a4c872007a32a2cf96453eda1d1e7be79d0ba", - url = "https://github.com/google/mpact-sim/archive/cb5a4c872007a32a2cf96453eda1d1e7be79d0ba.tar.gz", + sha256 = "e59a8ee258c3108d5589de7bfdd0b3880c31f7a7a2bd80284cdf0f4bb00fb298", + strip_prefix = "mpact-sim-31d54ae16a1227fc102dde44f2283113863b10e5", + url = "https://github.com/google/mpact-sim/archive/31d54ae16a1227fc102dde44f2283113863b10e5.tar.gz", )
diff --git a/riscv/riscv_zc.bin_fmt b/riscv/riscv_zc.bin_fmt index 8bcb1a8..1eb8f5e 100644 --- a/riscv/riscv_zc.bin_fmt +++ b/riscv/riscv_zc.bin_fmt
@@ -23,7 +23,7 @@ instruction group RiscVCZca[16] : Inst16Format { caddi4spn : CIW: func3 == 0b000, op == 0b00, imm8 != 0; clw : CL : func3 == 0b010, op == 0b00; - csw : CS : func3 == 0b110, op == 0b00;ß + csw : CS : func3 == 0b110, op == 0b00; cnop : CI : func3 == 0b000, imm1 == 0, rs1 == 0, imm5 == 0, op == 0b01; caddi : CI : func3 == 0b000, imm6 != 0, rd != 0, op == 0b01; cjal : CJ : func3 == 0b001, op == 0b01;
diff --git a/riscv/riscv_zfh_instructions.cc b/riscv/riscv_zfh_instructions.cc index e807747..c0dfcd8 100644 --- a/riscv/riscv_zfh_instructions.cc +++ b/riscv/riscv_zfh_instructions.cc
@@ -513,8 +513,8 @@ // Move a half precision value from an integer register to a float register template <typename XRegister> inline void RiscVZfhFMvhxHelper(const Instruction *instruction) { - using DstRegValue = RVFpRegister::ValueType; - using SrcRegValue = XRegister::ValueType; + using DstRegValue = typename RVFpRegister::ValueType; + using SrcRegValue = typename XRegister::ValueType; SrcRegValue lhs = generic::GetInstructionSource<SrcRegValue>(instruction, 0); HalfFP dest_value = {.value = static_cast<uint16_t>(lhs)}; @@ -535,7 +535,7 @@ // Compare two half precision values for equality. template <typename XRegister> inline void RiscVZfhFcmpeqHelper(const Instruction *instruction) { - using DstRegValue = XRegister::ValueType; + using DstRegValue = typename XRegister::ValueType; uint32_t fflags = 0; HalfFP lhs = GetNaNBoxedSource<RVFpRegister::ValueType, HalfFP>(instruction, 0); @@ -558,7 +558,7 @@ // Compare two half precision values for less than. template <typename XRegister> inline void RiscVZfhFcmpltHelper(const Instruction *instruction) { - using DstRegValue = XRegister::ValueType; + using DstRegValue = typename XRegister::ValueType; uint32_t unused_fflags = 0; HalfFP lhs = GetNaNBoxedSource<RVFpRegister::ValueType, HalfFP>(instruction, 0); @@ -583,7 +583,7 @@ // Compare two half precision values for less than or equal to. template <typename XRegister> void RiscVZfhFcmpleHelper(const Instruction *instruction) { - using DstRegValue = XRegister::ValueType; + using DstRegValue = typename XRegister::ValueType; uint32_t unused_fflags = 0; HalfFP lhs = GetNaNBoxedSource<RVFpRegister::ValueType, HalfFP>(instruction, 0);
diff --git a/riscv/test/riscv_fp_test_base.h b/riscv/test/riscv_fp_test_base.h index a408504..d54889b 100644 --- a/riscv/test/riscv_fp_test_base.h +++ b/riscv/test/riscv_fp_test_base.h
@@ -68,9 +68,9 @@ template <typename T> struct FPTypeInfo { using IntType = T; - static const int kBitSize = 8 * sizeof(T); - static const int kExpSize = 0; - static const int kSigSize = 0; + static constexpr int kBitSize = 8 * sizeof(T); + static constexpr int kExpSize = 0; + static constexpr int kSigSize = 0; static bool IsNaN(T value) { return false; } static constexpr IntType kQNaN = 0; static constexpr IntType kSNaN = 0; @@ -86,22 +86,22 @@ struct FPTypeInfo<float> { using T = float; using IntType = uint32_t; - static const int kExpBias = 127; - static const int kBitSize = sizeof(float) << 3; - static const int kExpSize = 8; - static const int kSigSize = kBitSize - kExpSize - 1; - static const IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; - static const IntType kSigMask = (1ULL << kSigSize) - 1; - static const IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; - static const IntType kSNaN = kExpMask | 1; - static const IntType kPosInf = kExpMask; - static const IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); - static const IntType kPosZero = 0; - static const IntType kNegZero = 1ULL << (kBitSize - 1); - static const IntType kPosDenorm = 1ULL << (kSigSize - 2); - static const IntType kNegDenorm = + static constexpr int kExpBias = 127; + static constexpr int kBitSize = sizeof(float) << 3; + static constexpr int kExpSize = 8; + static constexpr int kSigSize = kBitSize - kExpSize - 1; + static constexpr IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; + static constexpr IntType kSigMask = (1ULL << kSigSize) - 1; + static constexpr IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; + static constexpr IntType kSNaN = kExpMask | 1; + static constexpr IntType kPosInf = kExpMask; + static constexpr IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); + static constexpr IntType kPosZero = 0; + static constexpr IntType kNegZero = 1ULL << (kBitSize - 1); + static constexpr IntType kPosDenorm = 1ULL << (kSigSize - 2); + static constexpr IntType kNegDenorm = (1ULL << (kBitSize - 1)) | (1ULL << (kSigSize - 2)); - static const IntType kCanonicalNaN = 0x7fc0'0000ULL; + static constexpr IntType kCanonicalNaN = 0x7fc0'0000ULL; static bool IsNaN(T value) { return std::isnan(value); } static bool IsQNaN(T value) { IntType uint_val = absl::bit_cast<IntType>(value); @@ -114,22 +114,22 @@ struct FPTypeInfo<double> { using T = double; using IntType = uint64_t; - static const int kExpBias = 1023; - static const int kBitSize = sizeof(double) << 3; - static const int kExpSize = 11; - static const int kSigSize = kBitSize - kExpSize - 1; - static const IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; - static const IntType kSigMask = (1ULL << kSigSize) - 1; - static const IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; - static const IntType kSNaN = kExpMask | 1; - static const IntType kPosInf = kExpMask; - static const IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); - static const IntType kPosZero = 0; - static const IntType kNegZero = 1ULL << (kBitSize - 1); - static const IntType kPosDenorm = 1ULL << (kSigSize - 2); - static const IntType kNegDenorm = + static constexpr int kExpBias = 1023; + static constexpr int kBitSize = sizeof(double) << 3; + static constexpr int kExpSize = 11; + static constexpr int kSigSize = kBitSize - kExpSize - 1; + static constexpr IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; + static constexpr IntType kSigMask = (1ULL << kSigSize) - 1; + static constexpr IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; + static constexpr IntType kSNaN = kExpMask | 1; + static constexpr IntType kPosInf = kExpMask; + static constexpr IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); + static constexpr IntType kPosZero = 0; + static constexpr IntType kNegZero = 1ULL << (kBitSize - 1); + static constexpr IntType kPosDenorm = 1ULL << (kSigSize - 2); + static constexpr IntType kNegDenorm = (1ULL << (kBitSize - 1)) | (1ULL << (kSigSize - 2)); - static const IntType kCanonicalNaN = 0x7ff8'0000'0000'0000ULL; + static constexpr IntType kCanonicalNaN = 0x7ff8'0000'0000'0000ULL; static bool IsNaN(T value) { return std::isnan(value); } static bool IsQNaN(T value) { IntType uint_val = absl::bit_cast<IntType>(value); @@ -142,22 +142,22 @@ struct FPTypeInfo<HalfFP> { using T = HalfFP; using IntType = uint16_t; - static const int kExpBias = 15; - static const int kBitSize = sizeof(HalfFP) << 3; - static const int kExpSize = 5; - static const int kSigSize = kBitSize - kExpSize - 1; // 10 from the spec. - static const IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; - static const IntType kSigMask = (1ULL << kSigSize) - 1; - static const IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; - static const IntType kSNaN = kExpMask | 1; - static const IntType kPosInf = kExpMask; - static const IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); - static const IntType kPosZero = 0; - static const IntType kNegZero = 1ULL << (kBitSize - 1); - static const IntType kPosDenorm = 1ULL << (kSigSize - 2); - static const IntType kNegDenorm = + static constexpr int kExpBias = 15; + static constexpr int kBitSize = sizeof(HalfFP) << 3; + static constexpr int kExpSize = 5; + static constexpr int kSigSize = kBitSize - kExpSize - 1; // 10 from the spec. + static constexpr IntType kExpMask = ((1ULL << kExpSize) - 1) << kSigSize; + static constexpr IntType kSigMask = (1ULL << kSigSize) - 1; + static constexpr IntType kQNaN = kExpMask | (1ULL << (kSigSize - 1)) | 1; + static constexpr IntType kSNaN = kExpMask | 1; + static constexpr IntType kPosInf = kExpMask; + static constexpr IntType kNegInf = kExpMask | (1ULL << (kBitSize - 1)); + static constexpr IntType kPosZero = 0; + static constexpr IntType kNegZero = 1ULL << (kBitSize - 1); + static constexpr IntType kPosDenorm = 1ULL << (kSigSize - 2); + static constexpr IntType kNegDenorm = (1ULL << (kBitSize - 1)) | (1ULL << (kSigSize - 2)); - static const IntType kCanonicalNaN = 0x7e00; + static constexpr IntType kCanonicalNaN = 0x7e00; // std::isnan won't work for half precision. static bool IsNaN(T wrapper) { IntType exp = (wrapper.value & kExpMask) >> kSigSize;
diff --git a/riscv/test/riscv_zfh_instructions_test.cc b/riscv/test/riscv_zfh_instructions_test.cc index 08a434a..154e3a4 100644 --- a/riscv/test/riscv_zfh_instructions_test.cc +++ b/riscv/test/riscv_zfh_instructions_test.cc
@@ -212,7 +212,7 @@ this->instruction_->AppendSource(offset_source_operand); this->template SetRegisterValues<typename XRegister::ValueType, XRegister>( - {{kRs1Name, static_cast<XRegister::ValueType>(base)}}); + {{kRs1Name, static_cast<typename XRegister::ValueType>(base)}}); this->template SetRegisterValues<RVFpRegister::ValueType, RVFpRegister>( {{kFrdName, 0}}); @@ -478,7 +478,7 @@ template <typename XRegister> template <typename FPType> void RVZfhInstructionTestBase<XRegister>::FmvHxNanBoxHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; this->template AppendRegisterOperands<RVFpRegister>({}, {"f5"}); this->template AppendRegisterOperands<XRegister>({"x5"}, {}); this->instruction_->AppendSource(new TestRoundingModeSourceOperand()); @@ -500,7 +500,7 @@ // float register to an integer register. template <typename XRegister> void RVZfhInstructionTestBase<XRegister>::FmvXhHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; this->template UnaryOpFPTestHelper<ScalarRegisterType, HalfFP>( "fmv.x.h", this->instruction_, {"f", "x"}, 32, [](HalfFP half_fp) -> ScalarRegisterType { @@ -553,7 +553,7 @@ // Helper to test the comparison of two half precision values for equality. template <typename XRegister> void RVZfhInstructionTestBase<XRegister>::CmpEqHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; this->template BinaryOpWithFflagsFPTestHelper<ScalarRegisterType, HalfFP, HalfFP>( "feq.h", this->instruction_, {"f", "f", "x"}, 32, @@ -574,7 +574,7 @@ // Helper to test the comparison of two half precision values for less than. template <typename XRegister> void RVZfhInstructionTestBase<XRegister>::CmpLtHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; this->template BinaryOpWithFflagsFPTestHelper<ScalarRegisterType, HalfFP, HalfFP>( "flt.h", this->instruction_, {"f", "f", "x"}, 32, @@ -600,7 +600,7 @@ // equal to. template <typename XRegister> void RVZfhInstructionTestBase<XRegister>::CmpLeHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; this->template BinaryOpWithFflagsFPTestHelper<ScalarRegisterType, HalfFP, HalfFP>( "fle.h", this->instruction_, {"f", "f", "x"}, 32, @@ -625,7 +625,7 @@ // Helper to test the classification of the half precision value. template <typename XRegister> void RVZfhInstructionTestBase<XRegister>::ClassHelper() { - using ScalarRegisterType = XRegister::ValueType; + using ScalarRegisterType = typename XRegister::ValueType; UnaryOpWithFflagsMixedTestHelper<XRegister, RVFpRegister, ScalarRegisterType, HalfFP>( "fclass.h", this->instruction_, {"f", "x"}, 32,
diff --git a/riscv/test/zfh_encoding.h b/riscv/test/zfh_encoding.h index eb7311e..cf875fc 100644 --- a/riscv/test/zfh_encoding.h +++ b/riscv/test/zfh_encoding.h
@@ -86,17 +86,17 @@ class ZfhEncoding : public ZfhTraits<XLen>::EncodingBase, public RiscVEncodingCommon { public: - using OpcodeEnum = ZfhTraits<XLen>::OpcodeEnum; - using FormatEnum = ZfhTraits<XLen>::FormatEnum; - using DestOpEnum = ZfhTraits<XLen>::DestOpEnum; - using SourceOpEnum = ZfhTraits<XLen>::SourceOpEnum; - using ComplexResourceEnum = ZfhTraits<XLen>::ComplexResourceEnum; - using SimpleResourceEnum = ZfhTraits<XLen>::SimpleResourceEnum; - using PredOpEnum = ZfhTraits<XLen>::PredOpEnum; - using SlotEnum = ZfhTraits<XLen>::SlotEnum; - using SimpleResourceVector = ZfhTraits<XLen>::SimpleResourceVector; - using Extractors = ZfhTraits<XLen>::Extractors; - using XRegister = ZfhTraits<XLen>::XRegister; + using OpcodeEnum = typename ZfhTraits<XLen>::OpcodeEnum; + using FormatEnum = typename ZfhTraits<XLen>::FormatEnum; + using DestOpEnum = typename ZfhTraits<XLen>::DestOpEnum; + using SourceOpEnum = typename ZfhTraits<XLen>::SourceOpEnum; + using ComplexResourceEnum = typename ZfhTraits<XLen>::ComplexResourceEnum; + using SimpleResourceEnum = typename ZfhTraits<XLen>::SimpleResourceEnum; + using PredOpEnum = typename ZfhTraits<XLen>::PredOpEnum; + using SlotEnum = typename ZfhTraits<XLen>::SlotEnum; + using SimpleResourceVector = typename ZfhTraits<XLen>::SimpleResourceVector; + using Extractors = typename ZfhTraits<XLen>::Extractors; + using XRegister = typename ZfhTraits<XLen>::XRegister; explicit ZfhEncoding(RiscVState *state) : state_(state), @@ -173,19 +173,20 @@ } ResourceOperandInterface *GetSimpleResourceOperand( - SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, int end) { + SlotEnum, int, OpcodeEnum, SimpleResourceVector &resource_vec, + int end) override { return nullptr; } ResourceOperandInterface *GetComplexResourceOperand( SlotEnum, int, OpcodeEnum, ComplexResourceEnum resource, int begin, - int end) { + int end) override { return nullptr; } DestinationOperandInterface *GetDestination(SlotEnum, int, OpcodeEnum opcode, DestOpEnum dest_op, int dest_no, - int latency) { + int latency) override { int index = static_cast<int>(dest_op); auto iter = dest_op_getters_.find(index); if (iter == dest_op_getters_.end()) { @@ -198,7 +199,8 @@ } SourceOperandInterface *GetSource(SlotEnum, int, OpcodeEnum opcode, - SourceOpEnum source_op, int source_no) { + SourceOpEnum source_op, + int source_no) override { int index = static_cast<int>(source_op); auto iter = source_op_getters_.find(index); if (iter == source_op_getters_.end()) {
diff --git a/riscv/test/zfh_encoding_test.cc b/riscv/test/zfh_encoding_test.cc index 3f54fc5..357375a 100644 --- a/riscv/test/zfh_encoding_test.cc +++ b/riscv/test/zfh_encoding_test.cc
@@ -24,6 +24,7 @@ #include "absl/random/random.h" #include "absl/strings/str_cat.h" +#include "googlemock/include/gmock/gmock.h" #include "mpact/sim/generic/data_buffer.h" #include "mpact/sim/generic/immediate_operand.h" #include "mpact/sim/generic/operand_interface.h" @@ -34,8 +35,6 @@ #include "riscv/riscv_state.h" #include "riscv/zfh32_enums.h" #include "riscv/zfh64_enums.h" -#include "testing/base/public/gmock.h" -#include "testing/base/public/gunit.h" // Test that hand crafted zfh instructions are decoded and parsed correctly. @@ -167,7 +166,7 @@ ZfhEncodingTest() { state_ = new RiscVState("test", ConfigT::rvXLen, &memory_); enc_ = new ZfhEncoding<ConfigT::kXLen>(state_); - expected_slot_ = static_cast<ConfigT::SlotEnum>(ConfigT::slot); + expected_slot_ = static_cast<typename ConfigT::SlotEnum>(ConfigT::slot); } ~ZfhEncodingTest() override { @@ -187,7 +186,7 @@ void FloatFrs2Helper(uint32_t, typename ConfigT::OpcodeEnum); void FloatFrs3Helper(uint32_t, typename ConfigT::OpcodeEnum); void FloatRmHelper(uint32_t, typename ConfigT::OpcodeEnum); - ConfigT::OpcodeEnum GetOpcode(); + typename ConfigT::OpcodeEnum GetOpcode(); FlatDemandMemory memory_; RiscVState *state_; @@ -197,8 +196,9 @@ }; template <typename ConfigT> -ConfigT::OpcodeEnum ZfhEncodingTest<ConfigT>::GetOpcode() { - return static_cast<ConfigT::OpcodeEnum>(enc_->GetOpcode(expected_slot_, 0)); +typename ConfigT::OpcodeEnum ZfhEncodingTest<ConfigT>::GetOpcode() { + return static_cast<typename ConfigT::OpcodeEnum>( + enc_->GetOpcode(expected_slot_, 0)); } // Puts a random value in the expected register and checks that the source @@ -486,7 +486,7 @@ } TYPED_TEST(ZfhEncodingTest, FmvXh_rd) { - using XRegister = TypeParam::XRegister; + using XRegister = typename TypeParam::XRegister; using XValue = typename TypeParam::XRegister::ValueType; for (uint32_t rd_index = 1; rd_index < 32; ++rd_index) { uint32_t rd_adjustment = rd_index << 7;