This fixes github issuyes 11 and 12.

This also addresses an illegal shift amount in bit manipulation inst tests.

Minor cleanup of compiler warnings.

PiperOrigin-RevId: 818757811
Change-Id: I5f1194de401295e48a8f6d4e70badc204232d70c

riscv/riscv_renode.h

diff --git a/riscv/riscv_renode.h b/riscv/riscv_renode.h
index 4f02f57..a16b781 100644
--- a/riscv/riscv_renode.h
+++ b/riscv/riscv_renode.h
@@ -133,7 +133,7 @@
 
  private:
   std::string name_;
-  MemoryInterface* renode_sysbus_ = nullptr;
+  [[maybe_unused]] MemoryInterface* renode_sysbus_ = nullptr;
   RiscVState* rv_state_ = nullptr;
   RiscVFPState* rv_fp_state_ = nullptr;
   generic::DecoderInterface* rv_decoder_ = nullptr;
@@ -153,8 +153,8 @@
   InstructionProfiler* inst_profiler_ = nullptr;
   MemoryUseProfiler* mem_profiler_ = nullptr;
   RiscVInstrumentationControl* instrumentation_control_ = nullptr;
-  uint64_t stack_size_ = 32 * 1024;
-  uint64_t stack_end_ = 0;
+  [[maybe_unused]] uint64_t stack_size_ = 32 * 1024;
+  [[maybe_unused]] uint64_t stack_end_ = 0;
 };
 
 }  // namespace riscv

riscv/riscv_top.cc

diff --git a/riscv/riscv_top.cc b/riscv/riscv_top.cc
index 4b90c44..186748a 100644
--- a/riscv/riscv_top.cc
+++ b/riscv/riscv_top.cc
@@ -308,7 +308,7 @@
       state_->AdvanceDelayLines();
       // Check for interrupt.
       if (state_->is_interrupt_available()) {
-        uint64_t epc = (executed ? state_->pc_operand()->AsUint64(0) : next_pc);
+        uint64_t epc = (executed ? next_pc : state_->pc_operand()->AsUint64(0));
         state_->TakeAvailableInterrupt(epc);
       }
     } while (!executed);
@@ -404,7 +404,8 @@
         state_->AdvanceDelayLines();
         // Check for interrupt.
         if (state_->is_interrupt_available()) {
-          uint64_t epc = (executed ? state_->pc_operand()->AsUint64(0) : pc);
+          uint64_t epc =
+              (executed ? next_pc : state_->pc_operand()->AsUint64(0));
           state_->TakeAvailableInterrupt(epc);
         }
       } while (!executed);

riscv/rv32gv_sim.cc

diff --git a/riscv/rv32gv_sim.cc b/riscv/rv32gv_sim.cc
index cac54a3..c7cd8a9 100644
--- a/riscv/rv32gv_sim.cc
+++ b/riscv/rv32gv_sim.cc
@@ -263,7 +263,7 @@
     return -1;
   }
 
-  mpact::sim::util::MemoryInterface* memory_interface = memory;
+  [[maybe_unused]] mpact::sim::util::MemoryInterface* memory_interface = memory;
   if (memory_watcher != nullptr) {
     memory_interface = memory_watcher;
   }

riscv/test/riscv32_bitmanip_instructions_test.cc

diff --git a/riscv/test/riscv32_bitmanip_instructions_test.cc b/riscv/test/riscv32_bitmanip_instructions_test.cc
index af8749a..a7737b0 100644
--- a/riscv/test/riscv32_bitmanip_instructions_test.cc
+++ b/riscv/test/riscv32_bitmanip_instructions_test.cc
@@ -359,7 +359,7 @@
     SetRegisterValues<uint32_t>({{kX1, val1}, {kX2, val2}});
     instruction_->Execute(nullptr);
     EXPECT_EQ(GetRegisterValue<uint32_t>(kX3),
-              (val1 << val2) | (val1 >> (32 - val2)));
+              (val1 << val2) | ((val2 == 0) ? 0 : (val1 >> (32 - val2))));
   }
 }
 
@@ -375,7 +375,7 @@
     SetRegisterValues<uint32_t>({{kX1, val1}, {kX2, val2}});
     instruction_->Execute(nullptr);
     EXPECT_EQ(GetRegisterValue<uint32_t>(kX3),
-              (val1 >> val2) | (val1 << (32 - val2)));
+              (val1 >> val2) | ((val2 == 0) ? 0 : (val1 << (32 - val2))));
   }
 }