Enabled data caches.
Fixes some issues:
  - Failure when using tagged loads/stores
  - Write allocation was done regardless of the configuration

PiperOrigin-RevId: 681988267
Change-Id: I7afa83dadfda98f37adf32e17b175571587eb932

riscv/riscv_renode.cc

diff --git a/riscv/riscv_renode.cc b/riscv/riscv_renode.cc
index e1a67f4..148845a 100644
--- a/riscv/riscv_renode.cc
+++ b/riscv/riscv_renode.cc
@@ -563,6 +563,10 @@
     auto *cfg = riscv_top_->GetConfig("dcache");
     auto status = cfg->Import(&dcache_value);
     if (!status.ok()) return status;
+    // Hook the cache into the memory port.
+    auto *dcache = riscv_top_->dcache();
+    dcache->set_memory(riscv_top_->state()->memory());
+    riscv_top_->state()->set_memory(dcache);
   }
   return absl::OkStatus();
 }

riscv/riscv_top.cc

diff --git a/riscv/riscv_top.cc b/riscv/riscv_top.cc
index 797921b..d0e0b41 100644
--- a/riscv/riscv_top.cc
+++ b/riscv/riscv_top.cc
@@ -108,6 +108,7 @@
   }
 
   delete icache_;
+  delete dcache_;
   if (inst_db_) inst_db_->DecRef();
   delete rv_breakpoint_manager_;
   delete rv_action_point_manager_;

riscv/rv32g_sim.cc

diff --git a/riscv/rv32g_sim.cc b/riscv/rv32g_sim.cc
index d3d2149..481fe3f 100644
--- a/riscv/rv32g_sim.cc
+++ b/riscv/rv32g_sim.cc
@@ -143,8 +143,9 @@
 // Enable bit manipulation instructions.
 ABSL_FLAG(bool, bitmanip, false, "Enable bit manipulation instructions");
 
-// Flag to enable and configure the instruction cache.
+// Flag to enable and configure the instruction and data caches.
 ABSL_FLAG(std::string, icache, "", "Instruction cache configuration");
+ABSL_FLAG(std::string, dcache, "", "Data cache configuration");
 
 constexpr char kStackEndSymbolName[] = "__stack_end";
 constexpr char kStackSizeSymbolName[] = "__stack_size";
@@ -279,7 +280,18 @@
     if (!status.ok()) return -1;
   }
 
-  // TODO: enable dcache.
+  if (!absl::GetFlag(FLAGS_dcache).empty()) {
+    ComponentValueEntry dcache_value;
+    dcache_value.set_name("dcache");
+    dcache_value.set_string_value(absl::GetFlag(FLAGS_dcache));
+    auto *cfg = riscv_top.GetConfig("dcache");
+    auto status = cfg->Import(&dcache_value);
+    if (!status.ok()) return -1;
+    // Hook the cache into the memory port.
+    auto *dcache = riscv_top.dcache();
+    dcache->set_memory(riscv_top.state()->memory());
+    riscv_top.state()->set_memory(dcache);
+  }
 
   if (absl::GetFlag(FLAGS_exit_on_ecall)) {
     rv_state.set_on_ecall([&riscv_top](const Instruction *inst) -> bool {