Updated assembler to support architectures where the increment in address in the text section is different from the number of bytes added. Updated the decoder generators to better handle slots where instructions have been "deleted" from one or more base slots it inherits from. Fixed minor typos and oversights. PiperOrigin-RevId: 744051094 Change-Id: Icd4860e9f734470d2407fa3486e57322ee574d0c
diff --git a/riscv/BUILD b/riscv/BUILD index 65faa21..95fea11 100644 --- a/riscv/BUILD +++ b/riscv/BUILD
@@ -186,13 +186,10 @@ deps = [ ":riscv_fp_state", ":riscv_state", - "@com_google_absl//absl/base", "@com_google_absl//absl/log", - "@com_google_absl//absl/numeric:bits", "@com_google_absl//absl/numeric:int128", "@com_google_absl//absl/status", "@com_google_absl//absl/strings", - "@com_google_absl//absl/types:span", "@com_google_mpact-sim//mpact/sim/generic:arch_state", "@com_google_mpact-sim//mpact/sim/generic:core", "@com_google_mpact-sim//mpact/sim/generic:instruction", @@ -301,9 +298,7 @@ deps = [ ":riscv_g", ":riscv_state", - ":riscv_v", "@com_google_mpact-sim//mpact/sim/generic:arch_state", - "@com_google_mpact-sim//mpact/sim/generic:core", "@com_google_mpact-sim//mpact/sim/generic:instruction", ], ) @@ -817,15 +812,8 @@ ":riscv_encoding_common", ":riscv_getters", ":riscv_state", - "@com_google_absl//absl/base", - "@com_google_absl//absl/container:flat_hash_map", - "@com_google_absl//absl/functional:any_invocable", - "@com_google_absl//absl/functional:bind_front", "@com_google_absl//absl/log", "@com_google_absl//absl/strings", - "@com_google_absl//absl/strings:str_format", - "@com_google_absl//absl/types:span", - "@com_google_mpact-sim//mpact/sim/generic:arch_state", "@com_google_mpact-sim//mpact/sim/generic:core", "@com_google_mpact-sim//mpact/sim/generic:instruction", "@com_google_mpact-sim//mpact/sim/generic:program_error", @@ -875,11 +863,8 @@ ":riscv64g_bin_fmt", ":riscv64g_isa", ":riscv_getters", - ":riscv_state", "@com_google_absl//absl/base:no_destructor", "@com_google_absl//absl/container:flat_hash_map", - "@com_google_absl//absl/functional:any_invocable", - "@com_google_absl//absl/log:check", "@com_google_absl//absl/status", "@com_google_absl//absl/status:statusor", "@com_google_absl//absl/strings", @@ -894,7 +879,6 @@ srcs = ["riscv64g_as_main.cc"], copts = ["-O3"], deps = [ - ":riscv64g_bin_fmt", ":riscv64g_encoder", ":riscv64g_isa", "@com_github_serge1_elfio//:elfio", @@ -958,15 +942,8 @@ ":riscv_encoding_common", ":riscv_getters", ":riscv_state", - "@com_google_absl//absl/base", - "@com_google_absl//absl/container:flat_hash_map", - "@com_google_absl//absl/functional:any_invocable", - "@com_google_absl//absl/functional:bind_front", "@com_google_absl//absl/log", "@com_google_absl//absl/strings", - "@com_google_absl//absl/strings:str_format", - "@com_google_absl//absl/types:span", - "@com_google_mpact-sim//mpact/sim/generic:arch_state", "@com_google_mpact-sim//mpact/sim/generic:core", "@com_google_mpact-sim//mpact/sim/generic:instruction", "@com_google_mpact-sim//mpact/sim/generic:program_error",
diff --git a/riscv/riscv32g_encoding.h b/riscv/riscv32g_encoding.h index 7965d40..920e84e 100644 --- a/riscv/riscv32g_encoding.h +++ b/riscv/riscv32g_encoding.h
@@ -20,6 +20,8 @@ #include "absl/container/flat_hash_map.h" #include "absl/functional/any_invocable.h" +#include "mpact/sim/generic/operand_interface.h" +#include "mpact/sim/generic/resource_operand_interface.h" #include "mpact/sim/generic/simple_resource.h" #include "mpact/sim/generic/simple_resource_operand.h" #include "riscv/riscv32g_decoder.h" @@ -31,6 +33,14 @@ namespace riscv { namespace isa32 { +using ::mpact::sim::generic::DestinationOperandInterface; +using ::mpact::sim::generic::PredicateOperandInterface; +using ::mpact::sim::generic::ResourceOperandInterface; +using ::mpact::sim::generic::SimpleResource; +using ::mpact::sim::generic::SimpleResourceDelayLine; +using ::mpact::sim::generic::SimpleResourcePool; +using ::mpact::sim::generic::SourceOperandInterface; + // This class provides the interface between the generated instruction decoder // framework (which is agnostic of the actual bit representation of // instructions) and the instruction representation. This class provides methods @@ -101,7 +111,7 @@ } // Getter. - generic::SimpleResourcePool *resource_pool() const { return resource_pool_; } + SimpleResourcePool *resource_pool() const { return resource_pool_; } const SourceOpGetterMap &source_op_getters() { return source_op_getters_; } const DestOpGetterMap &dest_op_getters() { return dest_op_getters_; } @@ -134,8 +144,8 @@ RiscVState *state_; uint32_t inst_word_; OpcodeEnum opcode_; - generic::SimpleResourceDelayLine *resource_delay_line_ = nullptr; - generic::SimpleResourcePool *resource_pool_ = nullptr; + SimpleResourceDelayLine *resource_delay_line_ = nullptr; + SimpleResourcePool *resource_pool_ = nullptr; }; } // namespace isa32
diff --git a/riscv/riscv64g_as_main.cc b/riscv/riscv64g_as_main.cc index 3893308..c005a5a 100644 --- a/riscv/riscv64g_as_main.cc +++ b/riscv/riscv64g_as_main.cc
@@ -12,6 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. +#include <cstddef> #include <cstdint> #include <fstream> #include <iostream> @@ -61,10 +62,11 @@ RiscV64GAssembler(Riscv64gSlotMatcher* matcher) : label_re_("^(\\S+)\\s*:"), matcher_(matcher) {}; ~RiscV64GAssembler() override = default; - absl::Status Encode(uint64_t address, absl::string_view text, - AddSymbolCallback add_symbol_callback, - ResolverInterface* resolver, std::vector<uint8_t>& bytes, - std::vector<RelocationInfo>& relocations) override { + absl::StatusOr<size_t> Encode( + uint64_t address, absl::string_view text, + AddSymbolCallback add_symbol_callback, ResolverInterface* resolver, + std::vector<uint8_t>& bytes, + std::vector<RelocationInfo>& relocations) override { // First check to see if there is a label, if so, add it to the symbol table // with the current address. std::string label; @@ -83,7 +85,7 @@ for (int i = 0; i < size / 8; ++i) { bytes.push_back(u.b[i]); } - return absl::OkStatus(); + return bytes.size(); } private: