Google Git
Sign in
mpact/mpact-riscv/cd69512240fb2957be2771aeb71fd994bac7b247^!/.
commit
cd69512240fb2957be2771aeb71fd994bac7b247
[log]
author
Tor Jeremiassen <torerik@google.com>
Thu Feb 12 10:54:40 2026 -0600
committer
Tor Jeremiassen <torerik@google.com>
Thu Feb 12 11:00:16 2026 -0600
tree
a20068eaafdaa42e146e59ffa8ebca69c341fb72
parent
2b2fa932c84a8b7dec21bbd052dcd7d1ab12ae5b [diff]
No public description

PiperOrigin-RevId: 869240375
Change-Id: I0d0c81a13754b72ef70c405a5e644db7b444fe38

diff --git a/repos.bzl b/repos.bzl
index 6310023..10eecfa 100644
--- a/repos.bzl
+++ b/repos.bzl

@@ -22,7 +22,7 @@
     if not native.existing_rule("com_google_mpact-sim"):
         http_archive(
             name = "com_google_mpact-sim",
-            sha256 = "11c09c59eadca3a1d54a2fe026e419bdc80037c50dd0bbbc38fa8e112001998c",
-            strip_prefix = "mpact-sim-3cd45f0735627c80593b9ff6fe87033a7c9b9089",
-            url = "https://github.com/google/mpact-sim/archive/3cd45f0735627c80593b9ff6fe87033a7c9b9089.tar.gz",
+            sha256 = "e4115bbe5c5039d442378da745fc7401c79f9e52df590191d872354c7a999c58",
+            strip_prefix = "mpact-sim-4a9e8505f3a02719b076fdee5a838217d770ad89",
+            url = "https://github.com/google/mpact-sim/archive/4a9e8505f3a02719b076fdee5a838217d770ad89.tar.gz",
         )

diff --git a/riscv/BUILD b/riscv/BUILD
index 1db18de..0189fd9 100644
--- a/riscv/BUILD
+++ b/riscv/BUILD

@@ -992,7 +992,6 @@
         ":riscv64g_bin_fmt",
         ":riscv64g_isa",
         ":riscv_getters",
-        "//util/regexp/re2",
         "@com_google_absl//absl/base:no_destructor",
         "@com_google_absl//absl/container:flat_hash_map",
         "@com_google_absl//absl/status",
@@ -1000,6 +999,7 @@
         "@com_google_absl//absl/strings",
         "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
         "@com_google_mpact-sim//mpact/sim/util/asm",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1010,7 +1010,6 @@
     deps = [
         ":riscv64g_encoder",
         ":riscv64g_isa",
-        "//util/regexp/re2",
         "@com_github_serge1_elfio//:elfio",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
@@ -1021,6 +1020,7 @@
         "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
         "@com_google_mpact-sim//mpact/sim/util/asm",
         "@com_google_mpact-sim//mpact/sim/util/asm:simple_assembler",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1240,7 +1240,6 @@
         ":riscv_debug_interface",
         ":riscv_top",
         ":stoull_wrapper",
-        "//util/regexp/re2",
         "@com_google_absl//absl/container:btree",
         "@com_google_absl//absl/container:flat_hash_set",
         "@com_google_absl//absl/functional:any_invocable",
@@ -1252,6 +1251,7 @@
         "@com_google_mpact-sim//mpact/sim/generic:core_debug_interface",
         "@com_google_mpact-sim//mpact/sim/generic:debug_command_shell_interface",
         "@com_google_mpact-sim//mpact/sim/generic:type_helpers",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1300,7 +1300,6 @@
         ":riscv_fp_state",
         ":riscv_state",
         ":riscv_top",
-        "//util/regexp/re2",
         "@com_google_absl//absl/base:log_severity",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
@@ -1318,6 +1317,7 @@
         "@com_google_mpact-sim//mpact/sim/util/memory",
         "@com_google_mpact-sim//mpact/sim/util/program_loader:elf_loader",
         "@com_google_protobuf//:protobuf",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1336,7 +1336,6 @@
         ":riscv_fp_state",
         ":riscv_state",
         ":riscv_top",
-        "//util/regexp/re2",
         "@com_google_absl//absl/base:log_severity",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
@@ -1354,6 +1353,7 @@
         "@com_google_mpact-sim//mpact/sim/util/memory",
         "@com_google_mpact-sim//mpact/sim/util/program_loader:elf_loader",
         "@com_google_protobuf//:protobuf",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1370,7 +1370,6 @@
         ":riscv_fp_state",
         ":riscv_state",
         ":riscv_top",
-        "//util/regexp/re2",
         "@com_google_absl//absl/base:log_severity",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
@@ -1387,6 +1386,7 @@
         "@com_google_mpact-sim//mpact/sim/util/memory",
         "@com_google_mpact-sim//mpact/sim/util/program_loader:elf_loader",
         "@com_google_protobuf//:protobuf",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1404,7 +1404,6 @@
         ":riscv_fp_state",
         ":riscv_state",
         ":riscv_top",
-        "//util/regexp/re2",
         "@com_google_absl//absl/base:log_severity",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
@@ -1422,6 +1421,7 @@
         "@com_google_mpact-sim//mpact/sim/util/memory",
         "@com_google_mpact-sim//mpact/sim/util/program_loader:elf_loader",
         "@com_google_protobuf//:protobuf",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1468,7 +1468,6 @@
         "riscv_plic.h",
     ],
     deps = [
-        "//util/regexp/re2",
         "@com_google_absl//absl/container:btree",
         "@com_google_absl//absl/log",
         "@com_google_absl//absl/numeric:bits",
@@ -1477,6 +1476,7 @@
         "@com_google_mpact-sim//mpact/sim/generic:core",
         "@com_google_mpact-sim//mpact/sim/generic:instruction",
         "@com_google_mpact-sim//mpact/sim/util/memory",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 
@@ -1537,12 +1537,12 @@
         ":debug_command_shell",
         ":riscv_top",
         ":stoull_wrapper",
-        "//util/regexp/re2",
         "@com_google_absl//absl/functional:any_invocable",
         "@com_google_absl//absl/status",
         "@com_google_absl//absl/strings",
         "@com_google_absl//absl/strings:string_view",
         "@com_google_mpact-sim//mpact/sim/util/memory",
+        "@com_googlesource_code_re2//:re2",
     ],
 )
 

diff --git a/riscv/debug_command_shell.cc b/riscv/debug_command_shell.cc
index efa41bd..0893446 100644
--- a/riscv/debug_command_shell.cc
+++ b/riscv/debug_command_shell.cc

@@ -33,10 +33,10 @@
 #include "mpact/sim/generic/core_debug_interface.h"
 #include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/type_helpers.h"
+#include "re2/re2.h"
 #include "riscv/riscv_debug_interface.h"
 #include "riscv/riscv_top.h"
 #include "riscv/stoull_wrapper.h"
-#include "util/regexp/re2/re2.h"
 
 namespace mpact {
 namespace sim {

diff --git a/riscv/debug_command_shell.h b/riscv/debug_command_shell.h
index cba4b7f..eba421d 100644
--- a/riscv/debug_command_shell.h
+++ b/riscv/debug_command_shell.h

@@ -31,7 +31,7 @@
 #include "absl/strings/string_view.h"
 #include "mpact/sim/generic/core_debug_interface.h"
 #include "mpact/sim/generic/debug_command_shell_interface.h"
-#include "util/regexp/re2/re2.h"
+#include "re2/re2.h"
 
 namespace mpact {
 namespace sim {

diff --git a/riscv/riscv32_decoder.cc b/riscv/riscv32_decoder.cc
index 809aed0..79b2264 100644
--- a/riscv/riscv32_decoder.cc
+++ b/riscv/riscv32_decoder.cc

@@ -41,7 +41,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa32::OpcodeEnum,
                                            isa32::RiscV32GEncoding,
                                            isa32::RiscV32GInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32Decoder::DecodeInstruction(uint64_t address) {

diff --git a/riscv/riscv32g_bitmanip_decoder.cc b/riscv/riscv32g_bitmanip_decoder.cc
index f3b3023..48f3b94 100644
--- a/riscv/riscv32g_bitmanip_decoder.cc
+++ b/riscv/riscv32g_bitmanip_decoder.cc

@@ -42,7 +42,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa32gzb::OpcodeEnum,
                                            isa32gzb::RiscV32GZBEncoding,
                                            isa32gzb::RiscV32GZBInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32GBitmanipDecoder::DecodeInstruction(

diff --git a/riscv/riscv32g_bitmanip_decoder.h b/riscv/riscv32g_bitmanip_decoder.h
index c3e957a..4378450 100644
--- a/riscv/riscv32g_bitmanip_decoder.h
+++ b/riscv/riscv32g_bitmanip_decoder.h

@@ -18,7 +18,6 @@
 #include <cstdint>
 #include <memory>
 
-#include "mpact/sim/generic/data_buffer.h"
 #include "mpact/sim/generic/decoder_interface.h"
 #include "mpact/sim/generic/instruction.h"
 #include "mpact/sim/generic/type_helpers.h"
@@ -80,7 +79,6 @@
                                       isa32gzb::RiscV32GZBInstructionSet>>
       decoder_;
   util::MemoryInterface* memory_;
-  generic::DataBuffer* inst_db_;
   std::unique_ptr<isa32gzb::RiscV32GZBEncoding> riscv_encoding_;
   std::unique_ptr<RV32GZBIsaFactory> riscv_isa_factory_;
   std::unique_ptr<isa32gzb::RiscV32GZBInstructionSet> riscv_isa_;

diff --git a/riscv/riscv32g_vec_decoder.cc b/riscv/riscv32g_vec_decoder.cc
index 76d0694..41056b5 100644
--- a/riscv/riscv32g_vec_decoder.cc
+++ b/riscv/riscv32g_vec_decoder.cc

@@ -42,7 +42,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa32v::OpcodeEnum,
                                            isa32v::RiscV32GVecEncoding,
                                            isa32v::RiscV32GVInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32GVecDecoder::DecodeInstruction(uint64_t address) {

diff --git a/riscv/riscv32gzb_vec_decoder.cc b/riscv/riscv32gzb_vec_decoder.cc
index e88e01e..6f8c958 100644
--- a/riscv/riscv32gzb_vec_decoder.cc
+++ b/riscv/riscv32gzb_vec_decoder.cc

@@ -44,7 +44,7 @@
   decoder_ = std::make_unique<RiscVGenericDecoder<
       RiscVState, isa32gvzb::OpcodeEnum, isa32gvzb::RiscV32GZBVecEncoding,
       isa32gvzb::RiscV32GVZBInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+      state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV32GZBVecDecoder::DecodeInstruction(

diff --git a/riscv/riscv64_decoder.cc b/riscv/riscv64_decoder.cc
index 845dc54..1a62da6 100644
--- a/riscv/riscv64_decoder.cc
+++ b/riscv/riscv64_decoder.cc

@@ -46,7 +46,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa64::OpcodeEnum,
                                            isa64::RiscV64GEncoding,
                                            isa64::RiscV64GInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64Decoder::DecodeInstruction(uint64_t address) {

diff --git a/riscv/riscv64g_as_main.cc b/riscv/riscv64g_as_main.cc
index b3b65ba..9c266db 100644
--- a/riscv/riscv64g_as_main.cc
+++ b/riscv/riscv64g_as_main.cc

@@ -34,9 +34,9 @@
 #include "mpact/sim/util/asm/opcode_assembler_interface.h"
 #include "mpact/sim/util/asm/resolver_interface.h"
 #include "mpact/sim/util/asm/simple_assembler.h"
+#include "re2/re2.h"
 #include "riscv/riscv64g_bin_encoder_interface.h"
 #include "riscv/riscv64g_encoder.h"
-#include "util/regexp/re2/re2.h"
 
 using ::mpact::sim::riscv::isa64::RiscV64GBinEncoderInterface;
 using ::mpact::sim::riscv::isa64::Riscv64gSlotMatcher;

diff --git a/riscv/riscv64g_bitmanip_decoder.cc b/riscv/riscv64g_bitmanip_decoder.cc
index 826a39f..d5e8d6a 100644
--- a/riscv/riscv64g_bitmanip_decoder.cc
+++ b/riscv/riscv64g_bitmanip_decoder.cc

@@ -42,7 +42,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa64gzb::OpcodeEnum,
                                            isa64gzb::RiscV64GZBEncoding,
                                            isa64gzb::RiscV64GZBInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64GBitmanipDecoder::DecodeInstruction(

diff --git a/riscv/riscv64g_vec_decoder.cc b/riscv/riscv64g_vec_decoder.cc
index 007c8b8..0f88648 100644
--- a/riscv/riscv64g_vec_decoder.cc
+++ b/riscv/riscv64g_vec_decoder.cc

@@ -42,7 +42,7 @@
       std::make_unique<RiscVGenericDecoder<RiscVState, isa64v::OpcodeEnum,
                                            isa64v::RiscV64GVecEncoding,
                                            isa64v::RiscV64GVInstructionSet>>(
-          state, memory, riscv_encoding_.get(), riscv_isa_.get());
+          state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64GVecDecoder::DecodeInstruction(uint64_t address) {

diff --git a/riscv/riscv64gzb_vec_decoder.cc b/riscv/riscv64gzb_vec_decoder.cc
index f621fa3..0ca35b1 100644
--- a/riscv/riscv64gzb_vec_decoder.cc
+++ b/riscv/riscv64gzb_vec_decoder.cc

@@ -41,7 +41,7 @@
   decoder_ = std::make_unique<RiscVGenericDecoder<
       RiscVState, isa64gvzb::OpcodeEnum, isa64gvzb::RiscV64GZBVecEncoding,
       isa64gvzb::RiscV64GVZBInstructionSet>>(
-      state, memory, riscv_encoding_.get(), riscv_isa_.get());
+      state_, memory_, riscv_encoding_.get(), riscv_isa_.get());
 }
 
 generic::Instruction* RiscV64GZBVecDecoder::DecodeInstruction(

diff --git a/riscv/riscv_bin_setters.cc b/riscv/riscv_bin_setters.cc
index df4fa2b..721c345 100644
--- a/riscv/riscv_bin_setters.cc
+++ b/riscv/riscv_bin_setters.cc

@@ -23,7 +23,7 @@
 #include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
 #include "mpact/sim/generic/type_helpers.h"
-#include "util/regexp/re2/re2.h"
+#include "re2/re2.h"
 
 namespace mpact {
 namespace sim {

diff --git a/riscv/riscv_bin_setters.h b/riscv/riscv_bin_setters.h
index 9b04d63..7c4eae7 100644
--- a/riscv/riscv_bin_setters.h
+++ b/riscv/riscv_bin_setters.h

@@ -29,8 +29,8 @@
 #include "absl/strings/string_view.h"
 #include "mpact/sim/util/asm/opcode_assembler_interface.h"
 #include "mpact/sim/util/asm/resolver_interface.h"
+#include "re2/re2.h"
 #include "riscv/riscv_getter_helpers.h"
-#include "util/regexp/re2/re2.h"
 
 // This file contains various setters for the RiscV binary encoder that is used
 // by the assembler to map from operand text strings to integer values.

diff --git a/riscv/riscv_instrumentation_control.cc b/riscv/riscv_instrumentation_control.cc
index 66c7dc1..cea4aac 100644
--- a/riscv/riscv_instrumentation_control.cc
+++ b/riscv/riscv_instrumentation_control.cc

@@ -24,10 +24,10 @@
 #include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
 #include "mpact/sim/util/memory/memory_use_profiler.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv_top.h"
 #include "riscv/stoull_wrapper.h"
-#include "util/regexp/re2/re2.h"
 
 namespace mpact::sim::riscv {
 

diff --git a/riscv/riscv_instrumentation_control.h b/riscv/riscv_instrumentation_control.h
index d82c64e..911eb08 100644
--- a/riscv/riscv_instrumentation_control.h
+++ b/riscv/riscv_instrumentation_control.h

@@ -21,9 +21,9 @@
 
 #include "absl/strings/string_view.h"
 #include "mpact/sim/util/memory/memory_use_profiler.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv_top.h"
-#include "util/regexp/re2/re2.h"
 
 namespace mpact::sim::riscv {
 

diff --git a/riscv/riscv_plic.cc b/riscv/riscv_plic.cc
index 2671ce5..0b9be95 100644
--- a/riscv/riscv_plic.cc
+++ b/riscv/riscv_plic.cc

@@ -22,7 +22,7 @@
 #include "absl/status/status.h"
 #include "absl/strings/str_cat.h"
 #include "absl/strings/string_view.h"
-#include "util/regexp/re2/re2.h"
+#include "re2/re2.h"
 
 namespace mpact {
 namespace sim {

diff --git a/riscv/rv32g_sim.cc b/riscv/rv32g_sim.cc
index 03ca5e2..a45c698 100644
--- a/riscv/rv32g_sim.cc
+++ b/riscv/rv32g_sim.cc

@@ -47,6 +47,7 @@
 #include "mpact/sim/util/memory/memory_interface.h"
 #include "mpact/sim/util/memory/memory_watcher.h"
 #include "mpact/sim/util/program_loader/elf_program_loader.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv32_decoder.h"
 #include "riscv/riscv32_htif_semihost.h"
@@ -59,7 +60,6 @@
 #include "riscv/riscv_state.h"
 #include "riscv/riscv_top.h"
 #include "src/google/protobuf/text_format.h"
-#include "util/regexp/re2/re2.h"
 
 using ::mpact::sim::generic::Instruction;
 using ::mpact::sim::proto::ComponentData;

diff --git a/riscv/rv32gv_sim.cc b/riscv/rv32gv_sim.cc
index 9a1b6a2..36d52fb 100644
--- a/riscv/rv32gv_sim.cc
+++ b/riscv/rv32gv_sim.cc

@@ -47,6 +47,7 @@
 #include "mpact/sim/util/memory/memory_interface.h"
 #include "mpact/sim/util/memory/memory_watcher.h"
 #include "mpact/sim/util/program_loader/elf_program_loader.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv32_htif_semihost.h"
 #include "riscv/riscv32g_vec_decoder.h"
@@ -60,7 +61,6 @@
 #include "riscv/riscv_top.h"
 #include "riscv/riscv_vector_state.h"
 #include "src/google/protobuf/text_format.h"
-#include "util/regexp/re2/re2.h"
 
 using ::mpact::sim::generic::Instruction;
 using ::mpact::sim::proto::ComponentData;

diff --git a/riscv/rv64g_sim.cc b/riscv/rv64g_sim.cc
index 4193527..fe80fcc 100644
--- a/riscv/rv64g_sim.cc
+++ b/riscv/rv64g_sim.cc

@@ -46,6 +46,7 @@
 #include "mpact/sim/util/memory/memory_interface.h"
 #include "mpact/sim/util/memory/memory_watcher.h"
 #include "mpact/sim/util/program_loader/elf_program_loader.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv64_decoder.h"
 #include "riscv/riscv_arm_semihost.h"
@@ -56,7 +57,6 @@
 #include "riscv/riscv_state.h"
 #include "riscv/riscv_top.h"
 #include "src/google/protobuf/text_format.h"
-#include "util/regexp/re2/re2.h"
 
 using ::mpact::sim::generic::Instruction;
 using ::mpact::sim::proto::ComponentData;

diff --git a/riscv/rv64gv_sim.cc b/riscv/rv64gv_sim.cc
index 7215928..2bac95d 100644
--- a/riscv/rv64gv_sim.cc
+++ b/riscv/rv64gv_sim.cc

@@ -47,6 +47,7 @@
 #include "mpact/sim/util/memory/memory_interface.h"
 #include "mpact/sim/util/memory/memory_watcher.h"
 #include "mpact/sim/util/program_loader/elf_program_loader.h"
+#include "re2/re2.h"
 #include "riscv/debug_command_shell.h"
 #include "riscv/riscv64g_vec_decoder.h"
 #include "riscv/riscv64gzb_vec_decoder.h"
@@ -59,7 +60,6 @@
 #include "riscv/riscv_top.h"
 #include "riscv/riscv_vector_state.h"
 #include "src/google/protobuf/text_format.h"
-#include "util/regexp/re2/re2.h"
 
 using ::mpact::sim::generic::Instruction;
 using ::mpact::sim::proto::ComponentData;