riscv/riscv_zicond.isa

// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// This file contains the ISA description for the RiscV32/64 conditional zeroing
// extension.

includes {
  #include "riscv/riscv_zicond_instructions.h"
}

disasm widths = {-18};

slot riscv32_zicond {
  default size = 4;
  default opcode =
    disasm: "Illegal instruction at 0x%(@:08x)",
    semfunc: "&RiscVIllegalInstruction";
  resources ThreeOp = { next_pc, rs1, rs2 : rd[..rd]};
  opcodes {
    czero_eqz{: rs1, rs2: rd},
      resources: ThreeOp,
      disasm: "czero.eqz", "%rd, %rs1, %rs2",
      semfunc: "&RV32::RiscVCzeroEqz";
    czero_nez{: rs1, rs2: rd},
      resources: ThreeOp,
      disasm: "czero.nez", "%rd, %rs1, %rs2",
      semfunc: "&RV32::RiscVCzeroNez";
  }
}

slot riscv64_zicond : riscv32_zicond{
  opcodes {
    czero_eqz = override, semfunc: "&RV64::RiscVCzeroEqz";
    czero_nez = override, semfunc: "&RV64::RiscVCzeroNez";
  }
}