No public description PiperOrigin-RevId: 726269643 Change-Id: I192b16a2e42758f7cb31682711fe1927216b091a
diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt index 701a2b3..c33f0f2 100644 --- a/riscv/riscv32g.bin_fmt +++ b/riscv/riscv32g.bin_fmt
@@ -414,6 +414,7 @@ cfsw : CS : func3 == 0b111, op == 0b00; cnop : CI : func3 == 0b000, imm1 == 0, rs1 == 0, imm5 == 0, op == 0b01; caddi : CI : func3 == 0b000, imm6 != 0, rd != 0, op == 0b01; + caddi_hint: CI : func3 == 0b000, imm6 == 0, rd != 0, op == 0b01; cjal : CJ : func3 == 0b001, op == 0b01; cli : CI : func3 == 0b010, rd != 0, op == 0b01; caddi16sp : CI : func3 == 0b011, rd == 2, op == 0b01;
diff --git a/riscv/riscv32g.isa b/riscv/riscv32g.isa index 31e1537..828c820 100644 --- a/riscv/riscv32g.isa +++ b/riscv/riscv32g.isa
@@ -794,6 +794,9 @@ resources: {next_pc, rd : rd[0..]}, disasm: "addi", "%rd, %rd, %I_ci_imm6", semfunc: "&RV32::RiscVIAdd"; + caddi_hint{}, + disasm: "caddi_hint", + semfunc: "&RiscVINop"; caddi16sp{: x2, I_ci_imm6x16 : x2}, resources: {next_pc, x2 : x2[0..]}, disasm: "addi", "%x2, %x2, %(I_ci_imm6x16:d)",
diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt index 7e331c0..0307670 100644 --- a/riscv/riscv64g.bin_fmt +++ b/riscv/riscv64g.bin_fmt
@@ -477,6 +477,7 @@ csd : CS : func3 == 0b111, op == 0b00; cnop : CI : func3 == 0b000, imm1 == 0, rs1 == 0, imm5 == 0, op == 0b01; caddi : CI : func3 == 0b000, imm6 != 0, rd != 0, op == 0b01; + caddi_hint: CI : func3 == 0b000, imm6 == 0, rd != 0, op == 0b01; caddiw : CI : func3 == 0b001, rs1 != 0, op == 0b01; cli : CI : func3 == 0b010, rd != 0, op == 0b01; caddi16sp : CI : func3 == 0b011, rd == 2, ci_imm10 != 0, op == 0b01;
diff --git a/riscv/riscv64g.isa b/riscv/riscv64g.isa index 78f92cf..9370734 100644 --- a/riscv/riscv64g.isa +++ b/riscv/riscv64g.isa
@@ -971,6 +971,10 @@ resources: {next_pc, rd : rd[0..]}, disasm: "c.addi", "%rd, %rd, %I_ci_imm6", semfunc: "&RV64::RiscVIAdd"; + caddi_hint{: rd, I_ci_imm6 : rd}, + resources: {next_pc, rd : rd[0..]}, + disasm: "caddi_hint", + semfunc: "&RiscVINop"; caddiw{: rd, I_ci_imm6 : rd}, resources: {next_pc, rd : rd[0..]}, disasm: "c.addiw", "%rd, %rd, %I_ci_imm6",