No public description PiperOrigin-RevId: 703339900 Change-Id: If34cd1849dbbcf9f34f736e4f43dd6c40c9981c7

diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt
index 4123920..3d984b8 100644
--- a/riscv/riscv32g.bin_fmt
+++ b/riscv/riscv32g.bin_fmt

@@ -436,6 +436,7 @@
   cebreak   : CR : func4 == 0b1001, rs1 == 0, rs2 == 0, op == 0b10;
   cjalr     : CR : func4 == 0b1001, rs1 != 0, rs2 == 0, op == 0b10;
   cadd      : CR : func4 == 0b1001, rs1 != 0, rs2 != 0, op == 0b10;
+  cadd_hint : CR : func4 == 0b1001, rs1 == 0,rs2 != 0, op == 0b10;
   cfsdsp    : CSS: func3 == 0b101, op == 0b10;
   cswsp     : CSS: func3 == 0b110, op == 0b10;
   cfswsp    : CSS: func3 == 0b111, op == 0b10;

diff --git a/riscv/riscv32g.isa b/riscv/riscv32g.isa
index 10fcc09..a1f9fee 100644
--- a/riscv/riscv32g.isa
+++ b/riscv/riscv32g.isa

@@ -823,6 +823,9 @@
       resources: {next_pc, crs2, rd : rd[0..]},
       disasm: "add", "%rd, %rd, %crs2",
       semfunc: "&RV32::RiscVIAdd";
+    cadd_hint{},
+      disasm: "cadd_hint",
+      semfunc: "&RiscVINop";
     cand{: c3rs1, c3rs2 : c3rs1},
       resources: {next_pc, c3rs1, c3rs2 : c3rs1[0..]},
       disasm: "and", "%c3rs1, %c3rs1, %c3rs2",

diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt
index 9e52660..57054f3 100644
--- a/riscv/riscv64g.bin_fmt
+++ b/riscv/riscv64g.bin_fmt

@@ -501,6 +501,7 @@
   cebreak   : CR : func4 == 0b1001, rs1 == 0, rs2 == 0, op == 0b10;
   cjalr     : CR : func4 == 0b1001, rs1 != 0, rs2 == 0, op == 0b10;
   cadd      : CR : func4 == 0b1001, rs1 != 0, rs2 != 0, op == 0b10;
+  cadd_hint : CR : func4 == 0b1001, rs1 == 0, rs2 != 0, op == 0b10;
   cfsdsp    : CSS: func3 == 0b101, op == 0b10;
   cswsp     : CSS: func3 == 0b110, op == 0b10;
   csdsp     : CSS: func3 == 0b111, op == 0b10;

diff --git a/riscv/riscv64g.isa b/riscv/riscv64g.isa
index 8d7fcff..7fcbc7f 100644
--- a/riscv/riscv64g.isa
+++ b/riscv/riscv64g.isa

@@ -1004,6 +1004,9 @@
       resources: {next_pc, crs2, rd : rd[0..]},
       disasm: "c.add", "%rd, %rd, %crs2",
       semfunc: "&RV64::RiscVIAdd";
+    cadd_hint{},
+      disasm: "cadd_hint",
+      semfunc: "&RiscVINop";
     cand{: c3rs1, c3rs2 : c3rs1},
       resources: {next_pc, c3rs1, c3rs2 : c3rs1[0..]},
       disasm: "c.and", "%c3rs1, %c3rs1, %c3rs2",