No public description PiperOrigin-RevId: 772175199 Change-Id: I71cbab07bb639b79d5ac49d62765e2c04f632d8a
diff --git a/riscv/BUILD b/riscv/BUILD index ca708da..dc6da7b 100644 --- a/riscv/BUILD +++ b/riscv/BUILD
@@ -38,6 +38,8 @@ "riscv64v.isa", "riscv64zb.bin_fmt", "riscv64zb.isa", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", "riscv_vector.isa", ]) @@ -366,7 +368,8 @@ src = "riscv32g.bin_fmt", decoder_name = "RiscV32G", includes = [ - "riscv32v.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], deps = [ ":riscv32g_isa", @@ -399,6 +402,8 @@ includes = [ "riscv32g.bin_fmt", "riscv32zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", ], prefix = "riscv32gv", @@ -431,6 +436,8 @@ includes = [ "riscv32g.bin_fmt", "riscv32zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], prefix = "riscv32gzb", deps = [ @@ -464,6 +471,8 @@ includes = [ "riscv32g.bin_fmt", "riscv32zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", ], prefix = "riscv32gvzb", @@ -506,6 +515,8 @@ "riscv32g.bin_fmt", "riscv32v.bin_fmt", "riscv32zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_zc.bin_fmt", "riscv_zhintpause.bin_fmt", "riscv_zicbop.bin_fmt", @@ -536,6 +547,8 @@ src = "riscv64g.bin_fmt", decoder_name = "RiscV64G", includes = [ + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], prefix = "riscv64g", deps = [ @@ -571,6 +584,8 @@ "riscv32zb.bin_fmt", "riscv64g.bin_fmt", "riscv64zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", ], prefix = "riscv64gv", @@ -607,6 +622,8 @@ "riscv32zb.bin_fmt", "riscv64g.bin_fmt", "riscv64zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", ], prefix = "riscv64gvzb", @@ -641,6 +658,8 @@ "riscv32zb.bin_fmt", "riscv64g.bin_fmt", "riscv64zb.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], prefix = "riscv64gzb", deps = [ @@ -669,6 +688,8 @@ decoder_name = "ZVBB", includes = [ "riscv32g.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", "riscv_vector.bin_fmt", ], prefix = "zvbb", @@ -709,6 +730,8 @@ decoder_name = "ZFH", includes = [ "riscv32g.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], prefix = "zfh32", deps = [ @@ -722,6 +745,8 @@ decoder_name = "ZFH", includes = [ "riscv32g.bin_fmt", + "riscv_format16.bin_fmt", + "riscv_format32.bin_fmt", ], prefix = "zfh64", deps = [
diff --git a/riscv/riscv32g.bin_fmt b/riscv/riscv32g.bin_fmt index c33f0f2..9e8c4e6 100644 --- a/riscv/riscv32g.bin_fmt +++ b/riscv/riscv32g.bin_fmt
@@ -23,111 +23,8 @@ RiscVCInst16; }; -format Inst32Format[32] { - fields: - unsigned bits[25]; - unsigned opcode[7]; -}; - -format RType[32] : Inst32Format { - fields: - unsigned func7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned r_uimm5[5] = rs2; -}; - -format R4Type[32] : Inst32Format { - fields: - unsigned rs3[5]; - unsigned func2[2]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format IType[32] : Inst32Format { - fields: - signed imm12[12]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned u_imm12[12] = imm12; - unsigned i_uimm5[5] = rs1; -}; - -format SType[32] : Inst32Format { - fields: - unsigned imm7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned imm5[5]; - unsigned opcode[7]; - overlays: - signed s_imm[12] = imm7, imm5; -}; - -format BType[32] : Inst32Format { - fields: - unsigned imm7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned imm5[5]; - unsigned opcode[7]; - overlays: - signed b_imm[13] = imm7[6], imm5[0], imm7[5..0], imm5[4..1], 0b0; -}; - -format UType[32] : Inst32Format { - fields: - unsigned imm20[20]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned u_imm[32] = imm20, 0b0000'0000'0000; -}; - -format JType[32] : Inst32Format { - fields: - unsigned imm20[20]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - signed j_imm[21] = imm20[19, 7..0, 8, 18..9], 0b0; -}; - -format Fence[32] : Inst32Format { - fields: - unsigned fm[4]; - unsigned pred[4]; - unsigned succ[4]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format AType[32] : Inst32Format { - fields: - unsigned func5[5]; - unsigned aq[1]; - unsigned rl[1]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; +#include "riscv/riscv_format32.bin_fmt" +#include "riscv/riscv_format16.bin_fmt" instruction group RiscVGInst32[32] : Inst32Format { lui : UType : opcode == 0b011'0111; @@ -279,130 +176,6 @@ sfence_vma_nn : RType : func7 == 0b000'1001, rs2 != 0, rs1 != 0, func3 == 0, rd == 0, opcode == 0b111'0011; }; -// Compact instruction formats. - -format Inst16Format[16] { - fields: - unsigned func3[3]; - unsigned bits[11]; - unsigned op[2]; -}; - -format CSS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm6[6]; - unsigned rs2[5]; - unsigned op[2]; - overlays: - unsigned css_imm_w[8] = imm6[1..0], imm6[5..2], 0b00; - unsigned css_imm_d[9] = imm6[2..0], imm6[5..3], 0b000; -}; - -format CL[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned cl_rs1[5] = 0b01, rs1p; - unsigned cl_rd[5] = 0b01, rdp; - unsigned cl_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cl_imm_d[8] = imm2, imm3, 0b000; -}; - -format CS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned cs_rs1[5] = 0b01, rs1p; - unsigned cs_rs2[5] = 0b01, rs2p; - unsigned cs_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cs_imm_d[8] = imm2, imm3, 0b000; -}; - -format CJ[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm11[11]; - unsigned op[2]; - overlays: - signed jimm[12] = imm11[10, 6, 8..7, 4, 5, 0, 9, 3..1], 0b0; -}; - -format CR[16] : Inst16Format { - fields: - unsigned func4[4]; - unsigned rs1[5]; - unsigned rs2[5]; - unsigned op[2]; -}; - -format CB[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned func2[2] = [11, 10]; - unsigned func5[5] = [12..10, 6..5]; - unsigned shamt[6] = [12, 6..2]; - unsigned rs2p[3] = [4..2]; - unsigned rs2[5] = 0b10, [4..2]; - signed bimm[9] = imm3[2], imm5[4..3, 0], imm3[1..0], imm5[2..1], 0b0; -}; - -format CI[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm1[1]; - unsigned rs1[5]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned rd[5] = rs1; - signed imm6[6] = imm1, imm5; - unsigned uimm6[6] = imm1, imm5; - signed imm18[18] = imm1, imm5, 0b0000'0000'0000; - signed ci_imm10[10] = imm1, imm5[2..1, 3, 0, 4], 0b0000; - unsigned ci_imm_w[8] = imm5[1..0], imm1, imm5[4..2], 0b00; - unsigned ci_imm_d[9] = imm5[2..0], imm1, imm5[4..3], 0b000; -}; - -format CIW[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm8[8]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned rd[5] = 0b01, rdp; - unsigned ciw_imm10[10] = imm8[5..2, 7..6, 0, 1], 0b00; -}; - -format CA[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func2[2]; - unsigned fs2p[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, fs2p; - unsigned rd[5] = 0b01, rs1p; -}; - // Compact instruction encodings. instruction group RiscVCInst16[16] : Inst16Format { caddi4spn : CIW: func3 == 0b000, op == 0b00, imm8 != 0;
diff --git a/riscv/riscv32v.bin_fmt b/riscv/riscv32v.bin_fmt index 856c33c..f5eb8f8 100644 --- a/riscv/riscv32v.bin_fmt +++ b/riscv/riscv32v.bin_fmt
@@ -37,6 +37,7 @@ // Keep this separate (different base format). RiscVCInst16; } + #include "riscv/riscv32zb.bin_fmt" #include "riscv/riscv32g.bin_fmt" #include "riscv/riscv_vector.bin_fmt"
diff --git a/riscv/riscv64g.bin_fmt b/riscv/riscv64g.bin_fmt index 0307670..69e3062 100644 --- a/riscv/riscv64g.bin_fmt +++ b/riscv/riscv64g.bin_fmt
@@ -23,132 +23,8 @@ RiscVCInst16; }; -format Inst32Format[32] { - fields: - unsigned bits[25]; - unsigned opcode[7]; -}; - -format RType[32] : Inst32Format { - fields: - unsigned func7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned r_uimm5[5] = rs2; -}; - -// Format for shift immediate for RV64, note 6 bit immediate. -format RSType[32] : Inst32Format { - fields: - unsigned func6[6]; - unsigned r_uimm6[6]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format R4Type[32] : Inst32Format { - fields: - unsigned rs3[5]; - unsigned func2[2]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format IType[32] : Inst32Format { - fields: - signed imm12[12]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned u_imm12[12] = imm12; - unsigned i_uimm5[5] = rs1; -}; - -format SType[32] : Inst32Format { - fields: - unsigned imm7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned imm5[5]; - unsigned opcode[7]; - overlays: - signed s_imm[12] = imm7, imm5; -}; - -format BType[32] : Inst32Format { - fields: - unsigned imm7[7]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned imm5[5]; - unsigned opcode[7]; - overlays: - signed b_imm[13] = imm7[6], imm5[0], imm7[5..0], imm5[4..1], 0b0; -}; - -format UType[32] : Inst32Format { - fields: - unsigned imm20[20]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned u_imm[32] = imm20, 0b0000'0000'0000; - signed s_imm[32] = imm20, 0b0000'0000'0000; -}; - -format JType[32] : Inst32Format { - fields: - signed imm20[20]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - signed j_imm[21] = imm20[19, 7..0, 8, 18..9], 0b0; -}; - -format Fence[32] : Inst32Format { - fields: - unsigned fm[4]; - unsigned pred[4]; - unsigned succ[4]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format AType[32] : Inst32Format { - fields: - unsigned func5[5]; - unsigned aq[1]; - unsigned rl[1]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; - -format F12Type[32] : Inst32Format { - fields: - unsigned func12[12]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; -}; +#include "riscv/riscv_format32.bin_fmt" +#include "riscv/riscv_format16.bin_fmt" instruction group RiscVGInst32[32] : Inst32Format { lui : UType : opcode == 0b011'0111; @@ -342,130 +218,6 @@ sfence_vma_nn : RType : func7 == 0b000'1001, rs2 != 0, rs1 != 0, func3 == 0, rd == 0, opcode == 0b111'0011; }; -// Compact instruction formats. - -format Inst16Format[16] { - fields: - unsigned func3[3]; - unsigned bits[11]; - unsigned op[2]; -}; - -format CSS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm6[6]; - unsigned rs2[5]; - unsigned op[2]; - overlays: - unsigned css_imm_w[8] = imm6[1..0], imm6[5..2], 0b00; - unsigned css_imm_d[9] = imm6[2..0], imm6[5..3], 0b000; -}; - -format CL[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned cl_rs1[5] = 0b01, rs1p; - unsigned cl_rd[5] = 0b01, rdp; - unsigned cl_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cl_imm_d[8] = imm2, imm3, 0b000; -}; - -format CS[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm2[2]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned cs_rs1[5] = 0b01, rs1p; - unsigned cs_rs2[5] = 0b01, rs2p; - unsigned cs_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; - unsigned cs_imm_d[8] = imm2, imm3, 0b000; -}; - -format CJ[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm11[11]; - unsigned op[2]; - overlays: - signed jimm[12] = imm11[10, 6, 8..7, 4, 5, 0, 9, 3..1], 0b0; -}; - -format CR[16] : Inst16Format { - fields: - unsigned func4[4]; - unsigned rs1[5]; - unsigned rs2[5]; - unsigned op[2]; -}; - -format CB[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm3[3]; - unsigned rs1p[3]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned func2[2] = [11, 10]; - unsigned func5[5] = [12..10, 6..5]; - unsigned shamt[6] = [12, 6..2]; - unsigned rs2p[3] = [4..2]; - unsigned rs2[5] = 0b10, [4..2]; - signed bimm[9] = imm3[2], imm5[4..3, 0], imm3[1..0], imm5[2..1], 0b0; -}; - -format CI[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm1[1]; - unsigned rs1[5]; - unsigned imm5[5]; - unsigned op[2]; - overlays: - unsigned rd[5] = rs1; - signed imm6[6] = imm1, imm5; - unsigned uimm6[6] = imm1, imm5; - signed imm18[18] = imm1, imm5, 0b0000'0000'0000; - signed ci_imm10[10] = imm1, imm5[2..1, 3, 0, 4], 0b0000; - unsigned ci_imm_w[8] = imm5[1..0], imm1, imm5[4..2], 0b00; - unsigned ci_imm_d[9] = imm5[2..0], imm1, imm5[4..3], 0b000; -}; - -format CIW[16] : Inst16Format { - fields: - unsigned func3[3]; - unsigned imm8[8]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned rd[5] = 0b01, rdp; - unsigned ciw_imm10[10] = imm8[5..2, 7..6, 0, 1], 0b00; -}; - -format CA[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func2[2]; - unsigned fs2p[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, fs2p; - unsigned rd[5] = 0b01, rs1p; -}; - // Compact instruction encodings. instruction group RiscVCInst16[16] : Inst16Format { caddi4spn : CIW : func3 == 0b000, op == 0b00, imm8 != 0;
diff --git a/riscv/riscv_format16.bin_fmt b/riscv/riscv_format16.bin_fmt new file mode 100644 index 0000000..87e9518 --- /dev/null +++ b/riscv/riscv_format16.bin_fmt
@@ -0,0 +1,240 @@ +// Copyright 2025 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#once + +// This file defines the 16 bit instruction formats for the RISC-V encodings. + + +format Inst16Format[16] { + fields: + unsigned func3[3]; + unsigned bits[11]; + unsigned op[2]; +}; + +format CSS[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm6[6]; + unsigned rs2[5]; + unsigned op[2]; + overlays: + unsigned css_imm_w[8] = imm6[1..0], imm6[5..2], 0b00; + unsigned css_imm_d[9] = imm6[2..0], imm6[5..3], 0b000; +}; + +format CL[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm3[3]; + unsigned rs1p[3]; + unsigned imm2[2]; + unsigned rdp[3]; + unsigned op[2]; + overlays: + unsigned cl_rs1[5] = 0b01, rs1p; + unsigned cl_rd[5] = 0b01, rdp; + unsigned cl_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; + unsigned cl_imm_d[8] = imm2, imm3, 0b000; +}; + +format CS[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm3[3]; + unsigned rs1p[3]; + unsigned imm2[2]; + unsigned rs2p[3]; + unsigned op[2]; + overlays: + unsigned cs_rs1[5] = 0b01, rs1p; + unsigned cs_rs2[5] = 0b01, rs2p; + unsigned cs_imm_w[7] = imm2[0], imm3, imm2[1], 0b00; + unsigned cs_imm_d[8] = imm2, imm3, 0b000; +}; + +format CJ[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm11[11]; + unsigned op[2]; + overlays: + signed jimm[12] = imm11[10, 6, 8..7, 4, 5, 0, 9, 3..1], 0b0; +}; + +format CR[16] : Inst16Format { + fields: + unsigned func4[4]; + unsigned rs1[5]; + unsigned rs2[5]; + unsigned op[2]; +}; + +format CB[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm3[3]; + unsigned rs1p[3]; + unsigned imm5[5]; + unsigned op[2]; + overlays: + unsigned func2[2] = [11, 10]; + unsigned func5[5] = [12..10, 6..5]; + unsigned shamt[6] = [12, 6..2]; + unsigned rs2p[3] = [4..2]; + unsigned rs2[5] = 0b10, [4..2]; + signed bimm[9] = imm3[2], imm5[4..3, 0], imm3[1..0], imm5[2..1], 0b0; +}; + +format CI[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm1[1]; + unsigned rs1[5]; + unsigned imm5[5]; + unsigned op[2]; + overlays: + unsigned rd[5] = rs1; + signed imm6[6] = imm1, imm5; + unsigned uimm6[6] = imm1, imm5; + signed imm18[18] = imm1, imm5, 0b0000'0000'0000; + signed ci_imm10[10] = imm1, imm5[2..1, 3, 0, 4], 0b0000; + unsigned ci_imm_w[8] = imm5[1..0], imm1, imm5[4..2], 0b00; + unsigned ci_imm_d[9] = imm5[2..0], imm1, imm5[4..3], 0b000; +}; + +format CIW[16] : Inst16Format { + fields: + unsigned func3[3]; + unsigned imm8[8]; + unsigned rdp[3]; + unsigned op[2]; + overlays: + unsigned rd[5] = 0b01, rdp; + unsigned ciw_imm10[10] = imm8[5..2, 7..6, 0, 1], 0b00; +}; + +format CA[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned func2[2]; + unsigned fs2p[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rs2[5] = 0b01, fs2p; + unsigned rd[5] = 0b01, rs1p; +}; + + +format CLB[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned uimm2[2]; + unsigned rdp[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rd[5] = 0b01, rdp; +}; + +format CLH[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned func1[1]; + unsigned uimm1[1]; + unsigned rdp[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rd[5] = 0b01, rdp; + unsigned uimm2[2] = uimm1, 0b0; +}; + +format CMMV[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned func2[2]; + unsigned rs2p[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rs2[5] = 0b01, rs2p; +}; + +format CMPP[16] : Inst16Format { + fields: + unsigned func8[8]; + unsigned rlist[4]; + unsigned spimm[2]; + unsigned op[2]; +}; + + +format CSB[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned uimm2[2]; + unsigned rs2p[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rs2[5] = 0b01, rs2p; +}; + +format CSH[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned func1[1]; + unsigned uimm1[1]; + unsigned rs2p[3]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rs2[5] = 0b01, rs2p; + unsigned uimm2[2] = uimm1, 0b0; +}; + +format CU[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned rs1p[3]; + unsigned func5[5]; + unsigned op[2]; + overlays: + unsigned rs1[5] = 0b01, rs1p; + unsigned rd[5] = 0b01, rs1p; +}; + +format CMJT[16] : Inst16Format { + fields: + unsigned func6[6]; + unsigned index[8]; + unsigned op[2]; +} + +format CMopType[16] : Inst16Format { + fields: + unsigned func4[4]; + unsigned num[5]; + unsigned rd[5]; + unsigned op[2]; +};
diff --git a/riscv/riscv_format32.bin_fmt b/riscv/riscv_format32.bin_fmt new file mode 100644 index 0000000..83a6e87 --- /dev/null +++ b/riscv/riscv_format32.bin_fmt
@@ -0,0 +1,243 @@ +// Copyright 2025 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#once + +// This file defines the 32 bit instruction formats for the RISC-V encodings. + +format Inst32Format[32] { + fields: + unsigned bits[25]; + unsigned opcode[7]; +}; + +format RType[32] : Inst32Format { + fields: + unsigned func7[7]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + unsigned r_uimm5[5] = rs2; +}; + +// Format for shift immediate for RV64, note 6 bit immediate. +format RSType[32] : Inst32Format { + fields: + unsigned func6[6]; + unsigned r_uimm6[6]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; +}; + +format R4Type[32] : Inst32Format { + fields: + unsigned rs3[5]; + unsigned func2[2]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; +}; + +format IType[32] : Inst32Format { + fields: + signed imm12[12]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + unsigned u_imm12[12] = imm12; + unsigned i_uimm5[5] = rs1; +}; + +format SType[32] : Inst32Format { + fields: + unsigned imm7[7]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned imm5[5]; + unsigned opcode[7]; + overlays: + signed s_imm[12] = imm7, imm5; +}; + +format BType[32] : Inst32Format { + fields: + unsigned imm7[7]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned imm5[5]; + unsigned opcode[7]; + overlays: + signed b_imm[13] = imm7[6], imm5[0], imm7[5..0], imm5[4..1], 0b0; +}; + +format UType[32] : Inst32Format { + fields: + unsigned imm20[20]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + unsigned u_imm[32] = imm20, 0b0000'0000'0000; +}; + +format JType[32] : Inst32Format { + fields: + unsigned imm20[20]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + signed j_imm[21] = imm20[19, 7..0, 8, 18..9], 0b0; +}; + +format Fence[32] : Inst32Format { + fields: + unsigned fm[4]; + unsigned pred[4]; + unsigned succ[4]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; +}; + +format AType[32] : Inst32Format { + fields: + unsigned func5[5]; + unsigned aq[1]; + unsigned rl[1]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; +}; + +format F12Type[32] : Inst32Format { + fields: + unsigned func12[12]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; +}; + +format ZICBOP[32] : Inst32Format { + fields: + unsigned offset[7]; + unsigned func5[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned imm5[5]; + unsigned op[7]; + overlays: + unsigned bop_uimm12[12] = offset, 0b00000; +} + +format MopRType[32] : Inst32Format { + fields: + unsigned func1[1]; + unsigned n_hi[1]; + unsigned func2[2]; + unsigned n_mid[2]; + unsigned func4[4]; + unsigned n_lo[2]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + unsigned mop_no[5] = n_hi, n_mid, n_lo; +}; + +format MopRRType[32] : Inst32Format { + fields: + unsigned func1h[1]; + unsigned n_hi[1]; + unsigned func2[2]; + unsigned n_lo[2]; + unsigned func1l[1]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + unsigned mop_no[3] = n_hi, n_lo; +}; + +// Vector instruction formats. + +format VMem[32] : Inst32Format { + fields: + unsigned nf[3]; + unsigned mew[1]; + unsigned mop[2]; + unsigned vm[1]; + unsigned rs2[5]; + unsigned rs1[5]; + unsigned width[3]; + unsigned vd[5]; + unsigned opcode[7]; + overlays: + unsigned lumop[5] = rs2; + unsigned sumop[5] = rs2; + unsigned vs2[5] = rs2; + unsigned vs3[5] = vd; +}; + +format VArith[32] : Inst32Format { + fields: + unsigned func6[6]; + unsigned vm[1]; + unsigned vs2[5]; + unsigned vs1[5]; + unsigned func3[3]; + unsigned vd[5]; + unsigned opcode[7]; + overlays: + unsigned uimm5[5] = vs1; + unsigned uimm6[6] = func6[0], vs1; + unsigned func5[5] = func6[5..1]; + signed simm5[5] = vs1; + unsigned rd[5] = vd; + unsigned rs1[5] = vs1; + unsigned vd_mask[5] = vd; +}; + +format VConfig[32] : Inst32Format { + fields: + unsigned top12[12]; + unsigned rs1[5]; + unsigned func3[3]; + unsigned rd[5]; + unsigned opcode[7]; + overlays: + signed zimm11[11] = top12[10..0]; + unsigned func1[1] = top12[11]; + unsigned func2[2] = top12[11..10]; + unsigned func7[7] = top12[11..5]; + signed zimm10[10] = top12[9..0]; + unsigned uimm5[5] = rs1; + unsigned rs2[5] = top12[4..0]; +};
diff --git a/riscv/riscv_vector.bin_fmt b/riscv/riscv_vector.bin_fmt index 11a1db0..1c76737 100644 --- a/riscv/riscv_vector.bin_fmt +++ b/riscv/riscv_vector.bin_fmt
@@ -12,62 +12,9 @@ // See the License for the specific language governing permissions and // limitations under the License. +#include "riscv/riscv_format32.bin_fmt" + // RiscV vector instruction encodings. - -format VMem[32] : Inst32Format { - fields: - unsigned nf[3]; - unsigned mew[1]; - unsigned mop[2]; - unsigned vm[1]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned width[3]; - unsigned vd[5]; - unsigned opcode[7]; - overlays: - unsigned lumop[5] = rs2; - unsigned sumop[5] = rs2; - unsigned vs2[5] = rs2; - unsigned vs3[5] = vd; -}; - -format VArith[32] : Inst32Format { - fields: - unsigned func6[6]; - unsigned vm[1]; - unsigned vs2[5]; - unsigned vs1[5]; - unsigned func3[3]; - unsigned vd[5]; - unsigned opcode[7]; - overlays: - unsigned uimm5[5] = vs1; - unsigned uimm6[6] = func6[0], vs1; - unsigned func5[5] = func6[5..1]; - signed simm5[5] = vs1; - unsigned rd[5] = vd; - unsigned rs1[5] = vs1; - unsigned vd_mask[5] = vd; -}; - -format VConfig[32] : Inst32Format { - fields: - unsigned top12[12]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - signed zimm11[11] = top12[10..0]; - unsigned func1[1] = top12[11]; - unsigned func2[2] = top12[11..10]; - unsigned func7[7] = top12[11..5]; - signed zimm10[10] = top12[9..0]; - unsigned uimm5[5] = rs1; - unsigned rs2[5] = top12[4..0]; -}; - instruction group RiscVVInst32[32] : Inst32Format { //opcfg : VArith : func6 == 0bxxx'xxx, func3 == 0b111, opcode == 0b101'0111; vsetvli_xn : VConfig : rs1 != 0, func1 == 0, func3 == 0b111, opcode == 0b101'0111;
diff --git a/riscv/riscv_zc.bin_fmt b/riscv/riscv_zc.bin_fmt index 2a9ce58..8bcb1a8 100644 --- a/riscv/riscv_zc.bin_fmt +++ b/riscv/riscv_zc.bin_fmt
@@ -15,98 +15,15 @@ // This file refactors the original "C" extension into the new set of Zc* // extensions. These should be preferred for new simulator targets. +#include "riscv/riscv_format16.bin_fmt" + // Compact instruction formats. - -format CLB[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned uimm2[2]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rd[5] = 0b01, rdp; -}; - -format CLH[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func1[1]; - unsigned uimm1[1]; - unsigned rdp[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rd[5] = 0b01, rdp; - unsigned uimm2[2] = uimm1, 0b0; -}; - -format CMMV[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func2[2]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, rs2p; -}; - -format CMPP[16] : Inst16Format { - fields: - unsigned func8[8]; - unsigned rlist[4]; - unsigned spimm[2]; - unsigned op[2]; -}; - - -format CSB[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned uimm2[2]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, rs2p; -}; - -format CSH[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func1[1]; - unsigned uimm1[1]; - unsigned rs2p[3]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rs2[5] = 0b01, rs2p; - unsigned uimm2[2] = uimm1, 0b0; -}; - -format CU[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned rs1p[3]; - unsigned func5[5]; - unsigned op[2]; - overlays: - unsigned rs1[5] = 0b01, rs1p; - unsigned rd[5] = 0b01, rs1p; -}; - // Non floating point compact instructions from "C". instruction group RiscVCZca[16] : Inst16Format { caddi4spn : CIW: func3 == 0b000, op == 0b00, imm8 != 0; clw : CL : func3 == 0b010, op == 0b00; - csw : CS : func3 == 0b110, op == 0b00; + csw : CS : func3 == 0b110, op == 0b00;ß cnop : CI : func3 == 0b000, imm1 == 0, rs1 == 0, imm5 == 0, op == 0b01; caddi : CI : func3 == 0b000, imm6 != 0, rd != 0, op == 0b01; cjal : CJ : func3 == 0b001, op == 0b01; @@ -179,13 +96,6 @@ cm_mva01s : CMMV : func6 == 0b101'011, func2 == 0b11, op == 0b10; } -format CMJT[16] : Inst16Format { - fields: - unsigned func6[6]; - unsigned index[8]; - unsigned op[2]; -} - // Jump table instructions. instruction group RiscVCZcmt[16] : Inst16Format { cm_jt : CMJT : func6 == 0b101'000, index < 32, op == 0b10;
diff --git a/riscv/riscv_zicbop.bin_fmt b/riscv/riscv_zicbop.bin_fmt index 312248a..f665825 100644 --- a/riscv/riscv_zicbop.bin_fmt +++ b/riscv/riscv_zicbop.bin_fmt
@@ -15,17 +15,7 @@ // This file defines the encoding for the cache prefetch instructions in the // Zicbop extension. -format ZICBOP[32] : Inst32Format { - fields: - unsigned offset[7]; - unsigned func5[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned imm5[5]; - unsigned op[7]; - overlays: - unsigned bop_uimm12[12] = offset, 0b00000; -} +#include "riscv/riscv_format32.bin_fmt" instruction group RiscVZicbop[32] : Inst32Format { prefetch_i : ZICBOP : func5 == 0b00000, func3 == 0b110, imm5 == 0b00000, op == 0b001'0011;
diff --git a/riscv/riscv_zimop.bin_fmt b/riscv/riscv_zimop.bin_fmt index 20edaaf..9ed0c8a 100644 --- a/riscv/riscv_zimop.bin_fmt +++ b/riscv/riscv_zimop.bin_fmt
@@ -14,37 +14,8 @@ // This file contains the encoding for the Zimop and Zcmop instructions. -format MopRType[32] : Inst32Format { - fields: - unsigned func1[1]; - unsigned n_hi[1]; - unsigned func2[2]; - unsigned n_mid[2]; - unsigned func4[4]; - unsigned n_lo[2]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned mop_no[5] = n_hi, n_mid, n_lo; -}; - -format MopRRType[32] : Inst32Format { - fields: - unsigned func1h[1]; - unsigned n_hi[1]; - unsigned func2[2]; - unsigned n_lo[2]; - unsigned func1l[1]; - unsigned rs2[5]; - unsigned rs1[5]; - unsigned func3[3]; - unsigned rd[5]; - unsigned opcode[7]; - overlays: - unsigned mop_no[3] = n_hi, n_lo; -}; +#include "riscv/riscv_format32.bin_fmt" +#include "riscv/riscv_format16.bin_fmt" instruction group RiscVZimop[32] : Inst32Format { mop_r_0: MopRType : mop_no == 0, func1 == 0b1, func2 == 0b00, func4 == 0b0111, func3 == 0b100, opcode == 0b111'0011; @@ -89,13 +60,6 @@ mop_rr_7: MopRRType : mop_no == 7, func1h == 0b1, func2 == 0b00, func1l == 0b1, opcode == 0b111'0011; }; -format CMopType[16] : Inst16Format { - fields: - unsigned func4[4]; - unsigned num[5]; - unsigned rd[5]; - unsigned op[2]; -}; instruction group RiscVZcmop[16] : Inst16Format { c_mop_1: CMopType : func4 == 0b0110, num == 1, rd == 0, op == 0b01;