mpact/sim/decoder/test/testfiles/format_error.bin_fmt

// Copyright 2023 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

decoder ErrorTest {
  namespace sim::syntax_error;
  opcode_enum = "sim::OpcodeEnum";
  RiscVGInst32;
  X;
  Z;
  ZFormat;
  RiscVGInst32;                      // Error: multiple references to one group.
  GroupA;
  opcode_enum = "";                  // Error: empty opcode enum string.
  opcode_enum = "sim::OpcodeEnum";   // Error: multiple opcode_enums.
  namespace sim::errors;             // Error: multiple namespace decls.
};

// Duplicate decoder.
decoder ErrorTest {
  namespace sim::syntax_error;
  opcode_enum = "sim::OpcodeEnum";
  RiscVGInst32;
};

format Inst32Format[32] {
  fields:
    unsigned bits[25];
    unsigned opcode[7];
  overlays:
    unsigned overlayx[65] = bits, opcode, 0b1, opcode, bits;  // overlay > 64.
};

format BType[32] : Inst32Format {
  fields:
    unsigned imm7[7];
    unsigned rs2[5];
    // Duplicate field names - field not counted in width - generates width 
    // error too.
    unsigned rs2[5];
    unsigned func3[3];
    unsigned imm5[5];
    unsigned opcode[7];
  overlays:
    // Overlay name duplicates field name.
    signed imm7[7] = 0b111'1111;
    // Undefined field reference, will not be counted in width. Generates
    // width error too.
    signed b_imm[13] = imm7[6], imm5[0], imm7[5..0], immX[4..1], 0b0;
    unsigned overlay0[9] = imm7, 0b00;
    // Duplicate overlay name.
    unsigned overlay0[9] = imm7, 0b00;
};

format XFormat[32] {
  fields:
    unsigned bits[32];
};

// Inherited width differs.
format YFormat[36] : Inst32Format {
  fields:
    unsigned bits[36];
};

format ZFormat[32] : Inst32Format {
  fields:
    unsigned bits[32];
};

// Duplicate format.
format ZFormat[32] : Inst32Format {
  fields:
    unsigned bits[32];
};

format Format33[33] {
  fields:
    unsigned bits[33];
};

instruction group RiscVGInst32[32] : ZFormat {
  beq    : BType  : func3 == 0b000, opcode == 0b110'0011;
  bne    : BType  : func3 == 0b001, opcode == 0b110'0011;
  blt    : BType  : func3 == 0b100, opcode == 0b110'0011;
  bge    : BType  : func3 == 0b101, opcode == 0b110'0011;
  bltu   : BType  : func3 == 0b110, opcode == 0b110'0011;
  bgeu   : BType  : func3 == 0b111, opcode == 0b110'0011;
  // Format not derived from Inst32Format.
  none_0 : XFormat : bits == 0;
  // Using format not derived from ZFormat.
  none_1 : YFormat : bits == 0;
  // Format doesn't exist.
  none_2 : None : bits == 0;
  // Format of different length.
  none_3 : Format33 : bits == 0;
};

// Duplicate instruction group.
instruction group RiscVGInst32[32] : Inst32Format {
  beq    : BType  : func3 == 0b000, opcode == 0b110'0011;
  bne    : BType  : func3 == 0b001, opcode == 0b110'0011;
  blt    : BType  : func3 == 0b100, opcode == 0b110'0011;
  bge    : BType  : func3 == 0b101, opcode == 0b110'0011;
  bltu   : BType  : func3 == 0b110, opcode == 0b110'0011;
  bgeu   : BType  : func3 == 0b111, opcode == 0b110'0011;
};

// Error: format width differs from width of instruction group.
instruction group Z[34] : Inst32Format {
  // Error: width of none_4 different from declared width of instruction group.
  none_4 : Inst32Format : bits == 0;
};

// Illegal use of format identifier.
instruction group ZFormat[32] : Inst32Format {
  none_5 : Inst32Format : bits == 0;
};

// Format too wide.
format Inst72Format[72] {
  fields:
    unsigned bits[72];
};

// Instruction group too wide.
instruction group X[72] : Inst72Format {
  none_6 : Inst72Format : bits == 0;
};

format TypeA {    // No width or inherited format specified.
  fields:
    unsigned bits[25];
    unsigned opcode[7];
}

format TypeB : TypeX {    // Parent format does not exist.
  fields:
    unsigned bits[25];
    unsigned opcode[7];
}

instruction group GroupA[32] : Inst32Format {
  inst_0 : TypeA : opcode == 0b000'0000;
  inst_1 : TypeB : opcode == 0b000'0001;
}