mpact/sim/decoder/test/testfiles/example.isa

// Copyright 2023 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

// Define an isa with two bundles.
isa Example {
  namespace sim::example::isa;
  bundles {
    bundle_a;
    bundle_b;
  }
}

int const1 = 1;
int my_const = const1 + 2;

// Try some include files.
// Include file relative to test execution directory.
#include "mpact/sim/decoder/test/testfiles/include/empty_include.isa"
#include "mpact/sim/decoder/test/testfiles/include/bundle_a.isa"

// This file is passed as another source file in invocation arguments.
// #include "mpact/sim/decoder/test/testfiles/bundle_b.isa"

template<int base, int mult>
slot a_side_ops {
  int base_plus_1 = base + 1;
  int mult_plus_2 = mult + my_const;
  default attributes = { one, two = 3, three = base, four = base_plus_1, five = 0};
  opcodes {
    vctsf{(pred : sy : %reloc(dest)(base_plus_1))};
    cvtfs{(pred : sy : dest(base + 1))};
    adds{(pred : sy, sx : dest(base))},
      attributes: {five = 1, six};
    push{(pred : [rlist]: )};
    pop{(pred : : [rlist])};
    addf{(pred : sy, sx : dest(base))};
    subf{(pred : sy, sx : dest(base))};
    mulf{(pred : sy, sx : dest(mult_plus_2))};
    mulu{(pred : sy, sx : dest(mult + 1))};
  }
}

slot a_side  {
  opcodes {
    nop{()};
    delay{(pred : const)};
    settag{()};
    fence{()};
  }
}

slot a_side_0 : a_side, a_side_ops<2, 2> {
  default opcode =
    semfunc: "[](Instruction *) {}";
  opcodes {
    settag = delete;
    addf = delete;
    subf = delete;
    br_abs{()};
    br_rel{()};
    br_ind{()};
    call_abs{()};
    call_rel{()};
    call_ind{()};
  }
}

slot a_side_1 : a_side, a_side_ops<1, 4> {
  default opcode =
    semfunc: "[](Instruction *) {}";
  opcodes {
    ld{(pred : %reloc(yop) : ),(: : dest)},
      disasm:"%dest = sld %pred [smem:%yop]";
    ld_offset{(pred : xop, yop : dest(abs(-2)))};
    st{(pred)};
    mulf = delete;
    mulu = delete;
  }
}

slot other {
  default opcode =
    semfunc: "[](Instruction *) {}";
}

slot b_side_alu[4] {
  default opcode =
    semfunc: "[](Instruction *) {}";
}

slot b_side_store {
  default opcode =
    semfunc: "[](Instruction *) {}";
}

slot b_side_load[2] {
  default opcode =
    semfunc: "[](Instruction *) {}";
}

slot b_side_load_2 {
  default opcode =
    semfunc: "[](Instruction *) {}";
}