mpact/sim/decoder/test/testfiles/generator.isa

// Copyright 2023 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

disasm widths = {-18};

isa Generator {
  namespace sim::generator::isa;
  slots { branches; }
}

slot branches {
  default size = 4;
  default latency = 0;
  default opcode =
    disasm: "Illegal instruction at 0x%(@:08x)",
    semfunc: "[](Instruction *) {}";
  opcodes {
    // This should generate entries for beq, bne, blt, bltu, be, bgeu, along
    // with the "W" types with the appropriate string substitutions for 
    // $(btype), $(w) and $(fcn_w).
    GENERATE( btype = [ "eq", "ne", "lt", ltu, ge, geu],
             [w, fcn_w, unused] = [{"", "", 1}, {".w", _w, 2}] ) {
      b$(btype)$(fcn_w){: rs1, rs2, B_imm12 : next_pc},
        resources: { next_pc, rs1, rs2 : next_pc[0..]},
        disasm: "b$(btype)$(w)", "%rs1, %rs2, %(@+B_imm12:08x)",
        semfunc: "&sem_func_b$(btype)$(fcn_w)";
    };
  }
}