| // Copyright 2023 Google LLC |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // https://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| |
| // RiscV 32 bit G instruction decoder. |
| decoder RiscV32G { |
| namespace mpact::sim::riscv::encoding; |
| opcode_enum = "isa32::OpcodeEnum"; |
| includes { |
| #include "third_party/mpact_riscv/riscv32g_decoder.h" |
| } |
| RiscVGInst32; |
| RiscVCInst16; |
| }; |
